KR100488151B1 - Driving Method for Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that enables low voltage driving.

A method of driving a plasma display panel of the present invention includes supplying a ramp ramp waveform rising to a setup voltage with a slope to a first electrode during a setup period of an initialization period, and pairing with the first electrode during the setup period. Supplying a reset voltage to the second electrode, supplying a ramp ramp waveform falling from the set-up voltage with a slope to the first electrode during the set-down period of the initialization period, and supplying to the second electrode during the set-down period. Supplying a sustain scan voltage greater than the reset voltage.

Description

Driving method for plasma display panel {Driving Method for Plasma Display Panel}

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to enable low voltage driving.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. FIG. Electrodes X1 to Xm are provided.

At the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z, and the address electrodes X1 to Xm, a cell 1 for displaying any one of red, green, and blue is formed. Scan electrodes Y1 to Yn and sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period (reset period) for initializing the full screen, an address period for selecting a scan line and selecting a cell from the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period (reset period), the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. At the same time, 0 [V] is applied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up causes the setup discharge to occur between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

On the other hand, a surface discharge occurs between the scan electrode Y and the sustain electrode Z during the setup discharge, and an opposite discharge occurs between the scan electrode Y and the address electrode X. The double-sided discharge supplies a lot of light toward the observer located in front of the PDP, thereby reducing the contrast of the PDP. On the other hand, the light generated in the opposite discharge has a relatively small amount of light propagated toward the observer compared to the surface discharge.

In the set-down period SD, after the rising ramp waveform Ramp-up is supplied, it starts to fall at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up, and thus the base voltage GND or the negative polarity is specified. A falling ramp waveform Ramp-down falling to the voltage level is applied to the scan electrodes Y simultaneously. At the same time, a positive sustain voltage Vs is applied to the sustain electrode Z, and 0 [V] is applied to the address electrode X. When the falling ramp waveform Ramp-down is applied in this way, fine discharge occurs between the scan electrode Y and the sustain electrode Z. FIG. Further, no discharge occurs between the scan electrode Y and the address electrode Z in the section in which the falling ramp waveform Ramp-down falls, but discharge occurs at the lower limit of the falling ramp waveform Ramp-down.

The discharge occurring in the set down period SD eliminates unnecessary excessive wall charges generated in the address discharge generated in the setup period SU. Looking at the wall charge change in the setup period SU and the setdown period SD, there is almost no change in the wall charge on the address electrode X, and the negative (−) wall charge of the scan electrode Y decreases. On the other hand, the wall charge of the sustaining electrode Z was positive in the set-up period SU, but the negative wall charge accumulated in itself by the decrease of the negative wall charge of the scan electrode Y, and thus the set-down period At (SD), its polarity is reversed to negative polarity.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied.

The sustain electrode Z is supplied with a positive polarity DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference from the scan electrode Y so as to prevent erroneous discharge from the scan electrode Y.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, ramp waveforms having a small pulse width and a low voltage level are supplied to the sustain electrode Z to erase wall charges remaining in the cells of the full screen.

However, the conventional PDP is reduced on the scan electrode (Y) by the discharge of the set-down period (SD) and the remaining amount of the wall charge is small, so the voltage level of the voltage (Vd, Vscan) supplied from the outside during the address discharge can be increased. There is nothing else. In addition, since the conventional PDP has a small wall charge on the sustain electrode Z, which is accumulated during the discharge of the setdown period SD, the voltage of the sustain pulse su supplied from the outside during the sustain period, that is, the sustain voltage Vs, becomes high. There is no choice but to. In addition, there is a problem that the contrast of the PDP is lowered due to the surface discharge generated between the scan electrode Y and the sustain electrode Z during the setup period SU.

Accordingly, an object of the present invention is to provide a method of driving a plasma display panel which enables low voltage driving.

In order to achieve the above object, the driving method of the plasma display panel according to the present invention includes supplying a rising ramp waveform rising to a setup voltage with a slope to a first electrode during a setup period of an initialization period, and during the setup period. Supplying a reset voltage to a second electrode paired with an electrode, supplying a ramp ramp waveform falling from the set-up voltage with a slope to the first electrode during the set-down period of the initialization period, and the set-down period Supplying a sustain scan voltage greater than the reset voltage to the second electrode.

The setup period includes a section that rises to a setup voltage and a section that maintains the elevated setup voltage.

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And supplying a scan signal to the first electrode and supplying a data signal to a third electrode crossing the first and second electrodes to select a cell.

After the scan signals are supplied to all of the first electrodes, the voltage of the first electrode is gradually lowered from the common scan voltage. The falling ramp waveform is a voltage that falls from the set-up voltage to the common scan voltage. Same as the sustain scan voltage.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 5.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 4, the driving method of the PDP according to the first embodiment of the present invention is an initialization period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. Drive by dividing by.

In the initialization period (reset period), a rising ramp waveform Ramp-up that rises with a predetermined slope from the common scan voltage Vscan_com to the setup voltage Vsetup is applied to all the scan electrodes Y simultaneously. At the same time, the Z reset voltage Vz_reset (a voltage of 0 V or more, preferably 30 V or more) lower than the Z scan voltage Vz_scan is applied to the sustain electrode Z. When the rising ramp waveform Ramp-up and the Z reset voltage Vz_reset are applied to the scan electrodes Y and the sustain electrodes Z, discharges are concentrated between the scan electrodes Y and the address electrodes X. Is generated. In other words, since the positive Z reset voltage Vz_reset is applied to the sustain electrodes Z, no discharge occurs between the scan electrode Y and the sustain electrode Z (the voltage value of the Z reset voltage Vz_reset). Fine discharge may occur), and the discharge is concentrated between the scan electrode Y and the address electrode X. When the discharge is concentrated between the scan electrode Y and the address electrode X, a large number of negative (-) wall charges are accumulated on the scan electrode Y, and a large number of positive polarities ( +) Wall charges will accumulate.

After that, the positive common scan voltage Vscan_com is simultaneously applied to the scan electrodes Y, and the same Z scan voltage Vz_scan is simultaneously applied to the sustain electrodes Z as the common scan voltage Vscan_com. It begins. Since the same voltages Vscan-com and Vz-scan are simultaneously applied to the scan electrode Y and the sustain electrode Z at the beginning of the address period, there is no potential difference between the scan electrode Y and the sustain electrode Z. Subsequently, a scan pulse falling to the negative scan voltage Vscan is sequentially applied to the scan electrodes Y, and a data pulse rising to the positive data voltage Vdata in synchronization with the scan pulse scan. (data) is applied to the address electrodes (X). As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. On the other hand, since the discharge is concentrated between the scan electrode Y and the address electrode X during the initialization period, that is, a large number of wall charges are formed, the voltage values of the data voltage Vdata and the scan voltage Vscan can be lowered. have.

At the end of the address period, the voltage on the scan electrode Y gradually falls to 0 [V] or the base voltage. As a result, the slope voltage SLP lowered to a predetermined slope erases part of the excess wall charge on the scan electrode Y which is not necessary for the sustain discharge by the address discharge.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, an erase signal in the form of a square wave or a ramp wave having a small pulse width for erasing wall charges generated by the sustain discharge is supplied.

As a result, in the driving method of the PDP according to the first embodiment of the present invention, since the PDP is initialized only by the setup discharge by omitting the conventional set-down period, the initialization time can be reduced. In addition, by supplying the Z reset voltage Vz_reset to the sustain electrode Z, the setup discharge can be concentrated between the scan electrode Y and the address electrode X. Accordingly, a large number of wall charges can be generated. Y) and the address electrode X can be stacked. Therefore, the voltage value of the external drive voltage required for the address period can be significantly lowered. In addition, since the surface discharge is weakly generated or the surface discharge does not occur between the scan electrode Y and the sustain electrode Z during the initialization period, the contrast can be improved.

On the other hand, in the driving method of the PDP according to the first embodiment of the present invention, in order to form sufficient wall charges on the scan electrode Y and the address electrode X during the initialization period, the voltage value of the setup voltage Vsetup is increased. You must set it. When the voltage value of the setup voltage Vsetup is set high, sufficient wall charges are formed between the scan electrode Y and the address electrode X, thereby lowering the voltage value of the external driving voltage required for the address period.

However, when the voltage value of the setup voltage Vsetup is set high, self-erase occurs in the cells at the moment when the voltage falls from the setup voltage Vsetup to the common scan voltage Vscan_com. When self erase discharge occurs in the cells, the wall charges formed in the initialization period are recombined, so that a high voltage must be supplied in the address period. For example, in the first embodiment of the present invention, there is a problem in that the data voltage Vdata is set to 130V or more. In order to solve this problem, a driving method according to the second embodiment of the present invention as shown in FIG. 5 is proposed.

5 is a waveform diagram showing a method of driving a plasma display panel according to a second embodiment of the present invention.

Referring to FIG. 5, the driving method of the PDP according to the second embodiment of the present invention is an initialization period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. Drive by dividing by.

In the initialization period (reset period), in the setup period SU, a rising ramp waveform Ramp-up1 rising to a predetermined slope from the common scan voltage Vscan_com to the setup voltage Vsetup1 is applied to all the scan electrodes Y. It is applied at the same time. At the same time, the Z reset voltage Vz_reset (a voltage of 0 V or more, preferably 30 V or more) lower than the Z scan voltage Vz_scan is applied to the sustain electrode Z. When the rising ramp waveform Ramp-up1 and the Z reset voltage Vz_reset are applied to each of the scan electrodes Y and the sustain electrodes Z, discharge is concentrated between the scan electrodes Y and the address electrodes X. Is generated.

In other words, since the positive Z reset voltage Vz_reset is applied to the sustain electrodes Z, no discharge occurs between the scan electrode Y and the sustain electrode Z (the voltage value of the Z reset voltage Vz_reset). Fine discharge may occur), and the discharge is concentrated between the scan electrode Y and the address electrode X. When the discharge is concentrated between the scan electrode Y and the address electrode X, a large number of negative (-) wall charges are accumulated on the scan electrode Y, and a large number of positive polarities ( +) Wall charges will accumulate.

On the other hand, the setup period SU may be divided into a section that rises to the setup voltage Vsetup1 with a predetermined slope and a section that maintains the setup voltage Vsetup1. Here, the Z reset voltage Vz_reset is applied to both the rising section and the holding section.

Subsequently, in the set-down period SD of the initialization period (reset period), the falling ramp waveform Ramp-down falling from the setup voltage Vsetup1 to the common scan voltage Vscan_com with a predetermined slope is applied to all scan electrodes ( Is simultaneously applied to Y). At the same time, a Z scan voltage Vz_scan is applied to the sustain electrode Z. In this way, when a ramp ramp (down ramp) descending from the setup voltage (Vsetup1) to the common scan voltage (Vscan_com) with a predetermined slope is applied to all the scan electrodes (Y), the self-erase discharge occurs. It does not occur. In other words, when the falling ramp waveform Ramp-down having a predetermined falling slope is supplied, self erase discharge is not generated in the scan electrodes Y. Therefore, in the second embodiment of the present invention, the voltage value of the setup voltage Vsetup1 can be set higher than the voltage value of the setup voltage Vsetup shown in Fig. 5 (Vsetup1> Vsetup). When the voltage value of is set high, many wall charges may be formed in the cells during the initialization period.

During the address period, the common scan voltage Vscan_com is simultaneously applied to the scan electrodes Y, and the same Z scan voltage Vz_scan as the common scan voltage Vscan_com is simultaneously applied to the sustain electrodes Z. Since the same voltages Vscan-com and Vz-scan are simultaneously applied to the scan electrode Y and the sustain electrode Z at the beginning of the address period, there is no potential difference between the scan electrode Y and the sustain electrode Z. Subsequently, a scan pulse falling to the negative scan voltage Vscan1 is sequentially applied to the scan electrodes Y, and a data pulse rising to the positive data voltage Vdata1 in synchronization with the scan pulse scan. (data) is applied to the address electrodes (X). As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied.

In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. On the other hand, since the discharge is concentrated between the scan electrode Y and the address electrode X during the initialization period, that is, a large number of wall charges are formed, the voltage values of the data voltage Vdata1 and the scan voltage Vscan1 can be lowered. have. Particularly, in the second embodiment of the present invention, since the wall value is set high by setting the voltage value of the setup voltage Vsetup1 high, the voltage values of the data voltage Vdata1 and the scan voltage Vscan1 are shown in FIG. It can be lower than the first embodiment of the present invention shown.

At the end of the address period, the voltage on the scan electrode Y gradually falls to 0 [V] or the base voltage. As a result, the slope voltage SLP lowered to a predetermined slope erases part of the excess wall charge on the scan electrode Y which is not necessary for the sustain discharge by the address discharge.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, an erase signal in the form of a square wave or a ramp wave having a small pulse width for erasing wall charges generated by the sustain discharge is supplied.

As a result, in the driving method of the PDP according to the second embodiment of the present invention, a large value of wall charges can be formed during the initialization period by setting the voltage value of the setup voltage Vsetup1 high. In addition, it is possible to prevent the self-erasure discharge from occurring by supplying a falling ramp waveform Ramp-down that falls from the setup voltage Vsetup1 to the common scan voltage Vscan_com with a predetermined slope during the setdown period. In addition, by supplying the Z reset voltage Vz_reset to the sustain electrode Z, the setup discharge can be concentrated between the scan electrode Y and the address electrode X. Accordingly, a large number of wall charges can be generated. Y) and the address electrode X can be stacked. Therefore, the voltage value of the external drive voltage required for the address period can be significantly lowered. In addition, since the surface discharge is weakly generated or the surface discharge does not occur between the scan electrode Y and the sustain electrode Z during the initialization period, the contrast can be improved.

As described above, according to the driving method of the plasma display panel according to the present invention, low voltage driving is possible by accumulating a sufficient amount of wall charges on the scan electrode and the sustain electrode in the initialization period.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform for driving a conventional PDP.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention;

5 is a waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

1: cell

Claims (7)

A driving method of a plasma display panel including an initialization period, Supplying a ramp ramp waveform rising to the setup voltage with a slope to the first electrode during the setup period of the initialization period; Supplying a reset voltage to a second electrode paired with the first electrode during the setup period; Supplying a falling ramp waveform falling from the set-up voltage with a slope to the first electrode during the set-down period of the initialization period; And supplying a sustain scan voltage greater than the reset voltage to the second electrode during the set down period. The method of claim 1, And the setup period includes a section that rises to the setup voltage and a section that maintains the elevated setup voltage. delete The method of claim 1, And supplying a scan signal to the first electrode and supplying a data signal to a third electrode crossing the first and second electrodes to select a cell. The method of claim 4, wherein And gradually lowering the voltage of the first electrode from the common scan voltage after the scan signals are supplied to all the first electrodes. The method of claim 1, And the falling ramp waveform is a voltage falling from the set-up voltage to a common scan voltage. The method of claim 6, And wherein the common scan voltage is the same as the sustain scan voltage.