KR100505976B1 - Method and apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel to prevent abnormal discharge generated from a non-display area and to improve image quality.

A method and apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention provide a first driving signal including a scan pulse to a first electrode and a second driving signal different from the first driving signal to the first electrode. After supplying the second electrode to drive the plasma display panel, the plasma display panel is driven by supplying the first driving signal to the second electrode and simultaneously supplying the second driving signal to the first electrode.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel to improve image quality by preventing abnormal discharge generated from a non-display area.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP includes a sustain electrode pair including a scan electrode (Y) and a sustain electrode (Z) formed on the upper substrate 1, and a lower portion perpendicular to the sustain electrode pair. An address electrode X formed on the substrate 2 is provided. Each of the scan electrode Y and the sustain electrode Z is composed of a transparent electrode and a metal bus electrode formed thereon. The upper dielectric layer 6 and the MgO protective layer 7 are stacked on the upper substrate 1 on which the scan electrode Y and the sustain electrode Z are formed. The lower dielectric layer 4 is formed on the lower substrate 2 on which the address electrode X is formed to cover the address electrode X. FIG. A partition 3 is formed vertically on the lower dielectric layer 4. Phosphors 5 are formed on the surfaces of the lower dielectric layers 4 and the partition walls 3. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space provided between the upper substrate 1, the lower substrate 2, and the partition wall 3. The upper substrate 1 and the lower substrate 2 are bonded by a real material not shown.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. The initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling ramp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. After the rising ramp waveform Ramp-up is supplied in the set-down period SD, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The sustain electrode Z is supplied with a positive DC voltage Zdc during the set down period and the address period. The DC voltage Zdc causes a setdown discharge between the sustain electrode Z and the scan electrode Y in the setdown period, and a large discharge occurs between the scan electrode Y and the sustain electrode Z in the address period. The voltage difference between the sustain electrode Z and the scan electrode Y or between the sustain electrode Z and the address electrode X is set.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, a ramp waveform (erase) having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

On the other hand, as shown in Figs. 4 and 5, the PDP has a display area 31 in each of the upper non-display area 32 located on the upper outer side of the display area 31 and the lower non-display area 33 located on the lower outer side. A discharge space having the same structure as that of the discharge cell is formed. That is, the address electrode X and the pair of dummy electrodes UD1, UD2, BD1, and BD2 are formed in each of the upper non-display area 32 and the lower non-display area 33, and the electrodes X, UD1, UD2, Dielectric layers 4 and 6 are formed to cover BD1 and BD2. The dummy electrodes UD1, UD2, BD1, and BD2 formed in the upper non-display area 32 and the lower non-display area 33 respectively generate a discharge in the non-display area during the aging process, thereby causing the display area 31 to be discharged. The discharge characteristics of the discharge cells of the first horizontal line and the n-th horizontal line of the display area 31 are stabilized under the same conditions as the other discharge cells of. To this end, a voltage capable of causing a discharge during the aging process is applied to the dummy electrodes UD1, UD2, BD1, and BD2, and no voltage is applied after the aging process.

However, the conventional PDP has a problem in that discharge is accidentally generated from the upper non-display area 32 and the lower non-display area 33. Such discharges are defined as abnormal discharges. In detail, when a discharge such as an initialization discharge, an address discharge, and a sustain discharge occurs during the operation of the PDP, the space charges generated by the discharge are generated on the dielectric of the upper non-display area 32 and the lower non-display area 33. It is stored. For example, as shown in FIG. 5, the negative scanning pulse scan is sequentially shifted to the scan electrodes Y1 to Yn as shown in FIG. 5, and the positive space charge 52 moves toward the lower non-display area 33. At the same time, the negative space charge 51 moves toward the upper non-display area 32. The space charges 51 and 52 moved to the non-display areas 32 and 33 are accumulated on the dielectric layers 4 and 6 in the non-display areas 32 and 33. As shown in FIG. 6, when the wall voltage 61 rising due to the wall charges accumulated on the non-display areas 32 and 33 is equal to or higher than the voltage Vf sufficient to cause discharge, the non-display areas 32 and 33 An abnormal discharge occurs between the address electrode X and the scan electrode Y or the sustain electrode Z in the matrix. As a result of this abnormal discharge, visible light 71 from the non-display areas 32 and 33 is diffused above or below the display area 31 and recognized by the viewer. As a result, the display quality of the PDP is degraded due to the abnormal discharge.

Accordingly, it is an object of the present invention to provide a method and apparatus for driving a PDP to improve image quality by preventing abnormal discharge generated from a non-display area.

In order to achieve the above object, a method of driving a PDP according to an embodiment of the present invention includes a ramp waveform in an initialization period for initializing a full screen, and includes a scan pulse in an address period for selecting a cell and for a selected cell. Generating a first drive signal including a sustain pulse in a sustain period for displaying; Maintaining a DC voltage in an initialization period and an address period and generating a second driving signal including the sustain pulse in a sustain period; Supplying a first driving signal to the first electrode and simultaneously supplying a second driving signal to a second electrode facing the first electrode to drive the plasma display panel; And supplying a first driving signal to the second electrode and simultaneously supplying the second driving signal to the first electrode to drive the plasma display panel.

The method of driving a PDP according to an embodiment of the present invention further includes selecting a cell by applying data to address electrodes orthogonal to the first and second electrodes so as to be synchronized with the scan pulse.

In the driving method of the PDP according to the embodiment of the present invention, the driving signals supplied to the first and second electrodes are alternately arranged in subfield units or frame period units included in one frame period between the first and second driving signals. It is characterized by alternating.

A driving apparatus of a PDP according to an embodiment of the present invention includes a plasma display panel having a first electrode and a second electrode facing each other; The first electrode includes a first driving signal including a ramp waveform in an initialization period for initializing a full screen, a scan pulse in an address period for selecting a cell, and a sustain pulse in a sustain period for displaying a selected cell. A first electrode driver for supplying a second drive signal including a sustain pulse to the first electrode during the sustain period and maintaining a DC voltage in the initialization period and the address period after supplying to the first electrode; and supplying the second drive signal to the second electrode. And a second electrode driver for supplying a first driving signal to the second electrode after the supply.

The driving apparatus of the PDP according to the embodiment of the present invention further includes a data driver for applying data to address electrodes orthogonal to the first and second electrodes so as to be synchronized with the scan pulse.

In the driving apparatus of the PDP according to the embodiment of the present invention, the driving signals supplied to the first and second electrodes are alternately or subframe units included in one frame period between the first and second driving signals. It is characterized by alternating.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 10.

Referring to FIG. 8, a driving device of a PDP according to an embodiment of the present invention includes a data driver 82 for supplying data to data lines X1 to Xm, and scan / sustain electrodes in subfield or frame units. Scan / sustain driver 83 for supplying different drive signals to Y-Z1 to YZ, and sustain / scan paired with scan / sustain electrodes Y-Z1 to Y-Zn on a subfield or frame basis. A sustain / scan driver 84 for supplying different drive signals to the electrodes Z-Y1 to Z-Yn, and a timing controller 81 for controlling each of the drivers 82, 83, and 84 are provided.

The data driver 82 performs inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then latches the data mapped to each subfield by one line by a subfield mapping circuit, not shown. Next, the latched data is simultaneously supplied to the data lines X1 to Xm.

The scan / sustain driver 83 supplies the rising ramp waveform and the falling ramp waveform to the scan / sustain electrodes Y-Z1 to Y-Zn during the initialization period in the odd (or even) subfield or odd (or even) frame. Then, scan pulses for selecting scan lines in the address period are sequentially supplied to the scan electrodes Y-Z1 to Y-Zn, and sustain pulses for generating display discharge during the sustain period are scanned electrodes Y-Z1. To Y-Zn) at the same time. In addition, the scan / sustain driver 83 supplies a DC voltage to the scan / sustain electrodes Y-Z1 to Y-Zn during the set-down period and the address period in the even (or odd) subfield or the even (or odd) frame. After that, a sustain pulse for causing display discharge is simultaneously supplied to the scan electrodes Y1 to Yn.

The sustain / scan driver 84 supplies the rising ramp waveform and the falling ramp waveform to the sustain / scan electrodes Z-Y1 to Z-Yn during the initialization period in the even (or odd) subfield or the even (or odd) frame. After that, the scan pulses for selecting the scan line in the address period are sequentially supplied to the sustain / scan electrodes Z-Y1 to Z-Yn, and the sustain pulses for sustaining display discharge in the sustain period are supplied. It is supplied to (Z-Y1 to Z-Yn) at the same time. In addition, the sustain / scan driver 84 supplies a DC voltage to the sustain / scan electrodes Z-Y1 to Z-Yn during the setdown period and the address period in the odd (or even) subfield or odd (or even) frame. After that, a sustain pulse for causing display discharge is simultaneously supplied to the sustain / scan electrodes Z-Y1 to Z-Yn.

As a result, the scan / sustain electrodes Y-Z1 to Y-Zn are scanned electrodes in odd (or even) subfields or odd (or even) frames as compared to the conventional three-electrode surface discharge PDP shown in FIG. On the other hand, it serves as a sustain electrode in the even (or odd) subfield or the even (or odd) frame. The sustain / scan electrodes Z-Y1 to Z-Yn serve as electrodes facing the scan / sustain electrodes Y-Z1 to Y-Zn. That is, the sustain / scan electrodes Z-Y1 to Z-Yn serve as scan electrodes in even (or odd) subfields or even (or odd) frames as compared to conventional three-electrode surface discharge PDPs. It serves as a sustain electrode in the odd (or even) subfield or odd (or even) frame. For example, the sustain / scan electrodes Z-Y1 to Z-Yn serve as a sustain electrode opposite to each other when the scan / sustain electrodes Y-Z1 to Y-Zn serve as scan electrodes. When the scan / sustain electrodes Y-Z1 to Y-Zn serve as scan electrodes, the scan / sustain electrodes Y-Z1 to Y-Zn serve as a sustain electrode opposite thereto.

The timing controller 81 receives a vertical / horizontal synchronization signal, generates a timing control signal required for each driver 82, 83, 84, and supplies the timing control signal to each driver 82, 83, 84. do.

9 shows driving waveforms generated from the driving apparatus of the PDP according to the embodiment of the present invention.

Referring to FIG. 9, a PDP according to an embodiment of the present invention is driven by being divided into an initialization period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initializing period of the k-th subfield SFk or the k-th frame FRk, the rising ramp waveform Ramp- rises to a peak voltage higher than the sustain voltage during the setup period SU. up) is simultaneously applied to all scan / sustain electrodes YZ. The rising ramp waveform (Ramp-up) causes discharge in the cells of the full screen, and as a result, positive wall charges are accumulated on the address electrode (X) and the sustain / scan electrode (ZY), and the scan / sustain electrode ( On the YZ), negative wall charges are accumulated. In the set-down period SD of the k-th subfield SFk or the k-th frame FRk, a falling ramp waveform Ramp-down falling to the base voltage GND is simultaneously applied to the scan / sustain electrodes YZ. Excessively formed wall charges in the cells are erased. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period of the k-th subfield SFk or the k-th frame FRk, the negative scan pulses are sequentially applied to the scan / sustain electrodes YZ and synchronized with the scan pulses. Positive data pulse data is applied to field X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied.

During the set down period SD and the address period of the k-th subfield SFk or the k-th frame FRk, a positive DC voltage Z-Ydc is supplied to the sustain / scan electrode Z-Y.

In the sustain period of the k-th subfield SFk or the k-th frame FRk, the sustain pulse su is alternately applied to the scan / sustain electrodes Y-Z and the sustain / scan electrodes Z-Y. The cell selected by the address discharge has sustain voltage discharge between the scan / sustain electrode YZ and the sustain / scan electrode ZY whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. That is, display discharge occurs. At the end of the k-th subfield SFk or the k-th frame FRk, the wall charges generated during the sustain discharge are erased by the small ramp waveforms supplied to the sustain / scan electrodes Z-Y.

In the k + 1th subfield SFk + 1 or the k + 1th frame FRk + 1, the scan / sustain electrode YZ and the sustain / scan electrode ZY each play a role in the kth subfield SFk. It is opposite to the kth frame FRk.

In the initialization period of the k + 1th subfield SFk + 1 or the k + 1th frame FRk + 1, the ramp-up ramps up to a peak voltage higher than the sustain voltage during the setup period SU. Is applied to all the sustain / scan electrodes ZY simultaneously. Discharge is generated in the cells of the full screen by the rising ramp waveform Ramp-up, and as a result, positive wall charges are accumulated on the address electrode X and the sustain / scan electrode ZY, and the scan / sustain electrode YZ On the wall, negative wall charges are accumulated. In the setdown period SD of the k + 1th subfield SFk + 1 or the k + 1th frame FRk + 1, the ramp ramp down to the ground voltage GND is sustained / scanned. The wall charges excessively formed in the cells by being applied to the cells ZY are erased at the same time. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period of the k + 1th subfield SFk + 1 or the k + 1th frame FRk + 1, the negative scan pulse scan is sequentially applied to the sustain / scan electrodes ZY and the scan pulse is simultaneously applied. In synchronization with (scan), a positive data pulse (data) is applied to the address electrodes (X). As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied.

During the set down period SD and the address period of the k + 1th subfield SFk + 1 or the k + 1th frame FRk + 1, the scan / sustain electrode YZ has a positive DC voltage (Y-Zdc). Is supplied.

In the sustain period of the k + 1th subfield SFk + 1 or the k + 1th frame FRk + 1, the sustain pulses are alternately applied to the scan / sustain electrodes YZ and the sustain / scan electrodes ZY. sus) is authorized. The cell selected by the address discharge has sustain voltage discharge between the scan / sustain electrode YZ and the sustain / scan electrode ZY whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen. At the end of the k + 1th subfield (SFk + 1) or the k + 1th frame (FRk + 1), a wall generated during sustain discharge by a small ramp waveform (erase) supplied to the sustain / scan electrode (ZY). The charge is erased.

As such, the roles of the scan / sustain electrodes Z-Y and the sustain / scan electrodes Y-Z are periodically alternated, thereby inverting the polarity of the wall charges accumulated on the non-display areas 32 and 33 in FIG. The wall charges previously accumulated in the non-display areas 32 and 33 are then erased by the space charges or wall charges of opposite polarities supplied thereafter. Accordingly, as shown in FIG. 10, since the wall voltage 101 in the non-display areas 32 and 33 does not continuously rise along the time axis and rises and falls periodically, it is smaller than the voltage Vf that is sufficient to cause discharge. Maintain the voltage level. In FIG. 10, the horizontal axis represents the time axis t, and the vertical axis represents wall voltages in the non-display areas 32 and 33.

On the other hand, the method and apparatus for driving the plasma display panel according to the second embodiment of the present invention alternates the roles of the scan / sustain electrode YZ and the sustain / scan electrode ZY by dividing the subfield or frame into odd and even numbers. The roles of the scan / sustain electrode YZ and the sustain / scan electrode ZY may be alternately divided into successive subfield groups or successive frame groups. For example, if a frame is driven by time division by dividing into eight subfields, the scan pulse is supplied to the scan / sustain electrode YZ during the four subfields arranged at the beginning of the frame, and the four subfields arranged thereafter. The scan pulse is supplied to the sustain / scan electrode ZY. Similarly, scan pulses are supplied to the scan / sustain electrode YZ for i (where i is a positive integer) and sustain / scan for j frames (where j is a positive integer) disposed thereafter. The scan pulse may be supplied to the electrode ZY.

As described above, the method and apparatus for driving a PDP according to the present invention continuously accumulate the wall charges of the same polarity in the non-display area by periodically or aperiodically altering the driving voltages supplied to each of the two opposing electrodes. Do not become. As a result, the method and apparatus for driving a PDP according to the present invention can prevent the wall voltage in the non-display area from rising above a voltage level that can cause a discharge, thereby preventing abnormal discharge generated from the non-display area. .

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform for driving a conventional PDP.

4 is a plan view of a plasma display panel for showing a non-display area.

5 is a cross-sectional view of a plasma display panel for showing a non-display area.

6 is a graph showing a wall voltage continuously rising in the non-display area.

7 is a diagram schematically illustrating visible light generated from a non-display area and recognized in a display area.

8 is a block diagram schematically illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

9 is a waveform diagram illustrating driving signals generated from respective driving units shown in FIG. 8.

FIG. 10 is a graph illustrating wall voltages of non-display areas changed by a method and apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1: upper substrate 2: lower substrate

3: bulkhead 4,6: dielectric layer

5: phosphor 7: protective layer

X: address electrode Y: scan electrode

Z: sustain electrode

Claims (6)

Generating a first drive signal including a ramp waveform in an initialization period for initializing a full screen, a scan pulse in an address period for selecting a cell, and a sustain pulse in a sustain period for displaying a selected cell; Wow; Maintaining a DC voltage in the initialization period and the address period and generating a second driving signal including the sustain pulse in the sustain period; Supplying the first driving signal to a first electrode and simultaneously supplying the second driving signal to a second electrode facing the first electrode to drive a plasma display panel; And supplying the first driving signal to the second electrode and simultaneously supplying the second driving signal to the first electrode to drive the plasma display panel. The method of claim 1, And selecting a cell by applying data to address electrodes orthogonal to the first and second electrodes so as to be synchronized with the scan pulse. The method of claim 1, The driving signals supplied to the first and second electrodes are alternated in units of subfields included in one frame period or alternately in units of frame periods between the first and second driving signals. Way. A plasma display panel having a first electrode and a second electrode facing each other; A first driving signal including a ramp waveform in an initialization period for initializing a full screen, a scan pulse in an address period for selecting a cell, and a sustain pulse in a sustain period for displaying a selected cell; A first electrode driver for maintaining a DC voltage in the initialization period and the address period after supplying the electrode, and supplying a second driving signal including the sustain pulse to the first electrode in the sustain period; And a second electrode driver configured to supply the first driving signal to the second electrode after the second driving signal is supplied to the second electrode. The method of claim 4, wherein And a data driver for applying data to address electrodes orthogonal to the first and second electrodes so as to be synchronized with the scan pulse. The method of claim 4, wherein The driving signals supplied to the first and second electrodes are alternated in units of subfields included in one frame period or alternately in units of frame periods between the first and second driving signals. Device.