KR100765526B1 - Plasma display device and driving method of the same - Google Patents

Abstract

The present invention relates to a plasma display device and a method of driving the same, which can reduce manufacturing costs and prevent damage and malfunction of the data driver.

A plasma display device according to the present invention includes a plasma display panel for displaying an image, a data driver for supplying a data pulse consisting of a first voltage and a second voltage to an address electrode of the plasma display panel, and the first and second voltages. And a driving voltage generator for supplying the data driver to the data driver.

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

1 is a diagram illustrating a subfield pattern of an 8-bit default code for implementing 256 gray levels in a PDP.

2 is a diagram illustrating a conventional PDP driving waveform.

3 is a diagram illustrating an electrode arrangement of a general plasma display panel.

FIG. 4 is a view schematically illustrating a driving signal applied to electrodes and a selected discharge cell in an address period in the plasma display apparatus of FIG. 3.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a driving waveform of the plasma display device shown in FIG. 5.

FIG. 7 is a diagram for describing selection of a discharge cell by the driving waveform of FIG. 6.

<Description of the symbols for the main parts of the drawings>

1, 54: discharge cell 2, 56: data driver

60: scan driver 62: sustain driver

64: timing controller 66: drive voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device and a method of driving the same, which can reduce manufacturing costs and prevent damage and malfunction of a data driver.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Ne + Xe is discharged. Display an image. Such PDPs are not only thin and large in size, but also have improved image quality due to recent technology development.

1 is a diagram illustrating a subfield pattern of an 8-bit default code for implementing 256 gray levels in a PDP.

Referring to FIG. 1, the PDP performs time division driving by dividing one frame into several subfields having different emission counts in order to implement grayscale of an image. Each subfield includes a reset period for initializing the full screen, an address period for selecting a scan line and selecting a discharge cell in the selected scan line, an address period for selecting a scan line and selecting a discharge cell in the selected scan line, and It is divided into sustain periods for implementing gradation according to the number of discharges. For example, when displaying an image in 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period RP, an address period AP, and a sustain period SP as described above. In this case, while the reset period RP and the address period AP of each subfield are the same for each subfield, the sustain period and the number of sustain pulses allocated thereto are 2n (n = 0, 1, 2, 3, 4, 5, 6, 7) is increased.

2 is a diagram illustrating a conventional PDP driving waveform.

Referring to FIG. 2, each of the subfields SF includes a reset period RP for initializing the discharge cells of the full screen, an address period AP for selecting the discharge cells, and a sustain for discharging the selected discharge cells. It includes a period SP.

In the reset period RP, the rising ramp waveform PR is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. After the rising ramp waveform PR is applied in the set-down period SD, the positive sustain voltage Vs lower than the peak voltage of the rising ramp waveform PR to the negative scan voltage Vs is negative. The falling ramp waveform NR falling at a predetermined slope is simultaneously applied to the scan electrodes Y. The falling ramp waveform NR generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, thereby uniformly retaining wall charges required for address discharges in the cells of the full screen.

In the address period AP, a negative scan pulse SCNP is sequentially applied to the scan electrodes Y, and a positive data pulse DP is applied to the address electrodes. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive sustain voltage Vs is applied to the sustain electrodes Z during the set down period SD and the address period AP.

In the sustain period SP, a sustain pulse SSUS is applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SSUS is applied while the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge occurs. Here, the sustain pulses SSP have the same voltage value as the sustain voltage Vs.

3 is a diagram illustrating an electrode arrangement of a general plasma display panel.

In FIG. 3, the discharge cell 1 is configured at each intersection of scan electrode lines Y1 to Yn, sustain electrode lines Z1 to Zn, and address electrode lines (or data electrode lines X1 to Xm). Able to know.

The scan electrode lines Y1 to Yn supply scan pulses and sustain pulses so that the discharge cells 1 are scanned in units of lines, and the discharges are maintained in the discharge cells 1.

The sustain electrode lines Z1 to Zn commonly supply a sustain pulse to maintain the discharge in the discharge cells 1 together with the scan electrode lines Y1 to Yn. The address electrode lines X1 to Xm supply data pulses synchronized with the scan pulses in line units so that the discharge cells 1 in which discharges are to be maintained are selected according to the logic value of the data pulses.

As shown in FIGS. 2 and 3, the plasma display apparatus includes a scan signal SCNP sequentially applied to the scan electrode lines Y and an data signal supplied to the address electrode lines X in the address period AP. The discharge cell 1 is selected by the address signal.

FIG. 4 is a view schematically illustrating a driving signal applied to electrodes and a selected discharge cell in an address period in the plasma display apparatus of FIG. 3.

Referring to FIG. 4, the scan signal SCNP is sequentially supplied to the scan electrode lines in order to select a discharge cell in which the display discharge is to be generated in the address period AP. At the same time, the data pulse DP is supplied to the address electrode lines X. That is, while the scan signal SCNP is supplied to the first scan electrode line Y1, the positive data pulse DP is supplied to the first and third discharge cells R1 and B1 to perform the display discharge. The data pulse DP is not supplied to the second discharge cell G1 in which no display discharge occurs.

At this time, address discharge is generated in the first and third discharge cells R1 and B1 by the scan signal SCNP and the data pulse DP. The address discharge is generated by the difference between the potential (-Vy) of the negative scan signal SCNP and the potential Va of the data pulse DP of the positive polarity and the wall charge.

The data pulse DP is supplied to the address electrode lines X by the data driver 2 shown in FIG. 4. The data driver 2 supplies the signal voltages Va and GND supplied from a driving voltage generator (not shown) in synchronization with a control signal CS supplied from an external control circuit such as a timing controller (not shown). ) Is supplied to the address electrode lines X by switching.

However, the conventional PDP has a large voltage difference between the high logic value potential Va and the low logic value potential GND of the data pulse DP. In particular, the high logic value and the low logic value of the conventional PDP have a potential difference of several tens of volts [V] to several hundred volts [V]. The difference between the low and high logic values of the data pulse DP leads to the burden on the data driver 2 for processing the data pulse DP. Such a burden causes the breakdown voltage rating of the data driver 2 to have a voltage resistance large enough to withstand the high voltage of the data pulse DP. . That is, the data driver 2 has a breakdown voltage rating that is larger than the voltage Va of the high logic value of the data pulse DP, which causes a problem in that the manufacturing cost increases when the data driver 2 is manufactured. In addition, due to the high breakdown voltage, a large amount of heat is generated in the data driver 2 of the conventional PDP, and the heat damage and malfunction of the device are frequently caused by such heat.

Accordingly, it is an object of the present invention to provide a plasma display device and a method of driving the same, which can reduce manufacturing costs and prevent damage and malfunction of the data driver.

In order to achieve the above object, a plasma display device according to the present invention is a plasma display panel for displaying an image, a data driver for supplying a data pulse consisting of a first voltage and a second voltage to the address electrode of the plasma display panel and the And a driving voltage generator configured to generate a first voltage and a second voltage and supply the first and second voltages to the data driver.

The first voltage is greater than the base voltage and less than the second voltage.

The first voltage is larger than the base voltage and is smaller than the voltage obtained by subtracting the magnitude of the scan voltage and the wall charge voltage involved in the discharge from the discharge start voltage at which discharge occurs.

A driving method of a plasma display device according to the present invention is a method of driving a plasma display device in which one subfield is divided into a reset period, an address period, and a sustain period, wherein a negative scan pulse is applied to a scan electrode during the address period. And supplying a data pulse composed of a first polarity voltage and a second voltage to the address electrode in synchronization with the scan pulse during the address period.

The first voltage is greater than the base voltage and less than the second voltage.

And supplying the first voltage to the address electrode during the reset period and the sustain period.

The first voltage is greater than the base voltage and is characterized by being a voltage smaller than the voltage of the discharge start voltage at which the discharge occurs, minus the voltage size of the wall charges involved in the scan pulse and discharge.

Other objects and features of the present invention in addition to the above objects will be revealed through a detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 5 to 7.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 52, a red color R, and a green color G for displaying an image. And a data driver 56 for supplying red (R), green (G), and blue (B) data to the address electrodes X1 to Xm of the discharge cells 54 coated with the blue (B) phosphor. A scan driver 60 for driving the scan electrodes Y1 to Yn, a sustain driver 62 for driving the sustain electrodes Z, and a timing controller for controlling each driver 56, 60, 62 ( 64) and a driving voltage generator 66 for supplying driving voltages necessary for each of the driving units 56, 60, and 62.

The PDP 52 includes an upper substrate on which the scan electrodes Y1 to Yn and the sustain electrodes Z are formed, and a lower substrate on which the address electrodes X1 to Xm are formed. In the PDP 52, discharge cells 54 are formed in an area where scan electrodes Y1 to Yn, sustain electrodes Z, and address electrodes X1 to Xm cross each other. Phosphors of red (R), green (G), and blue (B) are coated inside the discharge cell 54, and supplied from the data driver 56, 58, the scan driver 60, and the sustain driver 62. It is driven by a slow drive waveform.

The data driver 56 samples and latches the red (R), green (G), and blue (B) data in response to the timing control signal Cx supplied from the timing controller 64, and then red (R), green. The second data voltage Va, which is the data voltage of the (G) and blue (B) data, may be converted into the address electrodes of the discharge cells 54 coated with the red (R), green (G), and blue (B) phosphors. X1 to Xm). Here, the data driver 56 can be driven by being divided into the first and the second data driver 56, and the data driver at this time is provided in the top, bottom, left and right of the PDP 52. That is, when the first data driver supplies data of any two colors among red (R), green (G), and blue (B) to some of the address electrodes (X1 to Xm), the second data driver may have one remaining color. Data can be supplied to the remaining address electrodes X1 to Xm for driving.

Here, the data driver 56 is supplied to the data driver 56 with the first voltage Va, which is a positive bias voltage, for reducing the breakdown voltage due to the voltage applied by the second voltage Va. In this case, the first voltage Vab supplied to the data driver 56 has a voltage in a range larger than the base voltages GND and 0V and smaller than the size of the second voltage Va. The first voltage Vab, which is supplied to the data driver 56, reduces the voltage difference Va-Vab from the data voltage Va to reduce the breakdown voltage applied to the data driver 56, but reduces the second voltage. Since the voltage difference Va-Vy between (Va) and the scan voltage Vy of the scan pulse SCNP has the same magnitude as before, the address discharge is normally performed. A detailed description thereof will be described later with reference to FIG. 6.

The scan driver 60 supplies the initialization waveforms to the scan electrodes Y1 to Yn during the reset period RP in response to the timing control signal Cy supplied from the timing controller 64 and then during the address period AP. The scan bias voltage Vsc is supplied and the scan pulse SCNP is sequentially supplied. The scan driver 60 supplies the sustain pulse SUSP to the scan electrodes Y1 to Yn during the sustain period SP in response to the timing control signal Cy supplied from the timing controller 64.

The sustain driver 62 has a positive sustain voltage of positive polarity on the sustain electrodes Z during the setdown period Sd and the address period AP in response to the timing control signal Cz supplied from the timing controller 64. After the supply of Vs, the sustain pulse SUSP is alternately supplied with the scan driver 60 during the sustain period SP.

The timing controller 64 receives the vertical / horizontal synchronization signal and the clock signal to generate timing control signals Cx, Cy, and Cz necessary for each of the driving units 56, 58, 60, and 62, and the timing control signals Cx, Each drive unit 56, 58, 60, 62 is controlled by supplying Cy and Cz to the drive units 56, 58, 60, 62. At this time, the data control signal Cx includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element. In addition, the scan control signal Cy includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 60. The sustain control signal Cz includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 62.

The driving voltage generator 66 generates a setup voltage Vsetup, a negative scan voltage Vy, a scan bias voltage Vsc, and a sustain voltage Vs of positive polarity (+) to generate a scan driver 60 and It supplies to the sustain drive part 62. In addition, the driving voltage generator 66 generates a data voltage Va corresponding to red (R), green (G), and blue (B) data and supplies the data voltage Va to the data driver 56. In addition, the driving voltage generator 66 supplies the data driver 56 with the first voltage Va, which is a positive (+) bias voltage, for reducing the voltage withstand voltage caused by the second voltage Va.

On the other hand, Equation 1 is a formula showing the relationship between the second voltage (Va), the scan voltage (Vy), the wall charge voltage (Vwall) and the discharge start voltage (Vf) for the address discharge.

As a condition for the discharge in the discharge cells selected in the address period AP as shown in Equation 1, the sum of the voltage magnitudes of the second voltage Va, the scan voltage Vy, and the wall charge voltage Vwall starts discharge. It must be greater than the voltage. That is, when the sum of the voltage magnitudes of the second voltage Va, the scan voltage Vy, and the wall charge voltage Vwall becomes larger than the discharge start voltage Vf, an address discharge is performed and a sustain discharge is to be generated. Is selected.

Similarly, the scan voltage Vy and the second voltage Va are not applied to the offcells in which the sustain discharge is not generated, so that a voltage smaller than the discharge start voltage Vf is maintained. This is shown in Equation 2.

That is, only the first voltage Vab, the wall charge voltage Vwall, and the scan voltage Vy are applied to the address electrodes X1 to Xm, so that the voltages required for discharge are the second voltage Va and the first voltage. It becomes insufficient as the difference voltage of (Vab). As a result, even when the first voltage Vab is applied, no discharge occurs in the off cells.

Therefore, the magnitude of the first voltage Vab is defined as in Equation 3.

That is, the first voltage Vab is larger than the conventional ground voltage GND, and has a voltage smaller than the magnitude of the voltage obtained by subtracting the scan voltage Vy and the wall voltage Vwall from the discharge start voltage Vf. It is preferable.

As such, the first voltage Vab does not generate discharge in a period when the data pulse DP is not applied, and should be determined within a range that can most effectively reduce the voltage breakdown voltage applied to the data driver 56. do.

FIG. 6 is a diagram illustrating a driving waveform of the plasma display apparatus illustrated in FIG. 5, and FIG. 7 is a diagram for describing selection of a discharge cell by the driving waveform of FIG. 6.

6 and 7, the PDP of the present invention includes a reset period RP for initializing the discharge cells 3 on the full screen, an address period AP for selecting a cell, and selected discharge cells ( And a sustain period SP for maintaining the discharge of 3).

In the setup period SU during the reset period RP, the rising ramp waveform PR is applied to all the scan electrodes Y, the ground voltage 0V is applied to the sustain electrodes Z, and the address electrodes The first voltage Vab of positive polarity is applied to X). Here, the first voltage Va has a voltage value greater than the base voltage 0V and less than the second voltage Va, which is a data voltage. Accordingly, in the setup period SU, dark discharge is generated in which light is hardly generated between the scan electrodes Y and the address electrodes X in the cells of the full screen by the rising ramp waveform PR. At the same time, dark discharge occurs between the scan electrodes (Y) and the sustain electrodes (Z). As a result of this dark discharge, positive wall charges remain on the address electrodes X and the sustain electrodes Z immediately after the setup period SU, and negative wall charges remain on the scan electrodes Y. Will remain.

Following the set-up period SU, in the set-down period SD of the reset period RP, the falling ramp waveform NR, which descends by a predetermined slope from the sustain voltage Vs to the negative erase voltage Ve, is scanned. To Y1 to Yn. At the same time, a positive sustain voltage Vs is applied to the sustain electrodes Z1 to Zn, and a first voltage Vab is applied to the address electrodes X. Accordingly, the dark discharge is generated between the scan electrodes Y and the address electrodes X in the discharge cells 3 of the full screen by the falling ramp waveform NR, and simultaneously with the scan electrodes Y Dark discharge also occurs between the sustain electrodes Z. As a result of the dark discharge in this set-down period SD, the wall charge distribution in each of the discharge cells 3 changes to the optimum condition of the address. That is, the excess wall charges unnecessary for the address discharge are erased on the scan electrodes Y and the address electrodes X in the respective discharge cells 3, and a certain amount of wall charges remains. The wall charges on the sustain electrodes Z are inverted from the positive to the negative polarity as the negative wall charges transferred from the scan electrodes Y accumulate.

In the address period AP, the negative scan signal SCNP is sequentially applied to the scan electrodes Y, and at the same time, the positive data pulse DP is applied to the address electrodes X in synchronization with the scan signal SCNP. The positive sustain voltage Vs or the lower positive bias voltage Vzb is applied to the sustain electrodes Z. Here, the scan signal SCNP is a scan voltage Vsc lowered from the base voltage 0V or the negative scan bias voltage Vyb close thereto to the negative scan voltage -Vy. Accordingly, an address discharge is generated between the scan electrodes Y and the address electrodes X in the on-cells to which the scan voltage Vsc and the data voltage Va are applied during the address period AP. Is generated.

In the sustain period SP, the sustain pulse SSUS of the sustain voltage level Vs is alternately applied to the scan electrodes Y and the sustain electrodes Z, and the first voltage Vab is applied to the address electrodes X. ) Is applied. Then, in the on-cells selected by the address discharge, a sustain discharge is generated between the scan electrodes Y and the sustain electrodes Z every time the sustain pulse SSUS is applied. In contrast, sustain discharge is not generated in the off-cells during the sustain period SP.

As described above, in the plasma display apparatus and the driving method thereof, the address electrodes are applied to the rest of the reset period RP, the sustain period SP, and the address period AP during which the data pulse DP is not applied. Since the first voltage Va which is greater than the base voltage 0V and smaller than the second voltage Va that is the data voltage is applied to X, the breakdown voltage applied to the data driver is reduced.

The breakdown voltage applied to the data driver is reduced by the positive bias voltage Vab applied to the address electrodes X1 to Xm during the period in which the data pulse DP is not applied. That is, unlike the related art, in the present invention, the breakdown voltage applied to the data driver is equal to the difference between the positive bias voltage Vab and the reference voltages 0 [V] and GND, which are continuously maintained at the address electrodes X1 to Xm. As a result, the voltage burden of the data driver is reduced.

In addition, as shown in FIG. 7, it can be seen that the voltage supplied to the data driver 56 is changed to the data voltage Va and the positive bias voltage Va, unlike in the related art. On the other hand, it can be seen that the waveform applied for the operation does not change. That is, the present invention can lower the breakdown voltage rating of the data driver 56 without changing the driving waveform by replacing the base voltage GND supplied to the data driver 56 with the positive bias voltage Vab. This makes it possible to implement the data driver 56 at a lower price than the conventional.

As described above, the plasma display apparatus and the driving method thereof according to the present invention provide a positive bias by supplying a positive bias voltage larger than the base voltage and smaller than the data voltage to the address electrodes for the remaining periods during which no data pulse is supplied during the address period. The breakdown voltage of the data driver may be reduced by a voltage. For this reason, the manufacturing cost of PDP can be reduced. In addition, since the data driver has a low breakdown voltage range, heat generated in the data driver may be reduced. Accordingly, the plasma display device and the driving method thereof of the present invention can prevent damage and malfunction of the driving element.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A plasma display panel for displaying an image; A data driver supplying a data pulse consisting of a first voltage and a second voltage during an address period to an address electrode of the plasma display panel; And A driving voltage generator configured to generate the first voltage and the second voltage and supply the first voltage and the second voltage to the data driver; The first voltage is greater than the base voltage and less than the second voltage, and the first voltage is supplied to the address electrode during the reset period and the sustain period. Plasma display device characterized in that. delete The method of claim 1, And the first voltage is greater than the base voltage and is less than the voltage obtained by subtracting the magnitude of the scan voltage and the wall charge voltage involved in the discharge from the discharge start voltage at which discharge occurs. A driving method of a plasma display apparatus which drives one subfield by dividing it into a reset period, an address period, and a sustain period, Supplying a negative scan pulse to a scan electrode during the address period; And Supplying a data pulse composed of a first polarity voltage and a second voltage to the address electrode in synchronization with the scan pulse during the address period; The first voltage is greater than the base voltage and less than the second voltage, Supplying the first voltage to the address electrode during the reset period and the sustain period. Method of driving a plasma display device, characterized in that. delete delete The method of claim 4, wherein And the first voltage is greater than the base voltage and is less than the voltage of the discharge start voltage from which the discharge is generated, minus the voltage of the wall charges involved in the scan pulse and discharge.

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