JP2003302928A - Plasma display device and driving circuit therefor, and driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device and a driving circuit therefor, a capable of high-luminance and high-gradation display even if pixels are increased in number, and to provide a driving method therefor. <P>SOLUTION: A data driver applies a data pulse Pd and a charge holding pulse Ph to address electrodes superimposing the two kinds of voltage signals. The data pulse Pd is a driving voltage for initiating discharge across the address electrodes and scanning electrodes, and the pulse width is narrower than conventional, for example, 1 μsec or less. The voltage value Vd is set so that the summation with the scanning pulse is higher than a discharge initiating voltage. The charge holding pulse Ph is a driving voltage for holding an electric field so as to sustain the discharge initiated by the application of the data pulse until the particulates charged in the pixel area are increased to a predetermined value. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device for displaying by utilizing an AC plasma discharge, a driving circuit thereof, and a driving method.

[0002]

2. Description of the Related Art Plasma display (PDP: Plasma)
The Display Panel) can be thinned and has a large screen, which is difficult to realize with a cathode ray tube (CRT) that has been widely used in television receivers and computer displays in the past. Expected to be deployed.

FIG. 8 shows the structure of a display panel of a conventional AC type plasma display device. This display panel 100
Has a structure in which a front glass substrate 101 and a rear glass substrate 102 are arranged to face each other, and an electrode pair 10 for discharging for light emission display is provided on the front glass substrate 101 on the display surface side.
7 (sustain electrodes 107X, scan electrodes 107Y) are formed in plural. The electrodes 107X and 107Y are arranged in parallel through a discharge gap, and bus electrodes 110X and 110Y for reducing electric resistance are integrally attached to the electrodes 107X and 107Y, respectively. Further, a dielectric layer 108 and a protective layer 109 are sequentially formed on it.

On the other hand, a plurality of address electrodes 103 are formed on the rear glass substrate 102 so as to be arranged in a direction intersecting with the electrode pairs 107. Address electrode 103
A dielectric layer 104 is formed on the above, and a partition wall 105 for partitioning a space for each address electrode 103 is further formed thereon.
Are formed. Between the partitions 105, red (R; Re
Phosphors 106 of three primary colors of d), green (G; Green) and blue (B; Blue) are periodically formed by coating.

The discharge space sandwiched between the front glass substrate 101 and the rear glass substrate 102 is hermetically sealed at the peripheral edge and filled with discharge gas. Here, when a predetermined voltage is applied to the sustain electrode 107X and the scan electrode 107Y, plasma discharge occurs in the gas between the electrode pair 107. Ultraviolet rays are radiated from this plasma, and when the ultraviolet rays hit the phosphor 106, the pixels emit light.

FIG. 9 is a plan view showing an electrode structure in the display panel 100. Here, the sustain electrodes 107X,
There are n scanning electrodes 107Y (X ₁ , Y ₁ , X ₂ , Y ₂ ,
..., X _n , Y _n ) and m address electrodes 103 (A
₁ , A ₂ , ..., _Am ) are provided and the electrode pair 10
7 and the address electrode 103 intersect to form a matrix of m × n dots having pixels at each intersection, as indicated by the dotted line in FIG. This plasma display device operates by supplying a driving pulse to each electrode from a driving circuit connected to the display panel 100, and turns ON / OF for each pixel.
The control of F (light emission / non-light emission) is usually performed in three steps. Each operation period is called a reset period, an address period, and a sustain (discharge sustaining) period after the operation content.
Taking the selective erasing method as an example, the voltage waveforms shown in FIGS. 10A to 10C are applied to the three electrodes forming the pixel.

During the reset period, all electrodes 107X,
By discharging between the pair of 107Y and uniformly accumulating wall charges in all pixel regions, all the information accumulated in each pixel before that is erased and the entire screen is brought into a uniform charged state.

In the next address period, a binary state is formed depending on the presence / absence of wall charges, and a pixel to emit light is selected. That is, the scan electrodes 107Y (Y ₁ , Y ₂ , ..., Y _n )
, The scanning pulse is sequentially applied at a predetermined timing. At the same time, all m address electrodes 103 (A ₁ , A
₂ , ..., A _m ) each of which emits light of a pixel selected by a combination with the scan electrode 107Y to which a voltage is applied.
A data pulse corresponding to non-light emission (to the non-light emission pixel in this case) is applied in synchronization with the scan timing on the scan electrode 107Y side. As a result, in non-emissive pixels,
Discharge occurs and the wall charges are erased. This operation is called data writing.

Next, during the sustain period, an AC pulse voltage is applied to the pair of electrodes 107X and 107Y in all pixels. At this time, only the pixels in which the wall charges remain selectively reach the discharge start voltage to generate and maintain the discharge, and the light emission is continued during the period.

Thus, the PDP is digitally controlled.
It is designed to display light emission, and as a drive system
The Buffield method is commonly used. Subfield
The method is to display a 1-field display screen on several sub-fees.
Time-division of the light emission time
This is a method of expressing gradation. According to this, shown in FIG.
Thus, the display period (16.7 msec) of one field is N bits
Weighted according to the bit digit of the image data of
Each 2^kN sub-frames that emit light one time (k = 0 to N-1)
It is divided into fields. For example, the image data per pixel
If the data is 8 bits, the display period for one field is
The subfields are divided into subfields SF1 to SF8.
Number of light emission during sustain period of fields SF1 to SF8
Is 2 in order ⁰(1), 2¹(2), 2²(4), ..., 2⁷(128) times
Is set to. ON / OFF of these 8 subfields
When combined with each other, it emits light every 0 to 255 times.
It is possible to display with 256 gradations.

[0011]

Recently, although such a flat-type plasma display device has almost reached the stage of practical application, there is a possibility that the image quality is deteriorated when the number of pixels of the display panel is increased. . The increase in the number of pixels, particularly the number of pixels in the vertical direction, lengthens the address period described above as the number of scan electrodes increases. As a result, the sustain period in each subfield becomes relatively short, and the display brightness decreases. Therefore, if the number of scan electrodes is increased, the sustain period is not sufficiently secured, and it becomes too dark to display at a proper brightness.

This will be described below with a specific example. Since the width of the scanning pulse per scan is generally 2 to 3 μsec, this is assumed to be 3 μsec. Also, for example, V
Since a GA (Video Graphics Array; 640 × 480 pixel number) display panel has 480 scanning electrodes, one address period is 480 × 3 = 1440 (μsec). If this is driven in 8 subfields to realize 256 gradations, an address period of 1440 (μsec) × 8≈11.5 (msec) is required to display a 1-field screen. Become.

On the other hand, a normal TV signal requires about 16.7 msec to transmit image information for one field. In other words, if the display of one image is not completed within this time, the subsequent images cannot be processed. Therefore, the time 16.7-11.5 = 5.2 (msec) obtained by subtracting the address period from the one-field period is the time that can be spent in the reset period and the sustain period. As described above, even in the case of displaying with a general number of pixels, the sustain period is actually shorter than the address period, and sufficient time is not sufficient.

Further, XGA (eXtended Graphics Array;
For a display panel with 1024 × 768 pixels, the address period can be estimated in the same manner as follows: 768 (line) × 3 (μsec) × 8 (SF) ≈1
It becomes 8.4 (msec), which exceeds 16.7 msec in one field. This means that display with 256 gradations is not possible.

Therefore, in the currently commercialized PDP, the number of gradations is reduced, or the screen is divided into upper and lower two blocks as shown in FIG.
The address period is shortened by taking measures such as scanning Y ₁ and 107 Y ₂ at the same time.

In the former case, if the number of gradations is reduced from 256 to 64 for 6 subfields, the address period is 768 (line) × 3 (μsec) × 6 (SF) ≈1.
It becomes 3.8 (msec). On the other hand, in the latter, although the total number of scan electrodes is 2n, writing is performed in the scan time for n lines, and the address period is 768/2 (line) × 3 (μsec) × 8 (SF).
≈9.2 (msec), and the sustain period is finally secured. However, when the number of gradations is reduced, naturally there is a problem that a natural image cannot be displayed because the image quality is inferior, and it cannot be applied to TV display as it is.

Further, when the screen is divided into two, the address electrodes 103A ₁ and 103A ₂ have to be drawn out separately in the upper and lower directions, and the number of driving ICs attached to each address electrode is doubled depending on the number of electrodes. The IC for PDP is expensive, and the cost increase due to this is also a problem. In addition, as the number of electrodes increases, the wiring pitch of the electrodes becomes smaller, and the yield of the flexible substrate used for connecting the display panel itself or the display panel and the drive circuit, and further the yield when connecting the flexible substrate to the display panel is increased. There was a risk of lowering. In addition to such a production problem, in this case, since the split screens are driven independently of each other, there is a problem that discontinuity of images is conspicuous particularly at a boundary between screens when displaying a moving image. As described above, the harmful effect of the screen division was considerably great.

In addition, it is possible to shorten the address period by reducing the width of the drive pulse at the time of writing data and performing the scanning earlier. However, it has been known that the pixel selection function is impaired when the width of the drive pulse applied to the address electrode is shortened. This is because the discharge is stopped before the ions and charges in the pixel space reach a steady state, so that sufficient time cannot be given for the discharge, and the amount of charge held in the pixel does not reach a predetermined amount. by. As a result, the pixels for which writing is insufficient are turned on.
In some cases, / OFF becomes indeterminate, and discharge may or may not occur during the sustain period. this is,
In particular, when displaying a moving image, it causes display noise such as flicker.

The present invention has been made in view of the above problems, and an object thereof is a plasma display device capable of high-luminance and high-gradation display even if the number of pixels is increased, and a driving circuit thereof.
Another object is to provide a driving method.

[0020]

According to a method of driving a plasma display device of the present invention, light emission control of a pixel region is performed by sequentially applying a scan voltage to a scan electrode, and at the same time, an address electrode, an address electrode and a scan electrode are provided. And a first drive voltage for starting discharge between the two, and an electric field is maintained so that the discharge started by applying the first drive voltage is continued until the charged particles inside the pixel region reach a predetermined amount. This is done by applying two kinds of voltages, that is, a second drive voltage for doing so.

The driving circuit of the plasma display device according to the present invention generates the first driving voltage for starting the discharge between the address electrode and the scanning electrode, and applies the first driving voltage to the address electrode. And generating a second drive voltage for holding an electric field so that the discharge started by the application of the first drive voltage is maintained until the charged particles inside the pixel region have a predetermined amount, and the second drive voltage is generated on the address electrode. Second to apply
It is provided with the voltage applying means.

A plasma display device according to the present invention includes a first substrate and a second substrate which are arranged to face each other, a scanning electrode which is provided in parallel on the first substrate and to which a scanning voltage is applied, An address electrode provided on the second substrate so as to cross the scanning electrodes and arranged in parallel with each other, and an address electrode to which a drive voltage for light emission control is applied, and a pixel region provided at an intersection region of the scanning electrodes and the address electrodes. And a driving circuit of the present invention.

In the driving method of the plasma display device according to the present invention, at the time of writing data, the first driving voltage is applied to the address electrode to start the discharge for writing the data, and the second driving voltage is set. Applied to form an electric field
The discharge generated by the first drive voltage is sustained.

In the driving circuit of the plasma display device according to the present invention, the first voltage applying means generates the first driving voltage for starting the discharge between the address electrode and the scanning electrode, and the second voltage is applied. A second means for holding an electric field so that the applying means keeps the discharge started by applying the first drive voltage until the charged particles inside the pixel region have a predetermined amount.
Drive voltage is generated.

In the plasma display device according to the present invention, the driving circuit of the present invention is provided, and display is performed by the driving method of the present invention.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a configuration diagram showing a schematic configuration of a plasma display device according to a first embodiment of the present invention. This plasma display device comprises a display panel 10 and a drive circuit, and the display panel 10 has the same structure as the conventional one. That is, n sustain electrodes 17X
(X ₁ , X ₂ , ..., X _n ) and scan electrode 17Y
An electrode pair 17 made of (Y ₁ , Y ₂ , ..., Y _n ),
m address electrodes 13 (A ₁ , A ₂ , ..., _Am )
Intersect with each other to form an m × n matrix having pixels as pixels at the intersections. In the same figure, a state in which such an electrode structure is viewed from the display surface side is shown.
The X and scan electrodes 17Y are electrically connected to the sustain driver 21, and the address electrodes 13 are electrically connected to the data driver 22. The drive circuit is connected to each electrode of the display panel 10 and outputs a predetermined voltage signal to the driver 2.
In addition to 1 and 22, the video signal processing unit and the control unit are included. Since the latter is configured as in the past, its illustration and description are omitted as appropriate.

The sustain driver 21 applies a reset pulse and a sustain pulse for each electrode pair 17 in the reset period and the sustain period, and applies a scan pulse to the scan electrode 17Y in the address period. The pulse width of this scanning pulse is almost the same as the data pulse Pd described later.

Further, the data driver 22 includes a pulse generation circuit 22A for generating a data pulse and a pulse generation circuit 22B for generating a charge holding pulse, and the pulse generation circuit 22 for each address electrode 13.
Two types of voltage signals, a data pulse Pd and a charge holding pulse Ph generated by A and 22B, are superimposed and applied. In the present embodiment, the data pulse Pd and the charge holding pulse Ph correspond to the "first drive voltage" and the "second drive voltage" of the present invention, respectively, and the pulse generation circuit 22A and the pulse generation circuit 22B. But, "First
"Voltage applying means" and "second voltage applying means".

FIG. 2 is a diagram for explaining the shapes of the data pulse Pd and the charge holding pulse Ph, (A).
6B is a voltage waveform diagram of the address electrode 13 to which the pulse Pd and the pulse Ph are applied in the address period, and FIG. 9B is a voltage waveform diagram of the address electrode in the conventional address period.

The data pulse Pd is a drive voltage for starting discharge between the address electrode 13 and the scan electrode 17Y, and is based on an ON / OFF signal generated from video data, like a normal data signal. The pulse generation circuit 22A outputs data to ON display pixels when writing data and to OFF display pixels when erasing data.
Controlled by. The voltage value Vd of the data pulse Pd is
The sum of the voltage value of the scan pulse is set to be higher than the discharge start voltage between the scan electrode 17Y and the address electrode 13. Further, since the data pulse Pd only has to give a trigger for the discharge, its pulse width can be made narrower than the conventional width of about 2 μsec. Here, the pulse width of the data pulse Pd is, for example, 1 μse.
c or less.

The charge holding pulse Ph is a driving voltage for holding the electric field so that the discharge started by the data pulse application is maintained until the charged particles inside the pixel region have a predetermined amount, and the pulse generation circuit 22B. Is to be applied by. Usually, in each address discharge, it is usually 2 to 3 μm to finish the discharge stably.
Although it takes a few seconds, here, the charge holding pulse Ph is continuously applied to all the address electrodes 13 during the address period, so that the discharge is continued in the pixel region where the discharge is started and is stably ended. ing. For the above reason, the application is continued for 2 to 3 μsec, at least 1 μsec after the scan electrode 17Y in the last column is scanned. The sum of the voltage value Vh of the charge holding pulse Ph and the voltage value of the scan pulse is the scan electrode 17
It is set to be lower than the discharge start voltage between the Y and address electrodes 13.

Next, a method of driving this plasma display device will be described. Here, it is assumed that gradation control is performed by the subfield method, and the basic operations of reset, address, and sustain in each subfield are performed as usual.

3A to 3C are time charts showing drive voltage waveforms (for one subfield) according to the drive method of the present embodiment. First, reset discharge is performed as usual. All sustain electrodes 17X, scan electrodes 17Y
Then, positive and negative pulses are applied from the sustain driver 21 to discharge between the electrode pairs 17. As a result, either the state where the wall charges are formed in all the pixel regions or the state where the charges are erased from all the pixel regions are uniformly formed.

Next, addressing is performed. From the sustain driver 21 to the scan electrodes 17Y (Y ₁ , Y ₂ , ...
, Y _n ) while applying a scanning pulse to the address electrodes 13 (A ₁ , A ₂ , ...) From the data driver 22.
, A _m ), the data pulse Pd synchronized with the scan timing and the charge holding pulse Ph held while scanning all the scan electrodes 17Y are superimposed and applied.

The data pulse Pd is supplied to the data generating circuit 22.
It is generated by A and is applied to the address electrode 13 of the ON display pixel in the case of writing data and in the OFF display pixel in the case of erasing data. Since the voltage values of the data pulse Pd and the scan pulse are set to exceed the discharge start voltage only when a voltage is applied to both electrodes of the scan electrode 17Y and the address electrode 13, the data pulse Pd is applied. The address discharge is generated only in the pixel area. As a result, the display panel 10 is in a state in which the wall charges are selectively formed only in the area of the ON display pixel among the pixels. The widths of the scan pulse and the data pulse Pd at this time are both 1 μs.
ec or less, and the scanning is performed at high speed.

The data pulse Pd is applied only for a short time of 1 μsec or less, which triggers the address discharge, but does not maintain the discharge. Instead, in the present embodiment, the charge holding pulse Ph generated by the data generation circuit 22B is continuously applied to the address electrode 13 and the discharge is maintained in the pixel region after the application of the data pulse Pd, or An electric field is formed so as to promote rapid movement of particles such as electrons and ions generated by the discharge. It should be noted that the charge holding pulse Ph has a predetermined time t of 1 μsec or more (more specifically, 2 to 3 μsec or more) after the scan electrode 17Y in the last column is scanned (the data pulse Pd is finally applied). Is applied for. As a result, the discharge is stably performed for a sufficient period until the charged particles in the pixel area have a predetermined amount. That is, in the selective writing method, a sufficient amount of wall charges are formed in the ON display pixels, and in the selective erasing method, the wall charges are sufficiently erased from the OFF display pixels, and the wall charges are prevented from remaining halfway.

Therefore, although the data writing operation is performed at a high speed, the generation of pixels whose ON / OFF is indefinite is suppressed at this stage.

Next, sustain discharge is performed as usual. That is, all sustain electrodes 17X and scan electrodes 17Y
A sustain pulse is applied from the sustain driver 21 to each of the electrodes to discharge between the electrode pairs 17. Here, since each pixel area holds a regular charge amount according to ON / OFF, it is possible to prevent abnormal discharge from occurring or not to discharge in the ON display pixel. Therefore, the occurrence of display noise such as flicker is suppressed.

As described above, in this embodiment, the data pulse Pd applied for a short time in order to start the discharge.
Then, two kinds of charge holding pulse Ph, which is applied for a sufficiently long time to maintain discharge, are applied to the address electrode 13.
Since the address discharge is performed by superimposing and applying on the address pulse, the scanning time per scan electrode 17Y is shortened according to the pulse width of the data pulse Pd, so that the entire address period can be shortened. Therefore, it is possible to relatively extend the sustain period and improve the display brightness. In addition, display panel 1 only for the shortened address period
The number of scan electrodes of 0 can be increased, and display can be performed without sacrificing high brightness and gradation even in a display panel having more pixels. Also here
Although the width of the data pulse Pd is shortened for scanning, a predetermined amount of wall charge is stably formed in the regular region by the charge holding pulse Ph, and ON / OFF of the pixel is properly determined. It is possible to perform display without noise such as flicker. Thus, by sharing the function of the conventional data pulse with the data pulse Pd and the charge holding pulse Ph, it is possible to achieve both high-speed addressing and stable charge control in the pixel region.

Further, here, since the display panel 10 is constructed in the same manner as the conventional one, there is no need to change from the conventional one except that the data driver 22 is constituted by the pulse generating circuits 22A and 22B. .

[Second Embodiment] FIG. 4 is a block diagram showing a schematic structure of a plasma display device according to a second embodiment of the present invention, and FIG. 5 is a display panel of this plasma display device. Shows the configuration of. The display panel 30 is provided such that the address electrode, which is conventionally one for each pixel, is made up of a predetermined number of two or more. In the plasma display device of the present embodiment, the first
The same components as those of the embodiment will be denoted by the same reference numerals, and the description of the same effects and advantages as those of the first embodiment will be omitted.

The front glass substrate 31 located on the display side is
It is necessary to have high transparency, and for example, high strain point glass or soda lime glass is used. Front glass substrate 31
A plurality of electrode pairs 37 including a sustain electrode 37X and a scan electrode 37Y are provided on the above so as to be in parallel. These electrode pairs 37 are transparent electrodes made of, for example, ITO (Indium-Tin Oxide), and bus electrodes are attached to their respective side edges. Further, a dielectric layer 38 made of, for example, SiO ₂ and a protective layer 39 made of MgO (magnesium oxide) are sequentially provided thereon.

The rear glass substrate 32 is also a plate made of high strain point glass or soda lime glass. Here, on this rear glass substrate 32, for example, A
Two address electrodes 33A and 33B made of a metal thin film such as 1 (aluminum) are arranged so as to form a set for each pixel. These address electrodes 33A, 33B
Are provided so that the extension direction is orthogonal to the extension direction of the electrode pair 37 to form a matrix, and the intersections thereof form the pixel region.

A dielectric layer 34 made of, for example, SiO ₂ (silicon dioxide) is provided on the address electrodes 33A, 33B, and a discharge space is formed on the dielectric layer 34 for forming the address electrodes 33A, 33B. A partition wall 35 for partitioning each set is provided. The partition wall 35 has a trapezoidal cross section, for example, and is mainly formed of low-melting glass. A phosphor 36 is provided between the partition walls 35 on the side surface of the partition wall 35 and on the exposed surface of the dielectric layer 34.

The front glass substrate 31 thus configured
The rear glass substrate 32 and the rear glass substrate 32 are opposed to each other with a discharge space therebetween, and hermetically sealed at the peripheral edge portion with a spacer (not shown). A discharge gas is enclosed in the discharge space, and the discharge space partitioned by the partition walls 35 constitutes individual discharge cells and emits light in pixel units. As the discharge gas, for example, He, Ne,
At least one of rare gases of Ar, Xe, and Kr is used, and a mixed gas of Ne and Xe or a gas composed of only Xe is preferable. The discharge gas pressure is the same as the sustain electrode 37 that discharges.
The pressure is set such that high-luminance and high-efficiency discharge can be stably performed in relation to the mutual distance between X, 37Y and the address electrodes 33A, 33B. This display panel 30
Is the address electrodes 33A and 33B for each pixel area.
It can be manufactured in the same manner as the conventional method except that the book is patterned.

Here, the sustain electrode 37X and the scan electrode 37Y
Is the same as in the first embodiment.
And pulsed in the same manner.

A data pulse Pd generated by the pulse generation circuit 42A is applied from the data driver 42 to the address electrode 33A. That is, the data driver 42 and the pulse generation circuit 42A are
It has the same configuration as the conventional data driver. further,
The charge holding pulse Ph generated by the pulse generation circuit 42B is applied to the address electrode 33B. Therefore, in the present embodiment, although the data pulse Pd and the charge holding pulse Ph are applied in pixel units,
Each of these pulses has a different address electrode 33.
A, 33B are applied. In the present embodiment, the pulse generating circuit 42A and the pulse generating circuit 42B are respectively referred to as "first voltage applying means" and "second voltage applying means".
It corresponds to.

Next, a method of driving this plasma display device will be described.

FIGS. 6A to 6D are time charts showing drive voltage waveforms (for one subfield) according to the drive method of the present embodiment. Also in the present embodiment, each operation in the reset period and the sustain period is performed in the same manner as the conventional one. However, regarding the address period, the scan driver 17Y (Y ₁ , Y ₂ , ...
.., Y _n ) and at the same time when the scan pulse is applied to the address electrodes 33A (A ₁ , A ₂ , ...
, A _m ) is applied with a data pulse Pd synchronized with the scanning timing to write data. The widths of the scan pulse and the data pulse Pd at this time are both 1 μs.
ec or less, and the scanning is performed at high speed. Further, the address electrodes 33B (B ₁ , B ₂ , ...
, B _m ) is applied with the charge holding pulse Ph. As a result, the discharge is maintained in the pixel area after the application of the data pulse Pd, and the discharge is stably performed for a sufficient period until the charged particles in the pixel area reach a predetermined amount.

Therefore, although the data writing operation is performed at a high speed, the generation of pixels whose ON / OFF is indefinite is suppressed at this stage.

As described above, in the present embodiment, the display panel 30 having the address electrodes 33A and 33B for each pixel is used, and two kinds of pulses of the data pulse Pd and the charge holding pulse Ph are applied to each of the address electrodes 33A and 33B. Since a conventional address driving IC is used as it is for the data driver 42, the data pulse Pd having a predetermined pulse width can be applied because the address discharge is performed by applying. Other effects are similar to those of the first embodiment.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made. For example, in the second embodiment described above, two types of pulses Pd and Ph are superposed and applied to one address electrode 13.
The configuration of the driver in that case is not limited to the embodiment,
This is realized by a known circuit configuration method that outputs a waveform obtained by adding two types of voltage waveforms.

In addition, in the second embodiment, the address electrode 33B serves as a common electrode, and one pulse generation circuit 42B is used.
However, the connection form of both is not limited to that described in the above embodiment, and various modifications are possible. For example, the pulse generating circuit may be separately connected to each of the address electrodes 33B. Alternatively, the address electrodes 33B may be grouped for each predetermined number, and the pulse generation circuits may be separately connected to each group.

In the second embodiment, the address electrodes are the address electrodes 33 to which different pulses are applied.
Although the description has been made with two lines A and 33B, three or more lines may be provided for each pixel. In that case, in addition to the electrodes for applying the data pulse, all the charge holding pulses may be applied, or in addition to the charge holding pulse, a pulse having another function may be applied. Furthermore, although the address electrodes 33A and 33B are arranged in parallel on the surface of the substrate 32, as shown in FIG.
A and 33B may be provided in the direction perpendicular to the substrate surface.

[0056]

As described above, according to the plasma display device and the drive circuit thereof according to the present invention, the first drive voltage for starting the discharge between the address electrode and the scan electrode is generated, and the address is generated. A first voltage applying means for applying to the electrode, and a first voltage holding means for maintaining an electric field so that the discharge started by the application of the first drive voltage is continued until the charged particles inside the pixel region reach a predetermined amount. A second voltage applying means for generating a driving voltage of 2 and applying it to the address electrode is provided. Further, according to the driving method of the plasma display device of the present invention, the emission control of the pixel region is performed by the scanning electrode. The scanning voltage is sequentially applied to the address electrodes, and at the same time, the first driving voltage for starting discharge between the address electrodes and the scanning electrodes and the first driving voltage are applied to the address electrodes. Discharge is performed by applying two kinds of voltage of the second drive voltage for maintaining the electric field so that the charged particles inside the pixel region are maintained to a predetermined amount. Can be shortened according to the application time of the first drive voltage, and the entire address period, which conventionally required a long time, can be shortened. Therefore, even if the number of pixels increases, it is possible to display with high brightness and high gradation. At the same time, despite reducing the scanning time, the first
By applying the second drive voltage after the application of the drive voltage, the predetermined amount of wall charges is stably formed in the regular region, and ON / OFF of the pixel is properly determined. Therefore,
It is possible to perform high-luminance display and display without flicker or other noise.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a main part of a plasma display device according to a first embodiment of the present invention.

2A and 2B are views for explaining the shape of a pulse applied to the plasma display device shown in FIG. 1, where FIG. 2A is a voltage waveform diagram of a data pulse Pd and a charge holding pulse Ph, and FIG.
FIG. 4 is a voltage waveform diagram of a conventional data pulse.

FIG. 3 is a voltage waveform diagram showing a driving sequence of the plasma display device shown in FIG.

FIG. 4 is a configuration diagram showing a main part of a plasma display device according to a second embodiment of the present invention.

5 is a partial perspective view showing a configuration of a display panel of the plasma display device shown in FIG.

6 is a voltage waveform diagram showing a driving sequence of the plasma display device shown in FIG.

7 is a cross-sectional view showing a configuration of a display panel according to a modification of the display panel of the plasma display device shown in FIG.

FIG. 8 is a partial perspective view showing a configuration of a display panel of a conventional plasma display device.

9 is a plan view showing a schematic electrode structure of a display panel of the plasma display device shown in FIG.

10 is a diagram showing voltage waveforms input to the display panel of the plasma display device shown in FIG.

11 is a diagram for explaining a general driving method of the plasma display device shown in FIG.

FIG. 12 is a schematic configuration diagram showing an electrode structure of a plasma display device driven by dividing a conventional screen into two parts.

[Explanation of symbols]

10, 30 ... Display panel, 31 ... Front glass substrate, 32
... Back glass substrate, 13, 33A, 33B ... Address electrode, 34 ... Dielectric layer, 35 ... Partition wall, 36 ... Phosphor layer, 1
7, 37 ... Electrode pair, 17X, 37X ... Sustain electrode, 17
Y, 37X ... Scan electrode, 38 ... Dielectric layer, 39 ... Protective layer, 21, 41 ... Sustain driver, 22, 42 ... Data driver, 22A, 22B, 42A, 42B ... Pulse generation circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/66 101 G09G 3/28 J F term (reference) 5C058 AA11 BA01 BA05 BA07 BA25 BB03 5C080 AA05 BB05 CC03 DD07 DD08 FF01 FF12 HH04 HH06 JJ04 JJ06

Claims (16)

[Claims] 1. A first substrate and a second substrate which are arranged to face each other, a scanning electrode which is provided on the first substrate in parallel and to which a scanning voltage is applied, and the second substrate. An address electrode which is provided on the above so as to intersect with the scanning electrode and arranged in parallel and to which a drive voltage for light emission control is applied; and a pixel region which is provided in an intersection region of the scanning electrode and the address electrode. A method of driving a plasma display device, comprising: controlling emission of light in the pixel region by sequentially applying a scan voltage to the scan electrodes, and at the address electrodes between the address electrodes and the scan electrodes. A first drive voltage for initiating discharge, and
Two kinds of voltage, a second driving voltage, for holding an electric field are applied so that the discharge started by the application of the first driving voltage is continued until the charged particles inside the pixel region have a predetermined amount. A method of driving a plasma display device, comprising: 2. A voltage that causes the sum of the scan voltage and the scan voltage to be higher than a discharge start voltage between the scan electrode and the address electrode, is applied to the address electrode as the first drive voltage. The voltage is applied not only in response to non-emission but also as the second drive voltage until at least the discharge started by the application of the first drive voltage brings the charged particles inside the pixel region to a predetermined amount. 2. The method of driving a plasma display device according to claim 1, wherein a voltage whose sum of the scanning voltage is lower than the discharge starting voltage is continuously applied. 3. The driving method of the plasma display device according to claim 2, wherein the width of the first driving voltage is set to 2 μsec or less. 4. The application period of the second drive voltage is 1 μs after the scan voltage is applied to the scan electrodes in the last column.
The driving method of the plasma display device according to claim 2, wherein the voltage is applied so as to include a period of ec or more. 5. The method of driving a plasma display device according to claim 1, wherein the first and second drive voltages are applied to the address electrodes in a superimposed manner. 6. A plasma display device in which a plurality of the address electrodes are provided for each of the light emitting unit regions, wherein the first and second drive voltages are distributed and applied to the address electrodes. Item 2. A driving method of a plasma display device according to item 1. 7. A first substrate and a second substrate facing each other, a scanning electrode provided in parallel on the first substrate and to which a scanning voltage is applied, and the second substrate. An address electrode which is provided on the above so as to intersect with the scanning electrode and arranged in parallel and to which a drive voltage for light emission control is applied; and a pixel region which is provided in an intersection region of the scanning electrode and the address electrode. A driving circuit of a plasma display device including: a first driving voltage for generating a first driving voltage for starting discharge between the address electrode and the scanning electrode, and applying the first driving voltage to the address electrode. And a second drive voltage for maintaining an electric field so that the discharge started by the application of the first drive voltage is maintained until the charged particles inside the pixel region have a predetermined amount. , The address electrode Driving circuit of a plasma display device characterized by having a second voltage application means for applying. 8. The first voltage applying means uses, as the first drive voltage, a pulse voltage whose sum with the scan voltage is higher than a discharge start voltage between the scan electrode and the address electrode. The drive circuit of the plasma display device according to claim 7, wherein the drive circuit is generated according to whether the pixel region emits light or not. 9. The pulse width of the first drive voltage is 2 μm.
9. The drive circuit for the plasma display device according to claim 8, wherein the drive circuit has a duration of sec or less. 10. The second voltage applying means is the second voltage applying means.
As a driving voltage of the discharge voltage, a voltage whose sum with the scanning voltage is lower than the discharge starting voltage is generated, and at least the discharge started by applying the first driving voltage causes a predetermined amount of charged particles inside the pixel region. 8. The drive circuit of the plasma display device according to claim 7, wherein the voltage is continuously applied until the above condition. 11. The second voltage applying means includes the second voltage applying means.
11. The drive circuit of the plasma display device according to claim 10, wherein the drive voltage of 1 is applied during a period including a period of 1 μsec or more after the scan voltage is applied to the scan electrode of the last column. 12. The first and second voltage applying means are electrically connected to each of the address electrodes so that the first and second drive voltages are applied to the address electrodes in a superimposed manner. 7. The method according to claim 7, wherein
A driving circuit of the plasma display device described. 13. A plasma display device in which the address electrodes are provided in groups of a predetermined number of two or more for each of the light emitting unit regions, wherein the first and second voltage applying units are the 8. The driving circuit of the plasma display device according to claim 7, wherein the address electrodes are electrically connected to different ones of the pair of address electrodes. 14. A first substrate and a second substrate arranged to face each other.
And a scanning electrode to which a scanning voltage is applied, the scanning electrode being provided in parallel on the first substrate, and the scanning electrode being provided on the second substrate so as to intersect the scanning electrode in parallel. A plasma display device comprising: an address electrode to which a driving voltage for controlling light emission is applied; and a pixel region provided in an intersection region of the scan electrode and the address electrode, wherein the address electrode and the scan A first voltage applying means for generating a first drive voltage for starting discharge between the electrodes and applying the first drive voltage to the address electrodes; and a discharge started by application of the first drive voltage. A second voltage applying means for generating a second driving voltage for holding the electric field so as to maintain the charged particles inside the pixel region to a predetermined amount and applying the second driving voltage to the address electrode. Characterizing Plasma display device. 15. The first and second voltage applying means are electrically connected to each of the address electrodes so that the first and second drive voltages are applied to the address electrodes in a superimposed manner. Claim 1 characterized by the above.
4. The plasma display device according to 4. 16. The address electrodes are provided so as to form a set with a predetermined number of two or more for each of the light emitting unit regions, and the first and second voltage applying means form the set. 15. The plasma display device according to claim 14, wherein the address electrodes are electrically connected to different ones.