KR100667557B1 - Plasma display device and driving method of the same - Google Patents

Abstract

The present invention relates to a plasma display device and a method of driving the same, which can reduce manufacturing costs and prevent damage and malfunction of the data driver.

A plasma display device according to the present invention comprises a plasma display panel for displaying an image; A data driver to drive an address electrode of the plasma display panel using a base voltage, a first voltage, and a second voltage; And a driving voltage generator configured to generate the base voltage, the first voltage, and the second voltage to supply the data to the data driver.

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

1 is a diagram illustrating a subfield pattern of an 8-bit default code for implementing 256 gray levels in a PDP.

2 is a diagram illustrating a conventional PDP driving waveform.

3 is a diagram illustrating an electrode arrangement of a general plasma display panel.

FIG. 4 is a view schematically illustrating a driving signal applied to electrodes and a selected discharge cell in an address period in the plasma display apparatus of FIG. 3.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a data driver of the plasma display device illustrated in FIG. 5.

FIG. 7 is a diagram illustrating a driving waveform generated by the plasma display device shown in FIG. 5.

<Description of the symbols for the main parts of the drawings>

1, 54: discharge cell 2, 56: data driver

60: scan driver 62: sustain driver

64: timing controller 66: drive voltage generator

82: first voltage supply control unit 84: second voltage supply control unit

86: base voltage supply control unit 88: data IC

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device and a method of driving the same, which can reduce manufacturing costs and prevent damage and malfunction of a data driver.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Ne + Xe is discharged. Display an image. Such PDPs are not only thin and large in size, but also have improved image quality due to recent technology development.

1 is a diagram illustrating a subfield pattern of an 8-bit default code for implementing 256 gray levels in a PDP.

Referring to FIG. 1, the PDP performs time division driving by dividing a frame into several subfields having different emission counts in order to realize gray level of an image. Each subfield includes a reset period for initializing the full screen, an address period for selecting a scan line and selecting a discharge cell in the selected scan line, an address period for selecting a scan line and selecting a discharge cell in the selected scan line, and a discharge. According to the number of times, it is divided into sustain period to implement gradation. For example, when displaying an image in 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period RP, an address period AP, and a sustain period SP as described above. In this case, while the reset period RP and the address period AP of each subfield are the same for each subfield, the sustain period and the number of sustain pulses allocated thereto are 2n (n = 0, 1, 2, 3, 4, 5, 6, 7) is increased.

2 is a diagram illustrating a conventional PDP driving waveform.

Referring to FIG. 2, each of the subfields SF includes a reset period RP for initializing the discharge cells of the full screen, an address period AP for selecting the discharge cells, and a sustain for discharging the selected discharge cells. It includes a period SP.

In the reset period RP, the rising ramp waveform PR is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. After the rising ramp waveform PR is applied in the set-down period SD, the positive sustain voltage Vs lower than the peak voltage of the rising ramp waveform PR to the negative scan voltage Vs is negative. The falling ramp waveform NR falling at a predetermined slope is simultaneously applied to the scan electrodes Y. The falling ramp waveform NR generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, thereby uniformly retaining wall charges required for address discharges in the cells of the full screen.

In the address period AP, a negative scan pulse SCNP is sequentially applied to the scan electrodes Y, and a positive data pulse DP is applied to the address electrodes. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive sustain voltage Vs is applied to the sustain electrodes Z during the set down period SD and the address period AP.

In the sustain period SP, a sustain pulse SSUS is applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SSUS is applied while the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge occurs. Here, the sustain pulses SSP have the same voltage value as the sustain voltage Vs.

3 is a diagram illustrating an electrode arrangement of a general plasma display panel.

In FIG. 3, it can be seen that the discharge cells 1 are configured at the intersections of the scan electrode lines Y1 to Yn, the sustain electrode lines Z, and the address electrode lines (or the data electrode lines X1 to Xm). have.

The scan electrode lines Y1 to Yn supply scan pulses and sustain pulses so that the discharge cells 1 are scanned in units of lines, and the discharges are maintained in the discharge cells 1.

The sustain electrode lines Z commonly supply a sustain pulse to maintain the discharge in the discharge cells 1 together with the scan electrode lines Y1 to Yn. The address electrode lines X1 to Xm supply data pulses synchronized with the scan pulses in line units so that the discharge cells 1 in which discharges are to be maintained are selected according to the logic value of the data pulses.

As shown in FIGS. 2 and 3, the plasma display apparatus includes a scan signal SCNP sequentially applied to the scan electrode lines Y in the address period AP and a data signal supplied to the address electrode lines X. The discharge cell 1 is selected by the address signal.

FIG. 4 is a view schematically illustrating a driving signal applied to electrodes and a selected discharge cell in an address period in the plasma display apparatus of FIG. 3.

Referring to FIG. 4, scan pulses SCNP are sequentially supplied to scan electrode lines in order to select a discharge cell in which a display discharge is to be generated in the address period AP. At the same time, the data pulse DP is supplied to the address electrode lines X. That is, while the scan pulse SCNP is supplied to the first scan electrode line Y1, the positive data pulse DP is supplied to the first and third discharge cells R1 and B1 to perform the display discharge. The data pulse DP is not supplied to the second discharge cell G1 in which no display discharge occurs.

In this case, address discharge is generated in the first and third discharge cells R1 and B1 by the scan pulse SCNP and the data pulse DP. The address discharge is generated by the difference between the potential (-Vy) of the negative scan pulse SCNP and the potential Va of the data pulse DP of the positive polarity and the wall charge.

The data pulse DP is supplied to the address electrode lines X by the data driver 2 illustrated in FIG. 4. The data driver 2 supplies the signal voltages Va and GND supplied from a driving voltage generator (not shown) in synchronization with a control signal CS supplied from an external control circuit such as a timing controller (not shown). ) Is supplied to the address electrode lines X by switching.

However, the conventional PDP has a large voltage difference between the high logic value potential Va and the low logic value potential GND of the data pulse DP. In particular, the high logic value and the low logic value of the conventional PDP have a potential difference of several tens of volts [V] to several hundred volts [V]. The difference between the low and high logic values of the data pulse DP leads to the burden on the data driver 2 for processing the data pulse DP. Such a burden causes the breakdown voltage rating of the data driver 2 to have a voltage resistance large enough to withstand the high voltage of the data pulse DP. . That is, the data driver 2 has a breakdown voltage rating that is larger than the voltage Va of the high logic value of the data pulse DP, which causes a problem in that the manufacturing cost increases when the data driver 2 is manufactured. In addition, due to the high breakdown voltage, a large amount of heat is generated in the data driver 2 of the conventional PDP, and the heat damage and malfunction of the device are frequently caused by such heat.

Accordingly, an object of the present invention is to provide a plasma display device and a method of driving the same, which can reduce manufacturing costs and prevent damage and malfunction of the data driver.

In order to achieve the above object, the plasma display device according to the present invention comprises a plasma display panel for displaying an image; A data driver to drive an address electrode of the plasma display panel using a base voltage, a first voltage, and a second voltage; And a driving voltage generator configured to generate the base voltage, the first voltage, and the second voltage to supply the data to the data driver.

The first voltage is greater than the base voltage and less than the second voltage.

The first voltage is larger than the base voltage and is smaller than the voltage obtained by subtracting the magnitude of the scan voltage and the wall charge voltage involved in the discharge from the discharge start voltage at which discharge occurs.

A driving method of a plasma display apparatus according to the present invention is a method of driving a plasma display apparatus in which one subfield is divided into a reset period, an address period, and a sustain period, the method comprising: providing a base voltage to an address electrode during the reset period ; Supplying a data pulse consisting of a positive first voltage and a second voltage to the address electrode during the address period; And supplying a ground voltage to the address electrode during the sustain period.

The first voltage is greater than the base voltage and less than the second voltage.

The first voltage is greater than the base voltage and is characterized by being a voltage smaller than the voltage of the discharge start voltage at which the discharge occurs, minus the voltage size of the wall charges involved in the scan pulse and discharge.

Other objects and features of the present invention in addition to the above objects will be revealed through a detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 5 to 7.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 52, a red color R, and a green color G for displaying an image. And a data driver 56 for supplying data to the address electrodes X1 to Xm of the discharge cells 54 coated with the blue (B) phosphor, and a scan driver for driving the scan electrodes Y1 to Yn. 60, a sustain driver 62 for driving the sustain electrodes Z, a timing controller 64 for controlling each driver 56, 60, and 62, and necessary for each driver 56, 60, 62; And a driving voltage generator 66 for supplying the driving voltage.

The PDP 52 includes an upper substrate on which the scan electrodes Y1 to Yn and the sustain electrodes Z are formed, and a lower substrate on which the address electrodes X1 to Xm are formed. In the PDP 52, discharge cells 54 are formed in an area where scan electrodes Y1 to Yn, sustain electrodes Z, and address electrodes X1 to Xm cross each other. In the discharge cell 54, red (R), green (G), and blue (B) phosphors are coated, and drive waveforms supplied from the data driver 56, the scan driver 60, and the sustain driver 62 are provided. Driven by

The data driver 56 samples and latches the red (R), green (G), and blue (B) data in response to the timing control signal Cx supplied from the timing controller 64, and then red (R), green. The first voltage Va, which is the data voltage of the data of (G) and blue (B), is the address electrodes X1 of the discharge cells 54 coated with the red (R), green (G), and blue (B) phosphors. To Xm). Here, the data driver 56 is supplied with a second voltage Vab, which is a positive bias voltage, in order to prevent the breakdown voltage of the switches installed therein from being increased by the first voltage Va. In addition, the base driver GND is supplied to the data driver 56. Accordingly, the data driver 56 supplies the base voltages GND and 0V to the address electrodes X1 to Xm during the reset period and the sustain period, and the first voltage Va and the second voltage Vab during the address period. Is supplied to the address electrodes X1 to Xm. Here, the second voltage Va has a voltage value greater than the base voltage GND and 0V and smaller than the first voltage Va. Due to the second voltage Vab, the breakdown voltages of the switches installed in the data driver 56 during the address period are lowered. That is, the switches have a breakdown voltage condition equal to the difference voltage Va-Vab between the first voltage Va and the second voltage Va. Detailed description thereof will be described later.

The scan driver 60 supplies the initialization waveforms to the scan electrodes Y1 to Yn during the reset period RP in response to the timing control signal Cy supplied from the timing controller 64 and then during the address period AP. The scan bias voltage Vsc is supplied and the scan pulse SCNP is sequentially supplied. The scan driver 60 supplies the sustain pulse SUSP to the scan electrodes Y1 to Yn during the sustain period SP in response to the timing control signal Cy supplied from the timing controller 64.

The sustain driver 62 supplies the positive sustain voltage Vs to the sustain electrodes Z during the set down period and the address period in response to the timing control signal Cz supplied from the timing controller 64. Afterwards, the sustain pulse SUSP is alternately supplied to the scan driver 60 during the sustain period.

The timing controller 64 receives the vertical / horizontal synchronization signal and the clock signal to generate timing control signals Cx, Cy, and Cz necessary for each of the driving units 56, 60, and 62, and the timing control signals Cx, Cy, Each drive unit 56, 60, 62 is controlled by supplying Cz) to the drive units 56, 60, 62. At this time, the data control signal Cx includes a sampling clock for sampling data, a latch control signal, and a switch control signal for controlling the on / off time of the driving switch element. In addition, the scan control signal Cy includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 60. The sustain control signal Cz includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 62.

The driving voltage generator 66 scans by generating a setup voltage Vsetup, a base voltage GND, 0V, a negative scan voltage (-Vy), a scan bias voltage Vsc, and a positive sustain voltage Vs. The driving unit 60 is supplied to the driving unit 60, and the ground voltages GND and 0V and the positive sustain voltage Vs are supplied to the sustain driving unit 62. In addition, the driving voltage generator 66 generates a first voltage Va, which is a data voltage of red (R), green (B), and blue (B) data, and a second voltage (Vab), which is a positive bias voltage. The first voltage Va, the second voltage Vab, and the base voltages GND and 0V are supplied to the data driver 56.

On the other hand, Equation 1 is a formula showing the relationship between the first voltage (Va), the negative scan voltage (-Vy), the wall charge voltage (Vwall) and the discharge start voltage (Vf) for the address discharge.

The condition for discharge in the discharge cells selected in the address period as shown in Equation 1 is the sum of the first voltage Va, the absolute value of the negative scan voltage (-Vy) and the voltage magnitude of the wall charge voltage (Vwall) It must be larger than this discharge start voltage Vf. That is, when the sum of the voltage magnitudes of the first voltage Va, the scan voltage -Vy, and the wall charge voltage Vwall becomes larger than the discharge start voltage Vf, an address discharge is performed, and a discharge to generate a sustain discharge is generated. The cell is selected.

Similarly, the first voltage Va is not applied to the off cells that do not generate sustain discharge, and thus a voltage smaller than the discharge start voltage Vf is maintained. This is shown in Equation 2.

That is, only the second voltage Vab, the wall charge voltage Vwall, and the scan voltage −Vy applied to the address electrodes X1 to Xm are applied, so that the voltages necessary for discharge are the first voltage Va and the second voltage. The voltage Vab becomes insufficient as the difference voltage. As a result, even if the second voltage Vab is applied, no discharge occurs in the off cells.

Therefore, the magnitude of the second voltage Vab is defined as in Equation 3.

That is, the second voltage Vab is larger than the conventional ground voltage GND, and has a voltage smaller than the magnitude of the voltage obtained by subtracting the scan voltage (-Vy) and the wall voltage (Vwall) from the discharge start voltage (Vf). desirable.

As described above, the second voltage Vab is determined within a range in which the voltage breakdown voltage applied to the data driver 56 can be most effectively reduced without generating discharge in a period where the data pulse DP is not applied. Should be.

FIG. 6 is a diagram illustrating a data driver shown in FIG. 5.

Referring to FIG. 6, in the plasma display apparatus of the present invention, the data driver 56 controls the first voltage supply controller 82 and the address electrode to control the first voltage Va to be supplied to the address electrodes X1 to Xm. A second voltage supply controller 84 controlling the second voltage Vab to be supplied to the fields X1 to Xm, and a base voltage supply controller controlling the base voltage GND to be supplied to the address electrodes X1 to Xm. 86 and an integrated circuit (hereinafter referred to as " IC ") 88. The &quot; IC &quot;

The first voltage supply controller 82 controls the first voltage Va to be supplied to the address electrodes X1 to Xm during the address period according to the control signal Cx supplied from the timing controller 64. The first voltage supply control unit 82 includes a first switch SW1 connected between the first voltage source Va and the data IC 88.

The second voltage supply controller 84 controls the second voltage Vab to be supplied to the address electrodes X1 to Xm during the address period according to the control signal Cx supplied from the timing controller 64. At this time, the second voltage supply control unit 84 is alternately driven with the first voltage supply control unit 82. That is, when the first voltage Va is supplied to the address electrodes X1 to Xm by the first voltage supply controller 82, the second voltage supply controller 84 does not operate. In contrast, when the second voltage Vab is supplied to the address electrodes X1 to Xm by the second voltage supply controller 84, the first voltage supply controller 82 is not driven. This second voltage supply control unit 84 includes a second switch SW2 and a third switch SW3 connected in series between the second voltage source Vab and the data IC 88. At this time, the body diode of the second switch SW2 prevents the reverse current from the data IC 88 to the second voltage source Vab when the first voltage Va is supplied to the address electrodes X1 to Xm. The body diode of the third switch SW3 prevents reverse current from the second voltage source Vab when the base voltages GND and 0V are supplied to the address electrodes X1 to Xm.

The base voltage supply control unit 86 controls the base voltages GND and 0V to be supplied to the address electrodes X1 to Xm during the reset period and the sustain period according to the control signal Cx supplied from the timing controller 64. . The base voltage supply control unit 86 is connected in parallel with the second voltage supply control unit 84 and includes a fourth switch SW4 connected between the base voltage source GND and the data IC 88. At this time, the body diode of the fourth switch SW4 is connected to the base voltage source GND from the data IC 88 when the first voltage Va and the second voltage Vab are supplied to the address electrodes X1 to Xm. To prevent reverse current.

The data IC 88 is connected to the address electrodes X1 to Xm and according to the control signal Cx supplied from the timing controller 64, the first voltage Va, the second voltage Vab, and the ground voltage GND. Is supplied to the address electrodes X1 to Xm. The data IC 88 may include a fifth switch SW5 and a second voltage supply controller 84 and a base voltage supply controller connected between the first voltage supply controller 82 and the address electrodes X1 to Xm. And a sixth switch SW6 connected between the common terminal and the address electrodes X1 to Xm.

As described above, when the first voltage Va is supplied to the address electrodes X1 to Xm, the data driver includes a second switch included in the second voltage supply controller 84. Since voltages are distributed between SW2 and the third switch SW3 and the fourth switch SW4 included in the base voltage supply controller 86, the breakdown voltage conditions of the switches SW1 to SW4 are lowered.

FIG. 7 is a diagram illustrating a driving waveform generated by the plasma display device shown in FIG. 5.

Referring to FIG. 7, the PDP of the present invention is a reset period (RP) for initializing the discharge cells 54 of the full screen, an address period (AP) for selecting a cell, and the selected discharge cells (54). And a sustain period SP for maintaining the discharge.

In the setup period SU during the reset period RP, the rising ramp waveform PR is applied to all the scan electrodes Y, the ground voltage 0V is applied to the sustain electrodes Z, and the address electrodes The ground voltage GND is applied to X). Accordingly, in the setup period SU, dark discharge is generated in which light is hardly generated between the scan electrodes Y and the address electrodes X in the cells of the full screen by the rising ramp waveform PR. At the same time, dark discharge occurs between the scan electrodes (Y) and the sustain electrodes (Z). As a result of this dark discharge, positive wall charges remain on the address electrodes X and the sustain electrodes Z immediately after the setup period SU, and negative wall charges remain on the scan electrodes Y. Will remain.

Following the set-up period SU, in the set-down period SD of the reset period RP, the falling ramp waveform NR, which descends by a predetermined slope from the sustain voltage Vs to the negative erase voltage Ve, is scanned. To Y1 to Yn. At the same time, a positive sustain voltage Vs is applied to the sustain electrodes Z, and a ground voltage GND is applied to the address electrodes X. Accordingly, a dark discharge is generated between the scan electrodes Y and the address electrodes X in the discharge cells 54 of the full screen by the falling ramp waveform NR, and simultaneously with the scan electrodes Y Dark discharge also occurs between the sustain electrodes Z. As a result of the dark discharge in this set-down period SD, the wall charge distribution in each of the discharge cells 3 changes to the optimum condition of the address. That is, the excess wall charges unnecessary for the address discharge are erased on the scan electrodes Y and the address electrodes X in the respective discharge cells 3, and a certain amount of wall charges remains. The wall charges on the sustain electrodes Z are inverted from the positive to the negative polarity as the negative wall charges transferred from the scan electrodes Y accumulate.

In the beginning of the address period AP, when the second voltage Vab is applied to the address electrodes X, when the negative scan pulse SCNP is sequentially applied to the scan electrodes Y, the scan pulse SCNP is applied. In synchronization with, a data pulse DP having a first voltage Va is applied to the address electrodes X. In addition, a positive sustain voltage Vs or a lower positive bias voltage Vzb is applied to the sustain electrodes Z. Here, the second voltage Vab has a voltage value greater than the base voltage 0V and less than the first voltage Va. The scan pulse SCNP is a scan voltage Vsc that is lowered from the base voltage 0V or the negative scan bias voltage Vyb close thereto to the negative scan voltage -Vy. Accordingly, an address discharge is formed between the scan electrodes Y and the address electrodes X in the on-cells to which the scan voltage Vsc and the first voltage Va are applied during the address period AP. Is generated.

In the sustain period SP, the sustain pulse SSUS of the sustain voltage level Vs is alternately applied to the scan electrodes Y and the sustain electrodes Z, and the ground voltages GND, are applied to the address electrodes X. 0V) is applied. Then, in the on-cells selected by the address discharge, a sustain discharge is generated between the scan electrodes Y and the sustain electrodes Z every time the sustain pulse SSUS is applied. In contrast, sustain discharge is not generated in the off-cells during the sustain period SP.

As described above, in the plasma display apparatus and the driving method thereof, the base voltages GND and 0V are applied to the address electrodes X during the reset period RP and the sustain period SP, and the address period ( The second voltage Vab, which is greater than the base voltage 0V and less than the first voltage Va, is applied to the address electrodes X during the remaining period in which the data pulse DP is not applied to the data driver DP. Loss of internal pressure decreases.

That is, in the present invention, unlike the conventional art, the breakdown voltage applied to the data driver is equal to the difference between the positive bias voltage Vab and the reference voltages 0 [V] and GND that are continuously maintained at the address electrodes X1 to Xm. As a result, the voltage burden of the data driver is reduced.

As described above, the plasma display device and the driving method thereof according to the present invention apply the base voltage to the address electrodes during the reset period and the sustain period, and the base voltage to the address electrodes for the remaining period during which no data pulse is supplied during the address period. By providing a positive bias voltage larger than the data voltage, the breakdown voltage of the data driver may be reduced by the positive bias voltage. For this reason, the manufacturing cost of PDP can be reduced. In addition, since the data driver has a low breakdown voltage range, heat generated in the data driver may be reduced. Accordingly, the plasma display device and the driving method thereof of the present invention can prevent damage and malfunction of the driving element.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

A plasma display panel for displaying an image; A scan driver for applying a scan bias voltage having a negative voltage value in an address period; A data driver which applies a first voltage and a second voltage to drive an address electrode of the plasma display panel; And And a driving voltage generator for generating the first voltage and the second voltage and supplying the first voltage and the second voltage to the data driver. The method of claim 1, And the second voltage is greater than the base voltage and less than the first voltage. The method of claim 1, And the second voltage is larger than the base voltage and is smaller than the voltage obtained by subtracting the absolute value of the scan voltage and the wall charge voltage involved in the discharge from the discharge start voltage at which the discharge is generated. A driving method of a plasma display apparatus which drives one subfield by dividing it into a reset period, an address period, and a sustain period, Supplying a ground voltage to an address electrode during the reset period; Supplying a scan bias voltage having a negative voltage value to the scan electrode during the address period, and supplying a data pulse comprising a first voltage and a second voltage having a positive polarity to the address electrode; And And supplying a ground voltage to the address electrode during the sustain period. The method of claim 4, wherein And the second voltage is greater than the base voltage and less than the first voltage. The method of claim 4, wherein The second voltage is greater than the base voltage and is less than the magnitude of the voltage obtained by subtracting the absolute value of the scan pulse and the voltage magnitude of the wall charges involved in the discharge from the discharge start voltage at which the discharge is generated. Way.

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