CN1885381A - Plasma display apparatus and driving method thereof - Google Patents
Plasma display apparatus and driving method thereof Download PDFInfo
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- CN1885381A CN1885381A CNA2006100908337A CN200610090833A CN1885381A CN 1885381 A CN1885381 A CN 1885381A CN A2006100908337 A CNA2006100908337 A CN A2006100908337A CN 200610090833 A CN200610090833 A CN 200610090833A CN 1885381 A CN1885381 A CN 1885381A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
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Abstract
A plasma display apparatus and driving method thereof are provided. The plasma display apparatus comprises a plasma display panel comprising address electrodes, a data driver for supplying a data voltage, and a first voltage having a voltage value that is greater than ground voltage, to the address electrodes, and a driving voltage generator for generating the first voltage and the data voltage, and for supplying the first voltage and the data voltage to the data driver. A driving method comprises supplying ground voltage to address electrodes during a reset period, supplying a first voltage, that is greater than the ground voltage, to the address electrodes during an address period, supplying a scan reference voltage to scan electrodes during the address period, supplying a data voltage to the address electrodes during the address period, and supplying ground voltage to the address electrodes during a sustain period.
Description
Technical field
The present invention relates to a kind of plasma display panel device, in particular to a kind of plasma display panel device and driving method thereof.
Background technology
In general, plasma display panel device comprises plasma display panel and the driver that is used to drive plasma display panel.
Usually, in plasma display panel, the barrier rib that forms between header board and back plate constitutes a discharge cell.Each discharge cell all is full of main discharge gas, such as the gaseous mixture of neon (Ne), helium (He) or Ne and He and the inert gas that comprises small amount of xenon (Xe).
A formed majority discharge cell constitutes a pixel.For example, can display predetermined colors in combination (R) discharge cell, green (G) discharge cell and blueness (B) discharge cell to be to constitute a pixel.
When by the discharge of HF voltage article on plasma display board, described inert gas produces vacuum ultraviolet usually, and makes the light-emitting phosphor that forms between the barrier rib, presents image thus.Because this plasma display panel can be made very thin and very light, so this has significantly become display device of future generation.
Fig. 1 has described the drive waveforms of typical plasma display panel device.
As shown in the figure, each subdomain SF includes the reset cycle RP of the discharge cell that is used for the whole screen of initialization, is used to the cycle of the keeping SP that selects the addressing period AP of discharge cell and be used to keep the discharge condition of selected discharge cell.
In reset cycle RP, during putting liter interval SU, simultaneously all scan electrode Y are applied the positive ramp waveform.Because of positive ramp waveform RP, weak discharge (that is, putting lifting) takes place in the discharge cell of whole screen, in discharge cell, produce the wall electric charge thus.
Put SD falls at interval and during, simultaneously scan electrode Y is applied negative ramp waveform NR.Negative ramp waveform NR has predetermined slope, and described slope is kept voltage Vs from positive extreme direction (+) and dropped to negative pole scanning direction voltage-Vy, and the crest voltage of voltage less than positive ramp waveform PR kept in wherein said positive extreme direction.
Described negative ramp waveform NR promotes to generate weak erasure discharge in discharge cell, so that wipe by putting electric wall electric charge that produces of lifting and the unnecessary electric charge in the middle of the space charge.Therefore, the common required wall electric charge level that can in the discharge cell of whole screen, be consistent of address discharge.
In addressing period AP, SCNP sequentially imposes on scan electrode Y negative pole direction (-) scanning impulse, and simultaneously positive extreme direction (+) data pulse DP is imposed on addressing electrode.When the wall electric charge that produces during the voltage difference between scanning impulse SCNP and the data pulse DP is because of reset cycle RP increases, at the inner address discharge that takes place of the discharge cell that is applied in positive pole (+) directional data pulsed D P.Because of address discharge, in selected discharge cell, produce the wall electric charge.
Put SD and addressing period AP fall at interval and during, positive pole (+) direction is kept voltage Vs is applied to and keeps electrode Z.
During keeping cycle SP, alternately be applied to scan electrode Y and keep electrode Z keeping pulse SUSP.Then, when the wall electric charge of selected discharge cell increases because of keeping pulse SUSP,, pass through address discharge in selected discharge cell inside, applying when keeping pulse SUSP, at scan electrode Y with keep and take place between the electrode Z to keep discharge with what the surface-discharge form occurred at every turn.Herein, the pulse SUSP that keeps that alternately applies has the magnitude of voltage identical with keeping voltage Vs.
Fig. 2 has described the configuration of typical plasma display panel device.
As shown in the figure, discharge cell 1 be set at scan electrode circuit Y1 to Yn, keep those places, point of crossing that electrode circuit Z1 intersects each other to Zn and addressing electrode circuit (perhaps data electrode circuit) X1 to Xm.
Scan electrode circuit Y1 provides scanning impulse and keeps pulse to Yn, so that permission is that discharge cell 1 is scanned on the basis with the circuit, and keeps the discharge condition of discharge cell 1 inside.
Keeping electrode circuit Z1 generally provides to Zn and keeps pulse, so that allow to keep the inside of discharge cell 1 and the scan electrode circuit Y1 discharge condition to Yn.
Addressing electrode circuit X1 to Xm based on circuit, synchronously provide data pulse, so that allow to select to keep the partial discharge unit 1 of discharge condition according to the logical value of data pulse with scanning impulse.
Plasma display panel device as shown in figs. 1 and 2 uses sweep signal SCNP and data-signal (perhaps address signal) to select part discharge cell 1, wherein said sweep signal SCNP sequentially is provided to scan electrode circuit Y during addressing period AP, and described data-signal is provided for addressing electrode circuit X.
Fig. 3 has described the sketch of the selected discharge cell in the plasma display panel device shown in the drive signal that is provided for electrode during addressing period and Fig. 2.
Sweep signal SCNP is sequentially offered scan electrode circuit Y so that will carry out the discharge cell of mark discharge during being chosen in addressing period AP therein.Selection course is synchronous therewith, and described data pulse DP is provided for addressing electrode circuit X.
More particularly, when sweep signal SCNP being offered the first scan electrode circuit Y1, the data pulse DP of anodal (+) direction is provided for the first and the 3rd discharge cell R1 and B 1, wherein will carry out the mark discharge.Data pulse DP is not offered the second discharge cell G1 that can not carry out the mark discharge.
At this moment, in the first and the 3rd discharge cell R1 and B1, because of address discharge takes place for sweep signal SCNP and data pulse DP.Described address discharge takes place because of the voltage difference between the voltage Va of the voltage-Vy of wall electric charge and negative pole (-) scanning direction signal SCNP and positive pole (+) directional data pulsed D P.
Data driver 2 offers addressing electrode circuit X to above-mentioned data pulse DP.
Data driver 2 is synchronous with the control signal CS that provides from the external control circuit such as the timing controller (not shown), and signal voltage Va and GND are provided, and they provide from driving voltage generator (not shown) by blocked operation.
Yet typical plasma display panel (PDP) has voltage difference greatly usually between the voltage Va of the data pulse DP that is in logic high and the voltage GND that is in logic low.
Specifically, in the logic high state and the scope of the voltage difference between the voltage in the logic low state from tens volts of several hectovolts of minimum to maximum.
This logic value difference among the data pulse DP becomes a burden of the data driver 2 that is used for deal with data pulsed D P.This burden can cause following influence: the higher voltage of voltage than the actual data pulse DP that provides is provided the breakdown voltage rating of data driver 2; so that bigger breakdown voltage rating is provided, described bigger breakdown voltage rating can provide impedance to the high pressure of data pulse.
That is to say that data driver 2 certainly will have the higher breakdown voltage rating of voltage Va than the data pulse DP that is in logic high, has often increased manufacturing cost thus.
The data driver 2 of typical case PDP can discharge a large amount of heats because of higher voltage breakdown, and therefore, equipment is damaged or the execution error operation probably.
Summary of the invention
Therefore, various embodiment of the present invention is devoted to solve the problem and the shortcoming of background technology at least.
The invention provides a kind of plasma display panel device, it can reduce manufacturing cost and reduce the damage of data driver and the faulty operation of data driver, and a kind of driving method of plasma display panel device is provided.
According to an aspect of of the present present invention, a kind of plasma display panel device comprises the plasma display panel with addressing electrode, be used for providing data voltage and greater than the data driver of first voltage of ground voltage, and be used to produce first voltage and data voltage and be used for providing the driving voltage generator of first voltage and data voltage to data driver to addressing electrode.
According to another aspect of the present invention, a kind of driving method of plasma display panel device comprises: during the reset cycle, provide ground voltage to addressing electrode; During addressing period, provide first voltage greater than ground voltage to addressing electrode; During addressing period, provide scan reference voltage to scan electrode; , during addressing period, provide data voltage to addressing electrode; And during the cycle of keeping, provide ground voltage to addressing electrode.
According to another aspect of the present invention, a kind of driving method of plasma display panel device comprises: during the reset cycle, provide first voltage greater than ground voltage to addressing electrode; During addressing period, provide described first voltage to addressing electrode; During addressing period, provide scan reference voltage to scan electrode; And during addressing period, provide data voltage to addressing electrode.
Description of drawings
To describe the present invention in detail with reference to accompanying drawing subsequently, in the accompanying drawings, identical numeral relates to components identical.
Fig. 1 has described the drive waveforms that is produced by typical plasma display panel device.
Fig. 2 has described the electrode lay-out of typical plasma display panel device.
Fig. 3 has described the drive signal that is provided for electrode during addressing period and the sketch of the selected discharge cell in Fig. 2 ionic medium display device.
Fig. 4 has described the subdomain pattern of 8 default code that are used to realize 256 gray scales in the plasma display panel device according to the embodiment of the invention.
Fig. 5 has described the block diagram according to the plasma display panel device of the embodiment of the invention.
Fig. 6 has described the data driver according to the plasma display panel device of the embodiment of the invention.
Fig. 7 has described the drive waveforms that is produced by the plasma display panel device according to the embodiment of the invention.
Fig. 8 has described the drive waveforms that is produced by the plasma display panel device according to another embodiment of the present invention.
Fig. 9 has described by the selection to discharge cell of the drive waveforms that produced by the plasma display panel device according to the embodiment of the invention.
Embodiment
In more detailed mode embodiments of the invention are described with reference to the accompanying drawings.
According to embodiments of the invention, a kind of plasma display panel device comprises the plasma display panel with addressing electrode, be used for providing data voltage and greater than the data driver of first voltage of ground voltage, and be used to produce first voltage and data voltage and be used for providing the driving voltage generator of first voltage and data voltage to data driver to addressing electrode.
Described data driver can comprise and be used to control first voltage controller that first voltage is provided to addressing electrode, and be used to control the data voltage source controller that data voltage is provided to addressing electrode.
Described first voltage controller can provide first voltage to addressing electrode continuously during addressing period; And the data voltage source controller and first voltage controller alternately drive.
First voltage controller can comprise second switch and the 3rd switch.
Described second switch and the 3rd switch all can comprise body diode; Wherein the anode terminal of the body diode of second switch is towards the direction setting of the anode terminal of facing the 3rd switch main body diode.
First voltage can be greater than ground voltage and less than data voltage.
Described data driver can provide ground voltage to addressing electrode during the reset cycle.
First voltage can be greater than ground voltage and less than the voltage that deducts the summation of scanning voltage that offers scan electrode and the wall voltage that participates in discharge the ignition voltage when beginning to produce discharge.
First voltage numerically can be greater than 25% of data voltage, and less than the voltage of the summation that from ignition voltage, deducts scanning voltage that offers scan electrode and the wall voltage that participates in discharge.
According to another embodiment of the present invention, a kind of driving method of plasma display panel device comprises: during the reset cycle, provide ground voltage to addressing electrode; During addressing period, provide first voltage greater than ground voltage to addressing electrode; During addressing period, provide scan reference voltage to scan electrode; During addressing period, provide data voltage to addressing electrode; And during the cycle of keeping, provide ground voltage to addressing electrode.
First voltage can be greater than ground voltage and less than second voltage.
First voltage can be greater than ground voltage and less than the voltage that deducts the summation of scanning voltage that offers scan electrode and the wall voltage that participates in discharge the ignition voltage when beginning to produce discharge.
First voltage numerically can be greater than 25% of data voltage, and less than the voltage of the summation that from ignition voltage, deducts scanning voltage that offers scan electrode and the wall voltage that participates in discharge.
Described scan reference voltage can be less than ground voltage.
According to another embodiment of the present invention, a kind of driving method of plasma display panel device comprises: during the reset cycle, provide first voltage greater than ground voltage to addressing electrode; During addressing period, provide described first voltage to addressing electrode; During addressing period, provide scan reference voltage to scan electrode, and during addressing period, provide data voltage to addressing electrode.
First voltage can be greater than ground voltage and less than data voltage.
First voltage can be greater than ground voltage and less than the voltage that deducts the summation of scanning voltage that offers scan electrode and the wall voltage that participates in discharge the ignition voltage when beginning to produce discharge.
First voltage numerically can be greater than 25% of data voltage, and less than the voltage of the summation that from ignition voltage, deducts scanning voltage that offers scan electrode and the wall voltage that participates in discharge.
Described scan reference voltage can be less than ground voltage.
Below, will describe the various exemplary embodiments of article on plasma display device and driving method thereof with reference to the accompanying drawings in detail.
Fig. 4 for example understands the subdomain pattern of 8 default code that are used to realize 256 gray scales in the plasma display panel device according to the embodiment of the invention.
In order to realize the gray scale of image, plasma display panel device drives based on time-sharing format, whereby, a frame is divided into a plurality of subdomains with different emission numbers.
Each subdomain is divided into three parts, and these three parts comprise reset cycle, addressing period and keep the cycle.Reset cycle will be used for the previous image of initialization, and addressing period is used for the discharge cell selecting trace wiring and select selected trace wiring, and the cycle of keeping is used for realizing gray scale according to the discharge number.
For example, when with 256 gray scale display images, corresponding to 1/60 second, promptly 16.67 milliseconds frame period is divided into 8 subdomain SF1 to SF8.Each of 8 subdomain SF1 to SF8 all is divided into reset cycle RP, addressing period AP and keeps cycle SP.
The reset cycle RP and the addressing period AP of each subdomain are substantially the same.Yet, cycle of keeping of each subdomain and for the number of keeping pulse of its distribution increases with factor 2n, wherein n=0,1,2,3,4,5,6 and 7.
Specifically, Fig. 4 has described an example that can be applied to according to the subdomain pattern of plasma display panel device of the present invention.It should be noted that the present invention is not limited to the subdomain pattern shown in Fig. 1.
Fig. 5 for example understands the block diagram according to the plasma display panel device of embodiments of the invention.
As shown in the figure, described plasma display panel device comprises PDP 52, data driver 56, scanner driver 60, keeps driver 62, timing controller 64 and driving voltage generator 66.Described PDP 52 display images.Data driver 56 provides red (R), green (G) and blue (B) data to the addressing electrode X1 to Xm of the discharge cell 54 that is coated with R, G and B fluorophor.Scanner driver 60 drives the scan electrode Y1 to Yn of PDP 52.That keeps that driver 62 drives PDP 52 keeps electrode Z.Described timing controller 64 control data drivers 56, scanner driver 60 and keep driver 62, and described driving voltage generator 66 produces data driver 56, scanner drivers 60 and keeps the required driving voltage of driver 62.
Described PDP 52 comprises the front substrate that wherein is formed with scan electrode Y1 to Yn and keeps electrode Z, and comprises the rear portion substrate that wherein is formed with addressing electrode X1 to Xm.
Discharge cell 54 is set at scan electrode Y1 to Yn, keep those some places that electrode Z and addressing electrode X1 to Xm intersect each other.
Discharge cell 54 is coated with R, G and B fluorophor, and by from data driver 56, scanner driver 60 and the drive waveforms of keeping driver 62 and providing drive.
The timing controling signal Cx that data driver 56 responses provide from timing controller 64 comes R, G and B data are sampled, and latch R, G and B sampled data, and the data voltage Va of the R that latchs, G and B data is provided for the addressing electrode X1 to Xm of the discharge cell 54 that is coated with R, G and B fluorophor.
Data driver 56 can be used as first data driver and second data driver is driven individually.First data driver and second data driver by upper and lower settings or about be provided with.
Specifically, when first data driver when some addressing electrode X1 to Xm provides two data of R, G and B data, described second data driver provides another data to other addressing electrode X1 to Xm.
The first voltage Vab as positive extreme direction bias voltage is offered data driver 56, so that reduce by the caused voltage breakdown of voltage that is applied to data driver 56 by data voltage Va.
The first voltage Vab that offers data driver 56 is greater than ground voltage (0 volt) GND and less than data voltage Va.
The first voltage Vab that offers data driver 56 has reduced voltage difference (Va-Vab) and has reduced to be applied to the voltage breakdown of data driver 56 thus.Yet the value with prior art is identical basically for the voltage difference (Va-Vy) between the scanning voltage Vy of data voltage Va and scanning impulse SCNP.Therefore, address discharge is normally carried out.To describe this operation in detail after a while.
During the reset cycle, described scanner driver 60 responses provide waveform of initialization from the timing controling signal Cy that timing controller 64 provides to scan electrode Y1 to Yn.During addressing period AP, described scanner driver 60 provides scan reference voltage Vyb and scanning impulse SCNP in turn.
Described scan reference voltage Vyb can be less than ground voltage.
During keeping cycle SP, described scanner driver 60 responses are kept pulse SUSP from next the providing to scan electrode Y1 to Yn of timing controling signal Cy that timing controller 64 provides.
Put cycle SD and addressing period AP fall and during, the timing controling signal Cz that keeping driver 62 response provides from timing controller 64 to keep voltage Vs to what keep that electrode Z provides positive extreme direction.Then, during keeping cycle SP, keep driver 62 and scanner driver 60 and alternately operate, so that provide and keep pulse SUSP to keeping electrode Z.
Described timing controller 64 receives horizontal/vertical synchronization signals and clock signal, produce each driver 56,58,60 and 62 required timing controling signal Cx, Cy and Cz, and provide timing controling signal Cx, Cy and Cz, so that control each driver 56,58,60 and 62.
Described timing controling signal Cx comprises sampling clock, latch control signal and the switch controlling signal that is used for sampled data, and described switch controlling signal is used for the on/off time of control energy recovery circuit and driving switch device.
Timing controling signal Cy comprises the switch controlling signal of the ON/OFF time of the energy recovering circuit that is used in the gated sweep driver 60 and driving switch device.
Timing controling signal Cz comprises the switch controlling signal of the ON/OFF time that is used to control the energy recovering circuit kept in the driver 62 and driving switch device.
Described driving voltage generator 66 produces to be put up voltage Vsetup, negative pole scanning direction voltage Vy, scan bias voltage Vsc and positive extreme direction and keeps voltage Vs, and to scanner driver 60 with keep driver 62 above-mentioned voltage Vsetup, Vy, Vsc and Vs are provided.
Driving voltage generator 66 produces the data voltage Va corresponding to R, G and B data, and provides data voltage Va to data driver 56.
In addition, described driving voltage generator 66 provides the first voltage Vab to data driver 56, and promptly positive extreme direction bias voltage is so that reduce the common voltage breakdown that is caused by data voltage Va.
Below formula 1 expression data voltage Va, scanning voltage Vy, wall voltage Vwall and be used for relation between the ignition voltage Vf of address discharge.
[formula 1]
Va+|V
y|+V
wall＞V
f
As formula 1, the discharging condition of the discharge cell of selecting during addressing period AP is: the summation of data voltage Va, scanning voltage Vy and wall voltage Vwall should be greater than ignition voltage Vf.Specifically, when the summation of data voltage Va, scanning voltage Vy and wall voltage Vwall during, carry out address discharge, and select wherein will keep the discharge cell of discharge greater than ignition voltage Vf.
Equally, owing to can not be applied to scanning voltage Vy and data voltage Va in the switching units of keeping discharge, maintenance is less than the voltage of ignition voltage Vf.This relation can be expressed as formula 2.
[formula 2]
V
ab+|V
y|+V
wall＜V
f
Specifically, owing to only applied the first voltage Vab, wall voltage Vwall and the scanning voltage Vy that imposes on addressing electrode X1 to Xm, so the required voltage that discharges is so much unlike the voltage difference between the data voltage Va and the first voltage Vab.Thus, even if apply the first voltage Vab, in switching units, can not discharge yet.
Therefore, following formula 3 has defined the numerical value of the first voltage Vab.
[formula 3]
GND＜V
ab＜V
f-|V
y|-V
wall
That is to say that the first voltage Vab is more preferably greater than ground voltage GND and less than by deduct the voltage that scanning voltage Vy and wall voltage Vwall are obtained from ignition voltage Vf.
More specifically, the first voltage Vab is numerically greater than 25% (Va/4) of data voltage, and less than by from ignition voltage Vf, deducting the voltage that scanning voltage Vy and wall voltage Vwall are obtained.
Should in the scope that effectively reduces the voltage breakdown that is applied to data driver 56 as far as possible, determine the first voltage Vab, during the cycle that does not apply data pulse DP, not discharge simultaneously.
Fig. 6 has described the data driver according to the plasma display panel device of the embodiment of the invention.
Data driver 56 comprises data voltage source controller 82, first voltage controller 84, ground voltage source controller 86 and data integrated circuit (IC) 88.Described data voltage source controller 82 controls provide data voltage Va to addressing electrode X1 to Xm.84 controls of first voltage controller provide the first voltage Vab to addressing electrode X1 to Xm.86 controls of ground voltage source controller provide ground voltage GND to addressing electrode X1 to Xm.
During addressing period, described data voltage source controller 82 is controlled to addressing electrode X1 to Xm according to the control signal Cx that provides from timing controller 64 data voltage Va is provided.
Described data voltage source controller 82 comprises first switch SW 1 that is coupling between data voltage source Va and the data I C 88.
During addressing period, first voltage controller 84 is controlled to addressing electrode X1 to Xm according to the control signal Cx that provides from timing controller 64 the first voltage Vab is provided.
At this moment, first voltage controller 84 and data voltage source controller 82 alternately drive.Specifically, when data voltage Va being offered addressing electrode X1 to Xm by data voltage source controller 82,84 inoperation of first voltage controller.Yet, when the first voltage Vab being offered addressing electrode X1 to Xm by first voltage controller 84,82 inoperation of data voltage source controller.
First voltage controller 84 comprises second switch SW2 and the 3rd switch SW 3 that is coupled in series between the first voltage source V ab and the data I C88.
When data voltage Va was offered addressing electrode X1 to Xm, the body diode of second switch SW2 prevented that inverse current from flowing into the first voltage source V ab from data I C 88.When ground voltage GND was offered addressing electrode X1 to Xm, the body diode of the 3rd switch SW 3 prevented that inverse current from flowing through from the first voltage source V ab.
In the reset cycle with during keeping the cycle, described ground voltage source controller 86 is controlled to addressing electrode X1 to Xm according to the control signal Cx that provides from timing controller 64 ground voltage GND is provided.
Ground voltage source controller 86 comprises the 4th switch SW 4 that is coupled in parallel to first voltage controller 84 between ground voltage source GND and the data I C 88.
When data voltage Va and the first voltage Vab were offered addressing electrode X1 and Xm, the body diode of the 4th switch SW 4 prevented that inverse current is from data I C 88 inflow place voltage source GND.
Described data I C 88 is coupled to addressing electrode X1 to Xm, and provides data voltage Va, the first voltage Vab and ground voltage GND according to the control signal Cx that provides from timing controller 64 to addressing electrode X1 to Xm.
Described data I C 88 comprises the 5th switch SW 5 that is coupling between data voltage source controller 82 and the addressing electrode X1 to Xm, and is coupling in the 6th switch SW 6 between the common node of addressing electrode X1 to Xm and first voltage controller 84 and ground voltage source controller 86.
In the plasma display panel device of present embodiment, when data driver 56 when addressing electrode X1 to Xm provides data voltage Va, voltage is assigned to the 4th switch SW 4 of second switch SW2 and the 3rd switch SW 3 and the ground voltage source controller 86 of first voltage controller 84.Therefore, the voltage breakdown condition of switch SW 1 to SW4 is reduced.
Fig. 7 has described the drive waveforms that is produced by the plasma display panel device according to the embodiment of the invention.
Described plasma display panel device comprises reset cycle RP, addressing period AP and keeps cycle SP.Described reset cycle RP will be used for the discharge cell of the whole screen of initialization.Addressing period AP will be used to select some discharge cell, and the cycle SP of keeping will be used to keep the discharge condition of selected discharge cell.
During putting of reset cycle RP rises cycle SU, apply positive ramp waveform PR to scan electrode Y.Ground voltage (0 volt) is applied to keeps electrode Z and addressing electrode X.
Therefore, put rise cycle SU during, therefore positive ramp waveform PR carries out dark discharge in whole discharge cell, can produce light between scan electrode Y and addressing electrode X hardly.Simultaneously, dark discharge is also at scan electrode Y with keep between the electrode Z and carry out.
As the result of this dark discharge, put rise cycle SU after, positive wall electric charge is at addressing electrode X and keep on the electrode Z and remain, and on the negative scan electrode Y of wall electric charge in whole discharge cell residue is arranged.
Putting during cycle SD falls in putting after rising cycle SU, NR is applied to scan electrode Y the negative ramp waveform.The voltage of negative ramp waveform NR is reduced to negative erasing voltage Ve with predetermined slope from keeping voltage Vs.
Simultaneously, the voltage Vs that keeps of positive extreme direction is applied to and keeps electrode Z.Ground voltage GND is applied to addressing electrode X.
Described negative ramp waveform NR makes dark discharge carry out in whole discharge cell 54.Simultaneously, described dark discharge is also at scan electrode Y with keep between the electrode Z and carry out.
Therefore, discharge cell 54 has the even wall CHARGE DISTRIBUTION that is optimized for the addressing condition.More particularly, the plussage of the unnecessary wall electric charge that is used for address discharge is wiped from scan electrode Y and addressing electrode X in each discharge cell 54, and the wall electric charge of residue scheduled volume.
When the negative wall electric charge accumulated from scan electrode Y in-migration, the polarity of keeping the wall electric charge on the electrode Z is negative from just changing into.
During the starting stage of addressing period AP, when the first voltage Vab being applied to addressing electrode X and negative pole scanning direction pulse SCNP sequentially is applied to scan electrode Y, data pulse DP with data voltage Va and scanning impulse SCNP are applied to addressing electrode X synchronously.
In addition, the negative pole direction is kept voltage Vs or be applied to less than the positive bias Vzb that the negative pole direction is kept voltage Vs and keep electrode Z.
The first voltage Vas is greater than ground voltage (0 volt) and less than data voltage Va.
Described scanning impulse SCNP is scanning voltage Vsc, and it is from about 0 volt or reduce to negative pole scanning direction voltage-Vy near 0 volt negative pole scanning direction bias voltage.Therefore, during addressing period AP, carry out address discharge between scan electrode Y in onunit and the addressing electrode X, wherein said onunit has been applied in scanning voltage Vsc and data voltage Va.
During keeping cycle SP, the pulse SUSP that keeps that keeps voltage level Vs alternately is applied to scan electrode Y and is kept electrode Z, and ground voltage is applied to addressing electrode X.
In the onunit of selecting by address discharge, in applying the process of keeping pulse SUSP, at scan electrode Y with keep between the electrode Z and keep discharge at every turn.
Yet, during keeping cycle SP, in switching units, do not keep discharge.
In plasma display panel device and driving method thereof, ground voltage is applied to addressing electrode X at reset cycle RP with during keeping cycle SP according to the embodiment of the invention.During not applying the residue addressing period of data pulse DP,, reduce voltage breakdown thus being applied to addressing electrode X greater than ground voltage (0 volt) and less than the first voltage Vab of data voltage Va.
That is to say that the voltage breakdown that is applied to data driver has been reduced positive extreme direction bias voltage Vab and reference voltage, and (0 volt, GND) voltage difference between is so much, has reduced the voltage burden of data driver thus.
Fig. 8 has described the drive waveforms that is produced by the plasma display panel device according to another embodiment of the present invention.
With reference to figure 8, described plasma display panel device comprises reset cycle RP, addressing period AP and keeps cycle SP.Described reset cycle RP will be used for the discharge cell of the whole screen of initialization.Addressing period AP will be used to select some discharge cell, and the cycle SP of keeping will be used to keep the discharge condition of selected discharge cell.
During putting of reset cycle RP rises cycle SU, apply positive ramp waveform PR to scan electrode Y.Ground voltage (0 volt) is applied to keeps electrode Z, and first a voltage Vab of positive extreme direction is applied to addressing electrode X.
The first voltage Vab is greater than ground voltage (0 volt) and less than data voltage Va.
Therefore, put rise cycle SU during, therefore positive ramp waveform PR makes dark discharge carry out in whole discharge cell, can produce light between scan electrode Y and addressing electrode X hardly.Simultaneously, dark discharge is also at scan electrode Y with keep between the electrode Z and carry out.
As the result of this dark discharge, put rise cycle SU after, positive wall electric charge is at addressing electrode X and keep on the electrode Z residue is arranged, and on the negative scan electrode Y of wall electric charge in whole discharge cell residue is arranged.
Putting during cycle SD falls in putting after rising cycle SU, NR is applied to scan electrode Y the negative ramp waveform.The voltage of negative ramp waveform NR is reduced to negative erasing voltage Ve with predetermined slope from keeping voltage Vs.
Simultaneously, the voltage Vs that keeps of positive extreme direction is applied to and keeps electrode Z.The first voltage Vab is applied to addressing electrode X.
Described negative ramp waveform NR makes dark discharge carry out in whole discharge cell 54.Simultaneously, described dark discharge is also at scan electrode Y with keep between the electrode Z and carry out.
Therefore, described discharge cell has the unified wall CHARGE DISTRIBUTION that is optimized for the addressing condition.
More particularly, the plussage of the unnecessary wall electric charge that is used for address discharge is wiped from scan electrode Y and addressing electrode X in each discharge cell 54, and the wall electric charge of residue scheduled volume.
When the negative wall electric charge accumulated from scan electrode Y in-migration, the polarity of keeping the wall electric charge on the electrode Z is negative from just changing into.
During addressing period AP, SCNP sequentially is applied to scan electrode Y negative pole scanning direction signal, and anodal directional data pulsed D P and sweep signal SCNP are applied to addressing electrode Y synchronously.Positive extreme direction kept voltage Vs or be applied to and keep electrode Z less than the positive extreme direction bias voltage Vzb that voltage Vs is kept in positive extreme direction.
Described scanning impulse SCNP is scanning voltage Vsc, and it is from about 0 volt or reduce to negative pole scanning direction voltage-Vy near 0 volt negative pole scanning direction bias voltage.
Therefore, during addressing period AP, carry out address discharge between scan electrode Y in onunit and the addressing electrode X, wherein said onunit has been applied in scanning voltage Vsc and data voltage Va.
During keeping cycle SP, the pulse SUSP that keeps that keeps voltage level Vs alternately is applied to scan electrode Y and is kept electrode Z.
In the onunit of selecting by address discharge, applying when keeping pulse SUSP, at scan electrode Y with keep between the electrode Z and keep discharge at every turn.
Yet, during keeping cycle SP, in switching units, do not keep discharge.
In plasma display panel device and driving method thereof according to present embodiment, do not apply in other periods of data pulse DP at reset cycle RP, in the middle of keeping cycle SP and addressing period AP, be applied to addressing electrode X greater than ground voltage (0 volt) and less than the first voltage Vab of data voltage Va, reduce voltage breakdown thus.
During the period that does not apply data pulse DP, the voltage breakdown that is applied to data driver can reduce by the anodal bias voltage Vab that is applied to addressing electrode X.
That is to say that it is so much to be applied to the voltage difference that the voltage breakdown of data driver has been reduced between positive extreme direction bias voltage Vas and the ground voltage GND, reduced the voltage burden of data driver thus.
Fig. 9 has described by the selection to discharge cell of the drive waveforms that produced by the plasma display panel device according to the embodiment of the invention.
As can be seen from Figure 9, the voltage that offers data driver 56 is changed into data voltage Va and positive extreme direction bias voltage Vab.
Yet the waveform that is used to operate does not change.By applying positive extreme direction bias voltage Vab, rather than, can reduce the breakdown voltage rating of data driver 56 from the ground voltage GND that data driver 56 provides.Therefore, described data driver 56 can be realized with low cost.
In the addressing period interim that data pulse is not provided, it is so much that the voltage breakdown of data driver can reduce positive extreme direction bias voltage, and this is to realize by providing to addressing electrode to have greater than ground voltage and less than the positive extreme direction bias voltage of data voltage.
In addition, because data driver has low breakdown voltage, thus can reduce heat from data driver, and reduce the damage and the fault of drive unit.
Described embodiments of the invention thus, it is evident that, the present invention can change in many aspects.Should not be considered as departing from the spirit and scope of the present invention to this change, all this modifications all are conspicuous for those of ordinary skills, and are included within the scope of claims subsequently.
Claims (19)
1. plasma display panel device comprises:
Plasma display panel with addressing electrode;
Be used for providing data voltage and greater than the data driver of first voltage of ground voltage to addressing electrode; And
Be used to produce first voltage and data voltage and be used for providing the driving voltage generator of described first voltage and described data voltage to data driver.
2. plasma display panel device as claimed in claim 1, wherein said data driver comprises:
Be used to control first voltage controller that first voltage is provided to addressing electrode; And
Be used to control the data voltage source controller that data voltage is provided to addressing electrode.
3. plasma display panel device as claimed in claim 2, wherein said first voltage controller provides first voltage to addressing electrode continuously during addressing period; And the described data voltage source controller and first voltage controller alternately drive.
4. plasma display panel device as claimed in claim 2, wherein said first voltage controller comprises second switch and the 3rd switch.
5. plasma display panel device as claimed in claim 4, wherein said second switch and the 3rd switch include body diode; Wherein the anode terminal of the body diode of second switch is towards the direction setting of the anode terminal of facing the 3rd switch main body diode.
6. plasma display panel device as claimed in claim 1, wherein said first voltage is greater than ground voltage and less than data voltage.
7. plasma display panel device as claimed in claim 1, wherein said data driver provides ground voltage to addressing electrode during the reset cycle.
8. plasma display panel device as claimed in claim 1, wherein said first voltage be greater than ground voltage, and less than the voltage that deducts the summation of scanning voltage that offers scan electrode and the wall voltage that participates in discharge the ignition voltage when beginning to produce discharge.
9. plasma display panel device as claimed in claim 8, wherein said first voltage be greater than 25% of data voltage numerical value, and less than the voltage of the summation that from ignition voltage, deducts scanning voltage that offers scan electrode and the wall voltage that participates in discharge.
10. the driving method of a plasma display panel device, described driving method comprises:
During the reset cycle, provide ground voltage to addressing electrode;
During addressing period, provide first voltage greater than ground voltage to addressing electrode;
During addressing period, provide scan reference voltage to scan electrode;
During addressing period, provide data voltage to addressing electrode; And
During the cycle of keeping, provide ground voltage to addressing electrode.
11. driving method as claimed in claim 10, wherein said first voltage is greater than ground voltage and less than second voltage.
12. driving method as claimed in claim 10, wherein said first voltage be greater than ground voltage, and less than the voltage that deducts the summation of scanning voltage that offers scan electrode and the wall voltage that participates in discharge the ignition voltage when beginning to produce discharge.
13. driving method as claimed in claim 12, wherein said first voltage be greater than 25% of data voltage numerical value, and less than the voltage of the summation that from ignition voltage, deducts scanning voltage that offers scan electrode and the wall voltage that participates in discharge.
14. driving method as claimed in claim 10, wherein said scan reference voltage is less than ground voltage.
15. the driving method of a plasma display panel device, described driving method comprises:
During the reset cycle, provide first voltage greater than ground voltage to addressing electrode;
During addressing period, provide first voltage to addressing electrode;
During addressing period, provide scan reference voltage to scan electrode; And
During addressing period, provide data voltage to addressing electrode.
16. driving method as claimed in claim 15, wherein said first voltage is greater than ground voltage and less than data voltage.
17. driving method as claimed in claim 15, wherein said first voltage be greater than ground voltage, and less than the voltage that deducts the summation of scanning voltage that offers scan electrode and the wall voltage that participates in discharge the ignition voltage when beginning to produce discharge.
18. driving method as claimed in claim 17, wherein said first voltage be greater than 25% of data voltage numerical value, and less than the voltage of the summation that from ignition voltage, deducts scanning voltage that offers scan electrode and the wall voltage that participates in discharge.
19. driving method as claimed in claim 15, wherein said scan reference voltage is less than ground voltage.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050055334 | 2005-06-24 | ||
| KR1020050055335 | 2005-06-24 | ||
| KR1020050055334A KR100765526B1 (en) | 2005-06-24 | 2005-06-24 | Plasma display device and driving method of the same |
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| Publication Number | Publication Date |
|---|---|
| CN1885381A true CN1885381A (en) | 2006-12-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100908337A Pending CN1885381A (en) | 2005-06-24 | 2006-06-26 | Plasma display apparatus and driving method thereof |
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| KR (1) | KR100765526B1 (en) |
| CN (1) | CN1885381A (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2655076B2 (en) * | 1994-04-27 | 1997-09-17 | 日本電気株式会社 | Driving method of plasma display panel |
| JP2003302928A (en) * | 2002-04-12 | 2003-10-24 | Sony Corp | Plasma display device and driving circuit therefor, and driving method |
| KR100515322B1 (en) * | 2003-08-14 | 2005-09-15 | 삼성에스디아이 주식회사 | Driving method of plasma display panel and plasma display device |
-
2005
- 2005-06-24 KR KR1020050055334A patent/KR100765526B1/en not_active IP Right Cessation
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| KR20060135404A (en) | 2006-12-29 |
| KR100765526B1 (en) | 2007-10-10 |
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