KR100515322B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel and a plasma display device. In the driving method of the plasma display panel, an address pulse voltage is applied to the address electrode in a state in which a constant voltage is biased in the address period, so that the bias voltage and the address pulse voltage are generally applied to the address electrode in the address period to perform an address. In this way, a high speed and high efficiency plasma display panel can be realized by reducing the discharge delay and smoothly performing the discharge. In addition, in the address period, the voltage difference between the address electrode and the scan electrode in a region other than the address selection region is reduced to prevent erroneous discharge, and the voltage difference between the address electrode and the sustain electrode is also reduced to prevent unwanted discharge. And, due to the bias voltage application, a unique effect that can reduce the address pulse voltage required for the address discharge occurs.

Description

Plasma display panel driving method and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

The present invention relates to a method of driving a plasma display panel (PDP).

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, a structure of a general plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. In the column direction, address electrodes A ₁ -A _m are arranged, and in the row direction, n rows of scan electrodes Y ₁ -Y _n and sustain electrodes X ₁ -X _n are arranged in pairs.

In the method of driving the plasma display panel, each subfield (which explains waveforms in one subfield for convenience) generally consists of a reset period, an address period, a sustain period, and an erase period.

The reset period is a period for initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period (or scan period, write period) is a cell that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is a period during which the wall charges are accumulated in the addressed cells). The sustain period is a period in which discharge for actually displaying an image is performed on the addressed cell, and the erase period is a period in which the wall discharge of the cell is reduced to end the sustain discharge.

3 is a view showing a driving method of a conventional plasma display panel.

As shown in Fig. 3, all of the discharge cells are discharged by the ramp voltage rising in the reset period so that a large amount of negative charges are accumulated on the scan electrode Y and a large amount of positive charges are stored on the address electrode A. .

Next, a ramp voltage falling on the scan electrode Y is applied to the discharge cell to lower the potential to the ground level while maintaining the wall charge structure. At this time, the wall charges formed in the discharge cells are erased by the rising lamp voltage. In other words, the wall charges accumulated in the discharge cells are erased again.

In the address (or scan) period, a positive voltage is applied to the address electrode A, and a ground level voltage GND is applied to the scan electrode Y as a low level to perform address discharge. In this case, the address operation margin depends on the positive voltage applied to the address electrode. Since the address discharge is performed in this way is determined by the magnitude of the positive voltage Va applied to the address electrode A, excessive wall charges are erased when the ramp voltage is not sufficiently formed or the ramp voltage is applied in the reset period. When the voltage Va applied to the address electrode A needs to be increased. In addition, in order to implement a high resolution plasma display panel, the discharge delay time (the time required to generate an address discharge after applying an address voltage) must be reduced, which is a voltage applied to the address electrode A ( Va) should be increased. In addition, in order to implement a high-efficiency plasma display panel, the voltage Va applied to the address electrode A must be increased.

However, in order to increase the voltage Va applied to the address electrode A, a component having a high breakdown voltage should be used as a component (particularly, a data IC), but this is a large burden on the manufacturing cost of the driving apparatus.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the problems of the prior art, and to provide a method of driving a plasma display panel having a high resolution by shortening an address discharge time without applying a high address pulse voltage applied to an address electrode. will be. The present invention also provides a method of driving a plasma display panel having high efficiency by increasing the address voltage as a whole without applying a high address pulse voltage.

A driving method of a plasma display panel according to an aspect of the present invention for achieving the above object is a plurality of third electrodes formed to intersect a plurality of first and second electrodes, the plurality of first and second electrodes And a method of driving a plasma display panel in which discharge cells are formed by the adjacent first, second and third electrodes, wherein one frame includes a reset period, an address period, and a sustain period, respectively. The plurality of first electrodes are driven by being divided into a plurality of subfields, and in a state in which a first voltage that is a positive voltage is applied to the plurality of second electrodes in an address period of a first subfield of the plurality of subfields. Applying a second voltage to a first electrode corresponding to a discharge cell to be selected; And applying a first pulse to the third voltage corresponding to the discharge cell to be selected from among the plurality of third electrodes while the second voltage is applied. In the reset period of the first subfield, the voltages of the plurality of second electrodes are gradually raised and then lowered. In the sustain period of the first subfield, a sustain voltage, which is a positive voltage, is alternately applied to the plurality of first electrodes and the plurality of second electrodes.

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According to another aspect of the present invention, a plasma display device includes a first substrate, a plurality of first electrodes and second electrodes formed on the first substrate, and a second substrate facing and spaced apart from the first substrate. And a plurality of third electrodes formed on the second substrate in a direction crossing the second electrode, and the first electrodes to discharge the discharge cells formed by the adjacent first, second and third electrodes. And a driving circuit for supplying a driving voltage to a second electrode and a third electrode, wherein the driving circuit includes the plurality of the plurality of second electrodes in a state in which a first voltage, which is a positive voltage, is applied to the plurality of second electrodes in an address period. Applying a second voltage to a first electrode corresponding to a discharge cell to be selected among the first electrodes,

While the second voltage is applied, a first pulse that is imparted to the third voltage is applied to a third electrode corresponding to the discharge cell to be selected among the plurality of third electrodes. Here, the third voltage is a positive voltage, and the driving circuit gradually raises and lowers the voltages of the plurality of first electrodes in a reset period, and drops the plurality of first electrodes and the plurality of electrodes in a sustain period. A sustain voltage, which is a positive voltage, is alternately applied to the second electrode of.

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DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating driving waveforms of the plasma display panel according to an exemplary embodiment of the present invention.

As shown in Fig. 4, the drive waveform according to the embodiment of the present invention includes a reset period, an address period, and a sustain period. In the plasma display panel, a scan / hold driving circuit (not shown) for applying a driving voltage to the scan electrode (Y) and the sustain electrode (X) in each period and an address driving circuit for applying a driving voltage to the address electrode (A) in each period. (Not shown) is connected. The driving circuit and the plasma display panel are connected to form one plasma display device.

The reset period is a period in which the wall charges formed in the sustain period are removed, and the address period is a period in which the discharge cells to be displayed are selected from the discharge cells. The sustain period is a period for discharging the discharge cells selected in the address period.

The reset period is a waveform similar to that of the conventional art of FIG. 3, in which all discharge cells are discharged by rising ramp voltages, whereby a large amount of negative charges are accumulated on the scan electrode Y, and a large amount of positive charges are provided on the address electrode A. FIG. Accumulates. Next, a ramp voltage falling on the scan electrode Y is applied to the discharge cell to lower the potential to the ground level while maintaining the wall charge structure. At this time, the wall charges formed in the discharge cells are erased by the rising lamp voltage. In other words, the wall charges accumulated in the discharge cells are erased again.

Next, in the address period, the address bias voltage V _B is applied so that a constant voltage is biased to the address electrode A. FIG. At this time, the address bias voltage V _B applies a voltage other than 0V in the same direction as the address pulse voltage V _P applied to the address electrode A. FIG. In the state where the address bias voltage V _B is applied, an address pulse voltage V _P is applied to the scan electrode to select a discharge cell. That is, in the address period, the address voltage is applied while the constant bias voltage is applied to the address electrode A. FIG. In addition, OV is applied to the scan electrode Y to select a discharge cell. Therefore, the voltage applied between the scan electrode Y and the address electrode during address discharge becomes V _B + V _P , and when V _B + V _P is higher than the discharge start voltage when other factors such as wall charge are ignored, the discharge is performed. This is disclosed. The method of applying the voltage of the address bias voltage (V _B ) to the address electrode (A) can be driven by the address driving circuit, which can be implemented by charging a constant voltage using a capacitor, the specific method for this is Since it can be implemented by those skilled in the art, a detailed implementation method is omitted below.

Finally, in the sustain period to the discharge cells selected in the address period is generated by applying a sustain voltage V _s intersection between the scan electrode (Y) and the sustain electrode (X). In the sustain period, discharge occurs through a value corresponding to the sum of the wall charge voltage and the sustain voltage. As shown in Fig. 4, the waveform of the sustain period is the same as in the prior art, and therefore, the detailed description thereof will be omitted.

Hereinafter, a specific effect generated when the address bias voltage V _B is applied such that a constant voltage is biased to the address electrode A in the address period as in the embodiment of the present invention will be described.

When the bias voltage is applied to the address electrode as in the embodiment of the present invention, since the discharge start voltage is a constant determined for each plasma display panel, the address pulse voltage V _P and the address bias voltage V _B have one degree of freedom. Have. That is, when the address bias voltage V _B increases, the address pulse voltage V _P decreases, and when the address bias voltage V _B decreases, the address pulse voltage V _P increases. Therefore, the address pulse voltage V _P can be changed by applying the address bias voltage V _B , thereby limiting the address pulse voltage V _P (the address pulse voltage is generally due to a circuit limit). Even if applied at a certain limit), a voltage applied between the address electrode A and the scan electrode X may be higher than that when the bias voltage is not applied. As a result, a high voltage is applied between the address electrode A and the scan electrode X, thereby reducing the discharge delay (referring to a predetermined time required to cause an address discharge between the scan electrode and the address electrode) during the address period, and the discharge is further increased. It occurs actively and the address period is shortened.

This shortening of the address period can address a large number of horizontal lines in a unit time, thereby enabling a high resolution plasma display panel. In addition, a plurality of commonly used address circuits (generally using a double scan to implement a high resolution display panel) can be reduced to one, which causes the effect of lowering the price of the plasma display panel. In other words, the number of circuits can be reduced by changing from a double scan to a single scan by shortening the unit time. In addition, since a higher voltage can be applied in the address period, an address discharge can be induced relatively easily with a gas having high efficiency but difficult to discharge (for example, a gas having a high Xe (xenon) content), etc. It is possible to construct a plasma display panel with high efficiency.

In addition, the address pulse voltage V _P can be reduced by applying the address bias voltage V _B. Increasing the address pulse voltage has a circuit limit, but if the limit is exceeded, a sudden increase in the circuit price can be prevented through the present invention.

When the address bias voltage V _B is applied, the voltage difference between the scan electrode Y and the address electrode becomes | V _B -V _SC | in a region other than the address selection region, as shown in FIG. It is possible to prevent the effect of the discharge in the non-region. That is, in the past, as shown in FIG. 3, the voltage difference of V _SC occurs in a region other than the selection region, which may cause mis-discharge, but the present invention can prevent such mis-discharge.

In general, an unwanted discharge may be caused due to a large voltage difference (V _e as shown in FIG. 3) between the sustain electrode X and the address electrode A in a region other than the selection region in the address period. In the address period as in the embodiment of the present invention, when the address bias voltage V _B is applied, as shown in FIG. 4, the voltage difference between the sustain electrode X and the address electrode A decreases (| V _e -V _B). It is possible to prevent unwanted discharge between the sustain electrode (X) and the address electrode (A).

In addition, the address pulse voltage can be lowered to reduce energy consumption. That is, when applying an address pulse voltage inde generally do not use the energy recovery circuit, wherein the power consumption is reduce an address pulse voltage (V _P) proportional to the square of the address pulse voltage (V _P) as if half The energy consumption is reduced to 1/4.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, by applying a bias voltage in the same direction as the address pulse voltage in the address period, the discharge delay time is reduced and discharge is more actively performed. As a result, an address period can be shortened, and a high resolution plasma display panel can be realized. In addition, since a higher voltage can be applied in the address period, an address discharge can be induced relatively easily with a gas having high efficiency but difficult to discharge (for example, a gas having a high Xe (xenon) content), etc. It is possible to construct a plasma display panel with high efficiency.

In addition, in the address period, the voltage difference between the address electrode and the scan electrode in a region other than the address selection region is reduced to prevent erroneous discharge, and the voltage difference between the address electrode and the sustain electrode is also reduced to prevent unwanted discharge.

And, due to the bias voltage application, a unique effect that can reduce the address pulse voltage required for the address discharge occurs.

1 is a schematic partial perspective view of a typical plasma display panel.

2 is an electrode array diagram of a general plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention.

Claims (7)

And a plurality of third electrodes formed to intersect the plurality of first and second electrodes, the plurality of first electrodes, and the second electrode, and are discharged by the adjacent first, second and third electrodes. In the method of driving a plasma display panel in which a cell is formed, One frame is driven by being divided into a plurality of subfields each including a reset period, an address period, and a sustain period. In the address period of the first subfield of the plurality of subfields, Applying a second voltage to a first electrode corresponding to a discharge cell to be selected from among the plurality of first electrodes while applying a first voltage having a positive voltage to the plurality of second electrodes; And While applying the second voltage, applying a first pulse of the third voltage to a third electrode corresponding to the discharge cell to be selected from among the plurality of third electrodes. Driving method. The method of claim 1, In the reset period of the first subfield, And driving the voltage of the plurality of second electrodes gradually up and down. The method according to claim 1 or 2, And applying the third voltage to a third electrode corresponding to a discharge cell other than the discharge cell to be selected among the plurality of third electrodes. The method according to claim 1 or 2, And wherein the third voltage is a positive voltage. The method according to claim 1 or 2, In the sustain period of the first subfield, And a sustain voltage which is a positive voltage alternately applied to the plurality of first electrodes and the plurality of second electrodes. First substrate, A plurality of first electrodes and second electrodes formed on the first substrate, respectively; A second substrate facing away from the first substrate, A plurality of third electrodes formed on the second substrate in a direction crossing the first and second electrodes, and A driving circuit for supplying a driving voltage to the first electrode, the second electrode, and the third electrode to discharge the discharge cells formed by the adjacent first, second, and third electrodes; The drive circuit, In the address period, a second voltage is applied to a first electrode corresponding to a discharge cell to be selected from among the plurality of first electrodes while a first voltage having a positive voltage is applied to the plurality of second electrodes. And a first pulse applied to a third voltage applied to a third electrode corresponding to the discharge cell to be selected from among the plurality of third electrodes while the second voltage is applied. The method of claim 6, The third voltage is a positive voltage, The drive circuit, Gradually raising and lowering voltages of the plurality of first electrodes in a reset period; And a sustain voltage alternately applied to the plurality of first electrodes and the plurality of second electrodes in a sustain period.