KR100684790B1 - Plasma display and driving method thereof - Google Patents

Abstract

In the plasma display device, a driving waveform is applied to the scan electrode while the sustain electrode is biased to the ground voltage to perform a reset operation, an address operation, and a sustain discharge operation. Then, the driving board driving the sustain electrode can be removed. When the sustain electrode is biased to the ground voltage, a low voltage is applied to the scan electrode in the reset period, so that the potential caused by the wall charge of the scan electrode may be higher than the potential caused by the wall charge of the address electrode. In addition, according to the present invention, by lowering the voltage of the address electrode than the voltage of the sustain electrode in the address period, it is possible to prevent low discharge from occurring at the beginning of the sustain period.

Plasma display, integrated board, voltage difference, scan electrode, sustain electrode

Description

Plasma display device and driving method thereof {PLASMA DISPLAY AND DRIVING METHOD THEREOF}

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

2 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

4 is a driving waveform diagram of a plasma display device according to a first embodiment of the present invention.

5 illustrates a wall charge state after address discharge by the driving waveform of FIG. 4.

6 is a driving waveform diagram of a plasma display device according to a second embodiment of the present invention.

FIG. 7 illustrates a state of wall charge after address discharge by the driving waveform of FIG. 6.

The present invention relates to a method of driving a plasma display panel and a plasma display device.

A plasma display panel is a display panel that displays characters or images by using plasma generated by gas discharge, and tens to millions or more pixels (discharge cells) are arranged in a matrix form according to their size.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

An object of the present invention is to provide a plasma display device having an integrated board capable of driving a scan electrode and a sustain electrode. It is another object of the present invention to provide a driving waveform suitable for an integrated board.

According to an aspect of the present invention, a method of driving a plasma display device includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. In the plasma display device including an electrode, the discharge cell is formed at the intersection of the first electrode, the second electrode and the third electrode to drive one frame divided into a plurality of subfields,

In at least one subfield where the second electrode is biased with a first voltage,

Applying a reset waveform to the first electrode to initialize the discharge cell, sequentially applying a second voltage to the first electrode, and applying a third voltage lower than the first voltage to the third electrode and the third voltage; Selectively selecting a discharge cell to be turned on by selectively applying a fourth voltage lower than three voltages, and applying a sustain discharge pulse alternately having a high level voltage and a low level voltage to the first electrode.

A plasma display device according to an aspect of the present invention includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and A driving board is applied to the second electrode and the third electrode to apply a driving waveform for displaying an image and to bias the first electrode to a first voltage while the image is displayed. A chassis base facing the plasma display panel;

The drive board,

In at least one subfield, bias the second electrode to a first voltage in an address period, sequentially apply a second voltage to the first electrode, and apply a third voltage lower than the first voltage to the third electrode. And selectively apply a fourth voltage lower than the third voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a schematic conceptual view of a plasma display panel according to an exemplary embodiment of the present invention. 3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 1, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 2, the plasma display panel 10 includes a plurality of address electrodes A1 to Am extending in the vertical direction, a plurality of scan electrodes Y1 to Yn extending in the horizontal direction, and a plurality of sustain electrodes X1 to Xn). The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 10 includes an insulating substrate on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and an insulating substrate on which address electrodes A1 to Am are arranged. The two insulating substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. . At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a cell (12 in FIG. 1).

As shown in FIG. 3, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 4, the plasma display apparatus for dual driving is described as an example. However, in the case of the single driving, the address buffer board 100 is disposed at any one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage for selecting a discharge cell to be displayed to each address electrode A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, the scan drive board 200 is electrically connected to the scan electrodes Y1 to Yn via the scan buffer board 300, and the sustain electrode. (X1 to Xn) are biased at a constant voltage. The scan buffer board 300 applies a voltage for sequentially selecting the scan electrodes Y1 to Yn in the address period to the scan electrodes Y1 to Yn. The scan driving board 200 receives a driving signal from the image processing and control board 400 and applies a driving voltage to the scan electrodes Y1 to Yn. In FIG. 3, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. Each is applied to the address driving board 100 and the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display device according to the first embodiment of the present invention will be described with reference to FIGS. 4 and 5.

FIG. 4 is a driving waveform diagram of the plasma display panel according to the first exemplary embodiment of the present invention, and FIG. 5 is a diagram showing a wall charge state after address discharge in the driving waveform of FIG. 4. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 5, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (the ground voltage in FIG. 4), the description of the voltage applied to the X electrode is omitted.

4, one subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period during the reset period, the voltage of the Y electrode is gradually increased from the Vs voltage to the Vset voltage while maintaining the A electrode at the reference voltage (0 V in FIG. 5). In FIG. 5, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 5, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally a voltage higher than the voltage applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period during the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the negative Vnf voltage while the A electrode is maintained at the reference voltage. Then, a slight discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, so that the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode The charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. Then, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby the discharge cells in which the address discharge has not occurred in the address period can be prevented from erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, in the address period, a scan pulse having a negative VscL voltage and an address pulse having a positive Va voltage are applied to the Y electrode and the A electrode to select a discharge cell to be turned on in the sustain period. The unselected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the discharge cell that will not be turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a discharge cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the discharge cells formed by the corresponding Y electrode.

Specifically, first, a scan pulse of the VscL voltage is applied to the scan electrodes of the first row (Y1 in FIG. 2), and an address pulse of Va voltage is applied to the A electrode located in the discharge cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode (Y2 in FIG. 3) of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be described. When the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A and Y electrodes and the external voltage Vnf between the A and Y electrodes is determined by the discharge start voltage Vfay between the A and Y electrodes. do. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, in the discharge cell in which the address discharge occurred in the address period, the wall voltage Vwxy of the Y electrode with respect to the X electrode was formed with a high voltage. Therefore, in the sustain period, a pulse having a Vs voltage is first applied to the Y electrode and the X electrode in the sustain period. A sustain discharge is caused between the electrodes. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is higher than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X are repeated by the number of times corresponding to the weight indicated by the corresponding subfield. .

As described above, in the first embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board for driving the X electrode can be removed, and only by biasing the X electrode to the reference voltage.

Meanwhile, according to the first embodiment of the present invention, a positive Va voltage is applied to the A electrode in the address period while the X electrode is biased to the reference voltage. Therefore, in the address period, since the potential of the A electrode is higher than that of the X electrode, the negative charges generated by the address discharge move to the A electrode as shown in FIG. 5 to form wall charges.

Thus, according to the first embodiment of the present invention, since sufficient wall charges are not formed between the X electrode and the Y electrode in the address period, the sustain discharge may not occur properly in the subsequent sustain period.

To compensate for this, a positive bias voltage is applied to the X electrode in the address period so that wall charges formed by the address discharge accumulate on the X electrode and the Y electrode, but in this case, a board for applying the bias voltage to the X electrode And switch is required.

Therefore, the second embodiment of the present invention proposes a method for sufficiently stacking the wall charges on the X electrode and the Y electrode after the address period while maintaining the X electrode at the reference voltage in the address period.

FIG. 6 is a driving waveform diagram according to a second exemplary embodiment of the present invention, and FIG. 7 is a diagram illustrating a wall charge state after address discharge in the driving waveform of FIG. 6.

As shown in FIG. 6, in the driving waveform according to the second embodiment of the present invention, a negative address voltage Va ′ is applied to the A electrode in the address period, and the voltage of the A electrode is applied in the period other than the address period. Maintain a negative voltage lower than the Va 'voltage. Waveforms in other sections are the same as in the first embodiment of the present invention, and thus redundant description thereof will be omitted.

As described above, when the negative voltage Va 'is applied to the A electrode while the X electrode is biased to the reference voltage (0 V) in the address period, the potential of the X electrode is higher than the potential of the A electrode. Therefore, the positive charge generated by the address discharge moves to the Y electrode to form wall charges, and the negative charge mostly moves to the X electrode having a higher potential than the A electrode to form wall charges. Therefore, as shown in Fig. 7, sufficient wall charges are formed in the X electrode and the Y electrode after the address discharge.

Thus, when the sustain discharge pulse is applied in the sustain period while the wall charges are sufficiently accumulated on the X electrode and the Y electrode, the discharge occurs smoothly by the wall charge formed by the address discharge.

As described above, according to the first and second embodiments of the present invention, since the driving waveform is applied only to the Y electrode while the X electrode is biased to a predetermined voltage, the reset operation, the address operation, and the sustain discharge operation can be performed. The board driving the X electrode can be removed.

In addition, by setting the bias voltage and the address voltage applied to the A electrode to a negative voltage so that the wall charges formed by the address discharge are sufficiently accumulated on the X electrode and the Y electrode, the sustain discharge can be caused more effectively.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

For example, in the exemplary embodiment of the present invention, the driving waveform is applied to the Y electrode while the X electrode is biased at a constant voltage. However, the driving waveform is applied to the X electrode while the Y electrode is biased at the constant voltage. You may.

In addition, in the exemplary embodiment of the present invention, the case in which the X electrode is biased to a predetermined voltage over the entire driving period has been described, but the present invention is not limited thereto.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the integrated board for removing the board driving the sustain electrode and driving with only one board can be implemented. As a result, the unit cost is reduced.

According to the present invention, since the pulse for sustain discharge is supplied only from the scan driving board, the impedance is always constant.

Further, according to the present invention, low discharge can be prevented from occurring at the beginning of the sustain period by applying a negative voltage to the address electrode in the address period and maintaining the voltage of the X electrode at the reference voltage.

Claims (8)

A plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and intersecting the first electrode, the second electrode, and the third electrode; In a plasma display device in which discharge cells are formed at a point, a frame is driven by dividing a frame into a plurality of subfields. In at least one subfield where the second electrode is biased with a first voltage, Applying a reset waveform to the first electrode to initialize the discharge cell; Selecting a discharge cell to be turned on by sequentially applying a second voltage to the first electrode and selectively applying a third voltage lower than the first voltage and a fourth voltage lower than the third voltage to the third electrode. ; And Applying a sustain discharge pulse alternately having a high level voltage and a low level voltage to the first electrode; Method of driving a plasma display device comprising a. The method of claim 1, In the step of applying the reset waveform and the step of applying the sustain discharge pulse, And a method of driving the plasma display device by biasing the third electrode to the fourth voltage. The method according to claim 1 or 2, And a discharge cell formed at an intersection of the first electrode to which the second voltage is applied and the third electrode to which the third voltage is applied is selected as a discharge cell to be turned on. The method according to claim 1 or 2, And the first voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and A driving board is applied to the second electrode and the third electrode to apply a driving waveform for displaying an image and to bias the first electrode to a first voltage while the image is displayed. A chassis base facing the plasma display panel; The drive board, In at least one subfield, Biasing the second electrode to a first voltage in an address period, sequentially applying a second voltage to the first electrode, and applying a third voltage lower than the first voltage and lower than the third voltage to the third electrode; Selectively applying a fourth voltage Plasma display device. The method of claim 5, The drive board, Biasing the third electrode to the fourth voltage in a reset period or a sustain period Plasma display device. The method of claim 6, And a discharge cell to be turned on at the intersection of the first electrode to which the second voltage is applied and the third electrode to which the third voltage is applied. The method according to any one of claims 5 to 7, And the first voltage is a ground voltage.

Images