KR100590047B1 - Plasma display device and driving method thereof - Google Patents

Abstract

In the plasma display device, a driving waveform is applied to the scan electrode while the sustain electrode is biased to the ground voltage to perform a reset operation, an address operation, and a sustain discharge operation. Then, the driving board driving the sustain electrode can be removed. In the sustain period of the subfield having the main reset which alternately applies the high voltage and the low voltage, the sustain discharge pulse applied to the scan electrode Y is divided into a plurality of groups in the order of application, and finally The width of at least one sustain discharge pulse of the group containing the sustain discharge pulses of the low voltage applied is made shorter than the width of the sustain discharge pulses of the other groups. In addition, after applying the last sustain discharge pulse of low voltage to the scan electrode, the voltage of the scan electrode is gradually increased. This allows the subsequent auxiliary reset to erase as many wall charges as desired.

PDP, integrated board, impedance, electrode, discharge, sustain discharge pulse, narrow, gap, charge

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

2 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

4 to 7 are driving waveform diagrams of the plasma display device according to the first to fourth embodiments of the present invention.

The present invention relates to a plasma display device and a driving method thereof.

Plasma display devices are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix form according to their size.

In the panel of the plasma display device, scan electrodes and sustain electrodes parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

According to a general method of driving a plasma display device, one frame is divided into a plurality of subfields to be driven, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

An object of the present invention is to provide a plasma display device having an integrated board capable of preventing excessive discharge in an address period and a sustain period, and capable of driving a scan electrode and a sustain electrode. It is another object of the present invention to provide a driving waveform suitable for an integrated board.

In order to solve this problem, the present invention applies a drive waveform to the scan electrode while the sustain electrode is biased at a constant voltage.

According to an aspect of the present invention, a frame is included in a plasma display device including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. The driving method includes a second voltage higher than the first voltage and the first voltage at the second electrode in a state in which the voltage of the first electrode is biased to the first voltage in the sustain period of at least one subfield. Applying a sustain discharge pulse alternately having a lower third voltage, and gradually applying a sustain discharge pulse of the third voltage to the second electrode in time, and then gradually increasing the voltage of the second electrode; A group including the last sustain discharge pulse in time when the plurality of sustain discharge pulses applied to the second electrode are divided into a plurality of groups according to the order in which the sustain discharge pulses are applied to the second electrode; The width of at least one sustain discharge pulse of is shorter than the width of the sustain discharge pulses of the remaining groups.

In this case, the voltage of the second electrode may be gradually increased from a voltage higher than the third voltage to the second voltage.

In addition, the driving method can perform initialization for the discharge cells in which sustain discharge has occurred in the immediately preceding subfield in the sustain period and subsequent reset period.

In addition, in the driving method, the first electrode may be biased to the first voltage in the reset period and the address period, and the first voltage may be the ground voltage.

According to another feature of the present invention, a plasma display panel includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. The plasma display panel applies a driving waveform to the second electrode and the third electrode to display an image, biases the first electrode to a first voltage in a sustain period, and applies the second electrode to the second electrode rather than the first voltage. A plasma display device including a driving board alternately applying a high second voltage and a third voltage lower than the first voltage is provided. At this time, the driving board divides the sustain discharge pulse applied to the second electrode in the sustain period into a plurality of groups according to the order of application, and sustain discharge of the third voltage last applied to the second electrode. The width of the at least one sustain discharge pulse of the group including the pulse is shorter than the width of the sustain discharge pulse of the other group, and after applying the last sustain discharge pulse of the third voltage to the second electrode, the second electrode Gradually increase the voltage of.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A plasma display device and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a schematic conceptual view of a plasma display panel according to an exemplary embodiment of the present invention. 3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 1, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed on the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 2, the plasma display panel 10 includes a plurality of address electrodes A1 to Am extending in the vertical direction, a plurality of scan electrodes Y1 to Yn extending in the horizontal direction, and a plurality of sustain electrodes X1 to Xn). The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 10 includes a substrate on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a substrate on which address electrodes A1 to Am are arranged. The two substrates are arranged to face each other with the discharge spaces interposed so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms the cell 12.

As shown in FIG. 3, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 3, the plasma display apparatus for dual driving is described as an example. However, in the case of the single driving, the address buffer board 100 is disposed at any one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage for selecting a discharge cell to be displayed to each address electrode A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, the scan drive board 200 is electrically connected to the scan electrodes Y1 to Yn via the scan buffer board 300, and the sustain electrode. (X1 to Xn) are biased at a constant voltage. The scan buffer board 300 applies a voltage for sequentially selecting the scan electrodes Y1 to Yn in the address period to the scan electrodes Y1 to Yn. The scan driving board 200 receives a driving signal from the image processing and control board 400 and applies a driving voltage to the scan electrodes Y1 to Yn. In FIG. 3, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. Each is applied to the address driving board 100 and the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display device according to the first exemplary embodiment of the present invention will be described in detail with reference to FIG. 4.

4 is a driving waveform diagram of a plasma display device according to a first embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 4, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (ground voltage in FIG. 4), the description of the voltage applied to the X electrode is omitted.

In addition, only two subfields of the plurality of subfields are illustrated in FIG. 4, and for convenience, the two subfields are illustrated as first and second subfields, respectively. The reset period of the first subfield is shown as consisting of a rising period and a falling period, and the reset period of the second subfield is shown as being a falling period. That is, in the reset period of the first subfield, all the discharge cells are initialized, and in the reset period of the second subfield, initialization is performed for the discharge cells in which the sustain discharge has occurred in the first subfield. Here, the reset period of the first subfield including the rising period and the falling period may be defined as a “main reset period”, and the reset period of the second subfield including the falling period may be defined as an “auxiliary reset period”.

4, the first subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period of the reset period of the first subfield, the voltage of the Y electrode is gradually increased from the voltage of Vs to the voltage of Vset while maintaining the A electrode at the reference voltage (0 V in FIG. 4). In FIG. 4, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 4, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally a voltage higher than the voltage applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the A electrode is maintained at the reference voltage. Then, a slight discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, so that the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode The charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, a scan pulse of the VscL voltage is applied to the Y electrode (Y1 of FIG. 2) in the first row, and an address pulse of Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, a scan pulse of VscL voltage is applied to the Y electrode (Y2 in FIG. 2) of the second row while an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be described. When the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A and Y electrodes and the external voltage Vnf between the A and Y electrodes is determined by the discharge start voltage Vfay between the A and Y electrodes. do. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, in the cell where the address discharge occurred in the address period, the wall voltage Vwxy of the Y electrode with respect to the X electrode was formed with a high voltage. In the sustain period, the Y electrode and the X electrode were first applied with a pulse having a Vs voltage to the Y electrode. It causes maintenance discharge between them. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is lower than the voltage Vfxy. As a result of the sustain discharge, negative wall charges are formed on the Y electrode and positive wall charges are formed on the X electrode and the A electrode, and the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of alternately applying the sustain discharge pulses of the Vs voltage and the -Vs voltage to the Y electrode is repeated the number of times corresponding to the weight indicated by the corresponding subfield.

As described above, the reset period of the second subfield is formed only in the falling period, and in the reset period of the second subfield, the sustain discharge pulse of the voltage Vs is applied to the Y electrode in the sustain period of the first subfield. The voltage at the electrode is gradually reduced to the voltage Vnf.

At this time, when sustain discharge occurs in the sustain period of the first subfield, since negative (−) wall charges are formed on the Y electrode and positive (+) wall charges are formed on the X electrode and the A electrode, the voltage of the Y electrode is gradually decreased. If the discharge start voltage is exceeded together with the wall voltage formed in the cell, the weak discharge occurs as in the falling period of the reset period of the first subfield. Since the final voltage Vnf of the Y electrode is the same as the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield ends in the falling period of the first subfield. It becomes substantially the same as the later wall charge state.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, discharge does not occur when the voltage of the Y electrode decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge.

Since the driving waveform after the reset period of the second subfield is the same as the first subfield, a description thereof will be omitted. However, the number of times of repeating the process of applying the sustain discharge pulse of the voltage Vs and the voltage -Vs to the Y electrode in the sustain period is different.

As described above, in the first embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed using only a driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

In general, when the voltage of the electrode changes slowly, discharge occurs only near the gap between the X electrode and the Y electrode, and charge is formed only near the gap. However, when a strong discharge such as a sustain discharge occurs, the discharge occurs in the X electrode and the Y electrode. Electric charge may be formed in the entire electrode by diffusing into the gap. As described above, when the auxiliary reset is performed after the charge is formed by the sustain discharge, the charge formed in the electrode may not be erased and a large amount of charge may remain. If such a large amount of charge remains, excessive discharge may occur during discharge in the address period and the sustain period. An embodiment capable of preventing such an excessive discharge will be described in detail with reference to FIG. 5.

5 is a driving waveform diagram of a plasma display device according to a second embodiment of the present invention.

인 경우에, Y 전극에 Vs 전압의 마지막 유지방전 펄스가 인가되기 직전 Y 전극에 인가되는 -Vs 전압의 유지방전 펄스의 폭을

정도로 할 수 있다. 이처럼 Y 전극에 마지막으로 인가되는 유지방전 펄스 직전에 인가되는 -Vs 전압의 유지방전 펄스의 폭을 세폭으로 하면, 일반적인 유지방전과 달리 소규모의 강한 방전이 일어나서 Y 전극과 X 전극에 벽 전하가 형성되지 않는다. 따라서, 이전 유지방전에 의해 간극 부근 외에 전극 내부에 형성된 전하까지 소거할 수 있게 된다.As shown in Fig. 5, the width of the sustain discharge pulse of the -Vs voltage applied to the Y electrode immediately before the last sustain discharge pulse of the Vs voltage is applied to the Y electrode in the sustain period is narrower than the width of the other sustain discharge pulses. . For example, the width of the sustain discharge pulse applied to the Y electrode

In this case, the width of the sustain discharge pulse of the -Vs voltage applied to the Y electrode immediately before the last sustain discharge pulse of the Vs voltage is applied to the Y electrode.

I can do that. As such, when the width of the sustain discharge pulse of the -Vs voltage applied immediately before the sustain discharge pulse applied to the Y electrode is made narrow, a small strong discharge occurs unlike the general sustain discharge, and wall charges are formed on the Y electrode and the X electrode. It doesn't work. Therefore, it is possible to erase the electric charges formed in the electrodes in addition to the gap vicinity by the previous sustain discharge.

In addition, after the sustain discharge pulse of -Vs voltage is applied to the Y electrode in a narrow period, the voltage of the Y electrode is gradually increased from 0 V to the Vs voltage without applying the sustain discharge pulse of the Vs voltage. Then, when the discharge start voltage between the Y electrode and the X electrode is exceeded while the voltage of the Y electrode is increased, a weak discharge occurs between the Y electrode and the X electrode. In this case, since charges are generated only in the vicinity of the gap of the electrode due to the weak discharge, the wall charges can be erased as desired by a subsequent auxiliary reset. Therefore, the wall charges can be sufficiently controlled in the reset period of the second subfield, thereby preventing excessive discharge in the address period.

In the second embodiment of the present invention, the last sustain discharge pulse applied to the X electrode has a narrow width, but it may be different according to the state of the panel. Hereinafter, such an embodiment will be described in detail with reference to FIG. 6.

6 is a driving waveform diagram of a plasma display device according to a third exemplary embodiment of the present invention.

As shown in FIG. 6, a plurality of groups G1 and G2 are arranged in the order in which a plurality of sustain discharge pulses of the Vs voltage or the -Vs voltage are applied to the Y electrode except the sustain discharge pulse last applied to the Y electrode in the sustain period. GN), and the pulse of the group GN including the sustain discharge pulse applied last in time is narrowed. This makes it possible to erase more wall charges in the sustain period than in the second embodiment of the present invention.

In the first to third embodiments of the present invention, the voltage of the Y electrode is decreased from the voltage of Vs to the voltage of Vnf in the falling period of the reset period of the first and second subfields. You do not have to. Hereinafter, such an embodiment will be described in detail with reference to FIG. 7.

7 is a driving waveform diagram of a plasma display device according to a fourth embodiment of the present invention.

As shown in FIG. 7, it is the same as the third embodiment of FIG. 6 except that the start voltage of the Y electrode is equal to or lower than the Vs voltage in the falling period of the reset period.

In the falling period of the reset period, the weak discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases. That is, since the discharge does not occur until the voltage difference between the Y electrode and the X electrode becomes equal to or higher than the discharge start voltage while the voltage of the Y electrode decreases, the start voltage of the Y electrode can be set to a voltage lower than the Vs voltage in the falling period. Setting the falling start voltage of the Y electrode to a low voltage makes it possible to more gently set the falling slope of the Y electrode in a given falling period. Then, even when the strong discharge occurs in the rising period, the strong discharge can be prevented because the voltage of the Y electrode changes at a slower speed than in the third embodiment. At this time, an additional power source may not be used when the falling start voltage of the Y electrode is set to the reference voltage (0V).

For example, when the falling start voltage of the Y electrode is 0 V, the difference between the voltage applied to the X electrode and the Y electrode from the outside at the time of falling of the Y electrode and the difference of the voltage applied to the A electrode and the Y electrode are all 0 V and thus discharged. This does not happen. Next, when the voltage of the Y electrode gradually decreases from 0V, weak discharge occurs when the difference between the wall voltage formed in the cell and the voltage applied from the outside exceeds the discharge start voltage, so that the wall charge can be set. In the fourth exemplary embodiment of FIG. 7, the falling start voltage of the Y electrode is set to 0V. By doing in this way, strong discharge can be prevented in the rise period of a reset period, and a fall period can also be shortened.

As shown in FIG. 7, the A electrode can be biased to a constant voltage in the rising period of the reset period of the first subfield. In this case, when the Va voltage is used as the bias voltage of the A electrode as illustrated in FIG. 7, an additional power source may not be used. When the voltage of the Y electrode is increased while the voltage of the A electrode is biased to the Va voltage, the voltage between the A electrode and the Y electrode is smaller than in the third embodiment, so that the voltage between the X electrode and the Y electrode is equal to the A electrode and the Y electrode. The discharge start voltage is exceeded before the voltage in between. Then, a weak discharge occurs first between the X electrode and the Y electrode, and the voltage between the A electrode and the Y electrode exceeds the discharge start voltage while the priming particles are formed by the weak discharge. The priming particles reduce the discharge delay between the A electrode and the Y electrode, so that a weak discharge is performed without generating a strong discharge, thereby forming a desired amount of wall charge.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the board for driving the sustain electrode can be removed. In other words, it is possible to implement an integrated board that is substantially driven by only one board, thereby reducing the unit cost.

In the case where the scan electrode and the sustain electrode are implemented as the respective driving boards, since the driving waveforms in the reset period and the address period are mainly supplied from the scan driving board, impedances formed in the scan driving board and the sustain driving board are different. Accordingly, the sustain discharge pulse applied to the scan electrode and the sustain discharge pulse applied to the sustain electrode in the sustain period may be different. However, according to the present invention, since the pulse for sustain discharge is supplied only from the scan driving board, the impedance is always constant.

Further, a plurality of groups in accordance with the order in which the sustain discharge pulses applied to the scan electrodes Y are applied in the sustain period of the subfield having the main reset which alternately applies the sustain discharge pulses having the high voltage and the low voltage alternately to the scan electrodes only. After dividing by and narrowing down at least one sustain discharge pulse of the group including a sustain discharge pulse having a low voltage applied last to the scan electrode Y, and applying the last sustain discharge pulse having a low voltage to the scan electrode In addition, by controlling the amount of the wall charge so as to gradually increase the voltage of the scan electrode to sufficiently control the wall charge in the subfield having a subsequent reset, excessive discharge is prevented in the later address period and the sustain period.

Claims (8)

In a plasma display device including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In a state in which the voltages of the plurality of first electrodes are biased to a first voltage, In the sustain period of at least one first subfield of the plurality of subfields,  Applying a plurality of sustain discharge pulses alternately having a second voltage higher than the first voltage and a third voltage lower than the first voltage to the plurality of second electrodes, and Gradually increasing the voltage of the plurality of second electrodes after the last sustain discharge pulse having the third voltage is applied to the plurality of second electrodes Including; When dividing the plurality of sustain discharge pulses into a plurality of groups according to the order applied to the plurality of second electrodes, And a width of at least one sustain discharge pulse of a group including sustain discharge pulses last applied to the plurality of second electrodes is shorter than a width of the sustain discharge pulses of the remaining groups. The method of claim 1, And a method of initializing a discharge cell in which sustain discharge has occurred in the first subfield in a reset period of a second subfield subsequent to a sustain period of the first subfield among the plurality of subfields.  The method of claim 2, And a voltage of the plurality of second electrodes is gradually increased from a voltage higher than the third voltage to the second voltage. The method according to any one of claims 1 to 3, And the first electrode is biased at a first voltage in a reset period and an address period. The method of claim 4, wherein And the first voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and The plurality of second electrodes and the plurality of third electrodes are applied with a driving waveform for displaying an image by the plasma display panel, and the plurality of first electrodes are biased with a first voltage in a sustain period. A driving board applying a plurality of sustain discharge pulses alternately having a second voltage higher than the first voltage and a third voltage lower than the first voltage to a second electrode of The drive board, Dividing the plurality of sustain discharge pulses into a plurality of groups according to an order applied to the plurality of second electrodes, Making the width of at least one sustain discharge pulse of the group including the sustain discharge pulses having a third voltage last applied to the plurality of second electrodes shorter than the width of the sustain discharge pulses of the other groups, And applying a last sustain discharge pulse having the third voltage to the plurality of second electrodes, and gradually increasing the voltages of the plurality of second electrodes to the second voltage. The method of claim 6, And a reset operation for the cells in which sustain discharge has occurred in the sustain period in the reset period of the subfield subsequent to the sustain period. The method according to claim 6 or 7, And the plurality of first electrodes are biased to the first voltage in a reset period and an address period.

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