KR20060019857A - Plasma display device and driving method of plasma display panel - Google Patents

Abstract

In the plasma display panel, a driving waveform is applied to the scan electrode while the sustain electrode is biased to the ground voltage to perform a reset operation, an address operation, and a sustain discharge operation. Then, the driving board driving the sustain electrode can be removed. When a high voltage is applied to the scan electrode while applying a sustain discharge pulse having alternating high and low voltages to the scan electrode, overdischarge may occur because negative ions formed in the sustain electrode move only to the scan electrode. When a low voltage is applied to the scan electrode, negative ions formed on the scan electrode are dispersed in the sustain electrode and the address electrode, so that discharge is less likely to occur and low discharge may occur. Therefore, the time taken for applying the sustain discharge pulse from the high voltage to the low voltage in the sustain period is made shorter than the time taken for applying the low voltage to the high voltage. In this manner, overdischarge and low discharge can be prevented in the sustain period.

PDP, integrated board, impedance, electrode, negative ion, sustain discharge pulse, sustain period

Description

Plasma display device and plasma display panel driving method {PLASMA DISPLAY DEVICE AND DRIVING METHOD OF PLASMA DISPLAY PANEL}

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

2 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

4 to 5 are driving waveform diagrams of the plasma display panel according to the first and second embodiments of the present invention.

6A and 6B are diagrams illustrating the presence or absence of overdischarge and low discharge while varying T1 and T2 in the driving waveform of FIG. 5, respectively.

The present invention relates to a method of driving a plasma display panel and a plasma display device.

A plasma display panel is a display panel that displays characters or images by using plasma generated by gas discharge, and tens to millions or more pixels (discharge cells) are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, a scan driving board for driving the scan electrodes and a sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

An object of the present invention is to provide a plasma display device having an integrated board capable of driving a scan electrode and a sustain electrode. It is another object of the present invention to provide a driving waveform suitable for an integrated board.

In order to solve this problem, the present invention applies a drive waveform to the scan electrode while the sustain electrode is biased at a constant voltage.

According to an aspect of the present invention, a frame is formed in a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. The driving method includes the second voltage in a sustain period in which a second voltage and a third voltage lower than the second voltage are alternately applied to the second electrode while the voltage of the first electrode is biased to the first voltage. Alternately applying the second voltage and the third voltage to the electrode may include increasing the voltage of the second electrode from the third voltage to the second voltage for a first time period. Applying a second voltage, decreasing the voltage of the second electrode from the second voltage to the third voltage for a second time different from the first time, and applying the third voltage to the second electrode. Applying.

이며, 상기 제2 시간은

일 수 있다.In this case, the first time is longer than the second time, and the first time is

Wherein the second time is

Can be.

In the driving method, the first electrode may be biased with a first voltage in a reset period and an address period, and the first voltage may be a ground voltage.

According to another feature of the present invention, a plasma display panel includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. And a driving board applying a driving waveform to the second electrode and the third electrode to display an image on the plasma display panel and biasing the first electrode to a first voltage while the image is displayed. Is provided. In this case, the driving board alternately applies a second voltage and a third voltage lower than the second voltage to the second electrode in the sustain period, and applies the voltage of the second electrode to the third voltage at the third voltage. The first time of changing the second voltage is longer than the second time of changing the voltage of the second electrode from the second voltage to the third voltage.                     

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a schematic conceptual view of a plasma display panel according to an exemplary embodiment of the present invention. 3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 1, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 2, the plasma display panel 10 includes a plurality of address electrodes A1 to Am extending in the vertical direction, a plurality of scan electrodes Y1 to Yn extending in the horizontal direction, and a plurality of sustain electrodes X1 to Xn). The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 10 includes a substrate on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a substrate on which address electrodes A1 to Am are arranged. The two substrates are arranged to face each other with the discharge spaces interposed so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a cell.

As shown in FIG. 3, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 3, the plasma display apparatus for dual driving is described as an example. However, in the case of the single driving, the address buffer board 100 is disposed at any one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage for selecting a discharge cell to be displayed to each address electrode A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, the scan drive board 200 is electrically connected to the scan electrodes Y1 to Yn via the scan buffer board 300, and the sustain electrode. (X1 to Xn) are biased at a constant voltage. The scan buffer board 300 applies a voltage for sequentially selecting the scan electrodes Y1 to Yn in the address period to the scan electrodes Y1 to Yn. The scan driving board 200 receives a driving signal from the image processing and control board 400 and applies a driving voltage to the scan electrodes Y1 to Yn. In FIG. 3, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. Each is applied to the address driving board 100 and the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display panel according to the first exemplary embodiment of the present invention will be described in detail with reference to FIG. 4.                     

4 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 4, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (ground voltage in FIG. 4), the description of the voltage applied to the X electrode is omitted.

4, one subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period of the reset period, the voltage of the Y electrode is gradually increased from the voltage of Vs to the voltage of Vset while the A electrode is maintained at the reference voltage (0 V in FIG. 4). In FIG. 4, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 4, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, the state of all cells must be initialized, so the voltage Vset is high enough to cause discharge in the cells of all conditions. In addition, the Vs voltage is generally a voltage higher than the voltage applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the A electrode is maintained at the reference voltage. Then, a slight discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, so that the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode The charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, the scan pulse of the VscL voltage is applied to the scan electrodes of the first row (Y1 in FIG. 2), and the address pulse of the Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, a scan pulse of VscL voltage is applied to the Y electrode (Y2 in FIG. 2) of the second row while an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be described. When the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A and Y electrodes and the external voltage Vnf between the A and Y electrodes is determined by the discharge start voltage Vfay between the A and Y electrodes. do. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the delay time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage in order to better generate address discharge.

Next, in the cell where the address discharge occurred in the address period, the wall voltage Vwxy of the Y electrode with respect to the X electrode was formed with a high voltage. In the sustain period, the Y electrode and the X electrode were first applied with a pulse having a Vs voltage to the Y electrode. It causes maintenance discharge between them. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is lower than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage and the -Vs voltage to the scan electrode Y is repeated a number of times corresponding to the weight indicated by the corresponding subfield.                     

As described above, in the first embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed using only a driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

4, in the first embodiment of the present invention, when the Vs voltage is applied to the Y electrode in the sustain period, since the Y electrode actually acts as an anode, negative ions formed in the X electrode move only toward the Y electrode. In addition, excessive discharge of negative ions may occur to the Y electrode. On the other hand, when the -Vs voltage is applied to the Y electrode, since the X electrode and the A electrode actually act as an anode, negative ions formed in the Y electrode are dispersed and moved between the X electrode and the A electrode. If the negative ions are not supplied sufficiently, the discharge may not occur well or the discharge may occur weakly, resulting in low discharge. Accordingly, an embodiment in which negative ions are controlled in the discharge space between the Y electrode and the X electrode to cause stable discharge in the sustain period will be described in detail with reference to FIGS. 5 to 6B.

5 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

As shown in FIG. 5, the driving waveform according to the second embodiment of the present invention is a time taken to raise the voltage of the Y electrode from the -Vs voltage to the Vs voltage in the sustain period (hereinafter referred to as "rise time") ( T1) is made longer than the time taken to lower the voltage of the Y electrode from the Vs voltage to the -Vs voltage (hereinafter referred to as "fall time") (T2). In this way, the absolute value of the rising slope that increases the voltage of the Y electrode to the Vs voltage becomes smaller than the absolute value of the falling slope that decreases the voltage of the Y electrode to the -Vs voltage.

In this manner, when the absolute value of the slope of the voltage rise of the Y electrode becomes small in the sustain period, the intensity of the discharge is also reduced, thereby reducing the amount of negative ions moving to the Y electrode. When the amount of negative ions is reduced, it is possible to prevent overdischarge that may occur when the voltage Vs is applied to the Y electrode. In addition, when the absolute value of the voltage drop slope of the Y electrode becomes large in the sustain period, the discharge is also increased, thereby increasing the amount of negative ions moving to the X electrode. When the amount of negative ions is increased, it is possible to prevent low discharge that may occur when the -Vs voltage is applied to the Y electrode.

Next, the rise and fall times T1 and T2 will be described with reference to FIGS. 6A and 6B.

FIG. 6A is a diagram illustrating the presence or absence of overdischarge measured while varying T1 in the driving waveform of FIG. 5, and FIG. 6B is a diagram illustrating the presence or absence of low discharge measured while varying T2 in the driving waveform of FIG. 5.

에서

까지 각각 가변시키면서 과방전 유무를 측정한 결과, 상승 시간(T1)이

이상이 되면 과방전이 발생하지 않는다는 것을 알 수 있다. 이 때, 상승 시간(T1)이

일 때에는 과방전이 발생하지 않았지만 기울기가 너무 완만해져서 방전이 발생하지 않는 결과가 나왔다. First, looking at Figure 6a, the rise time (T1)

in

As a result of measuring overdischarge and varying each up to, the rise time T1

It turns out that overdischarge does not occur when it becomes abnormal. At this time, the rise time T1

When, overdischarge did not occur, but the slope became too slow, resulting in no discharge.

에서

까지 각각 가변시키면서 저방전 유무를 측정한 결과, 하강 시간(T2)이

이하가 되면 저방전이 발생하지 않는다는 것을 알 수 있다. 이 때, 하강 시간(T2)이

일 때에는 저방전이 발생하지 않았지만 기울기가 너무 급해져서 각 전극을 덮고 있는 유전체층에 손상이 가는 결과가 나왔다.Next, looking at Figure 6b, the fall time (T2)

in

As a result of measuring the low discharge while varying each, the fall time (T2)

It turns out that low discharge does not generate | occur | produce below. At this time, the fall time (T2)

Low discharge did not occur, but the slope was too steep, resulting in damage to the dielectric layer covering each electrode.

및

으로 설정하면 과방전 및 저방전을 방지할 수 있다.Therefore, the rise time T1 and the fall time T2 in the holding period are respectively

And

When set to, overdischarge and low discharge can be prevented.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the board for driving the sustain electrode can be removed. In other words, it is possible to implement an integrated board that is substantially driven by only one board, thereby reducing the unit cost.

In the case where the scan electrode and the sustain electrode are implemented as the respective driving boards, since the driving waveforms in the reset period and the address period are mainly supplied from the scan driving board, impedances formed in the scan driving board and the sustain driving board are different. Accordingly, the sustain discharge pulse applied to the scan electrode and the sustain discharge pulse applied to the sustain electrode in the sustain period may be different. However, according to the present invention, since the pulse for sustain discharge is supplied only from the scan driving board, the impedance is always constant.

In addition, when a high voltage is applied to the scan electrode while applying a sustain discharge pulse having a high voltage and a low voltage to only the scan electrode alternately in the sustain period, overdischarge may occur since the negative ions move only to the scan electrode. When a low voltage is applied to the negative ions, the negative ions are dispersed and moved between the sustain electrode and the address electrode, thereby causing low discharge. However, according to the present invention, overdischarge and low discharge are prevented by making the time taken to apply the low voltage when applying the sustain discharge pulse shorter than the time taken to apply the high voltage in the sustain period.

Claims (8)

In a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In a sustain period in which a second voltage and a third voltage lower than the second voltage are alternately applied to the second electrode while the voltage of the first electrode is biased to the first voltage, Alternately applying the second voltage and the third voltage to the second electrode, Increasing the voltage of the second electrode from the third voltage to the second voltage for a first time period, Applying a second voltage to the second electrode, Reducing the voltage of the second electrode from the second voltage to the third voltage for a second time different from the first time, and Applying the third voltage to the second electrode Method of driving a plasma display panel comprising a. The method of claim 1, And the first time is longer than the second time. The method of claim 2, The first time is

Is, The second time is

A method of driving a plasma display panel. The method according to any one of claims 1 to 3, And the first electrode is biased at a first voltage in a reset period and an address period. The method of claim 4, wherein And the first voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and A driving board on which the plasma display panel applies a driving waveform for displaying an image and biases the first electrode to a first voltage while the image is displayed; Including The drive board, In the sustain period, a second voltage and a third voltage lower than the second voltage are alternately applied to the second electrode, A plasma display device having a first time for changing the voltage of the second electrode from the third voltage to the second voltage is longer than a second time for changing the voltage of the second electrode from the second voltage to the third voltage. . The method of claim 6, And the first voltage is a ground voltage. The method according to claim 6 or 7, The first time is

Is, The second time is

Plasma display device.

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