KR100550991B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel. In particular, in the plasma display panel driving method, a waveform having a reset function, an address function, and a sustain discharge function is applied to the scan electrode while the sustain electrode is biased to the ground voltage. At this time, when the rising waveform is applied to the scan electrode, the address electrode is floated to float the address electrode when the rising waveform is applied to the scan electrode and the address electrode when the falling waveform is applied to the scan electrode. In this way, the board driving the sustain electrode can be removed, thereby reducing the driving board price and reducing the background luminance in the reset period.

PDP, scan electrode, sustain electrode, drive board, contrast, switch, drive circuit

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a partial perspective view of a typical AC plasma display panel.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

3 is a schematic concept of a plasma display panel according to an exemplary embodiment of the present invention.

4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

6 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

7 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

8 shows a general address IC.

FIG. 9 is a diagram illustrating an address IC according to a first embodiment of the present invention for generating an address driving waveform in the reset period shown in FIG. 7.

10 is a diagram showing the wall charge state of a cell when a strong discharge occurs in the reset period.

11 is a driving waveform diagram of a plasma display panel according to a fourth exemplary embodiment of the present invention.

FIG. 12 is a diagram illustrating an address IC according to a second embodiment of the present invention for generating an address driving waveform in the reset period shown in FIG. 11.

13 is a driving waveform diagram of a plasma display panel according to a fourth exemplary embodiment of the present invention.

The present invention relates to a method for driving a plasma display panel (PDP).

A plasma display panel is a flat display device that displays characters or images by using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC type plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component and has a long life compared to the DC type since the electrode is protected from the impact of ions during discharge.

In the AC plasma display panel, scan electrodes and sustain electrodes that are parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

1 is a partial perspective view of a typical AC plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 13 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

An object of the present invention is to provide a plasma display device having an integrated board capable of driving a scan electrode and a sustain electrode. It is another object of the present invention to provide a driving waveform suitable for an integrated board.

In order to solve this problem, the present invention grounds the sustain electrode and applies a driving waveform to the scan electrode.

According to an aspect of the present invention, a frame is formed in a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. In the driving method, the voltage of the plurality of second electrodes is gradually decreased from the second voltage to the third voltage in the at least one subfield while the plurality of first electrodes are biased to the first voltage in the reset period. In the address period, applying the ninth voltage to a third electrode of a discharge cell to be turned on through a plurality of first transistors connected between the plurality of third electrodes and a first power supply for supplying a ninth voltage, Applying the sixth voltage to a third electrode of a discharge cell that is not to be turned on through a plurality of second transistors connected between the plurality of third electrodes and a second power supply that supplies a sixth voltage lower than the ninth voltage. And sustain-discharging the discharge cells to be turned on in a state in which the plurality of first electrodes are biased to the first voltage in the sustain period. In a state in which a first switch connected between the second power supply and the plurality of second transistors is turned off in a first period during which the voltage of the pole is at least part of a period of decreasing from the second voltage to the third voltage; The plurality of third electrodes are floated.

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And the driving method further includes gradually increasing a voltage of the second electrode from a seventh voltage to an eighth voltage while biasing the first electrode to a first voltage in the reset period. A state in which a second switch connected between the first power supply and the plurality of first transistors is turned off in a second period during which the voltage of the second electrode is at least part of a period in which the voltage of the second electrode increases from the seventh voltage to the eighth voltage. The third electrodes are floated at. In this case, in the address period, the first electrode may be biased with the first voltage, and the first voltage may be a ground voltage.

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According to another aspect of the present invention, a plasma display device is provided. The apparatus includes a plasma display panel including a plurality of first electrodes and a plurality of second electrodes, and a plurality of third electrodes crossing the first and second electrodes, the plurality of third electrodes and the first voltage. A plurality of first transistors connected between the first power supplies to supply and a plurality of second transistors connected between the second power supplies to supply a second voltage lower than the first voltage, wherein the plurality of second transistors are connected in the address period. A plurality of selection circuits applying the first voltage to a third electrode of a discharge cell to be turned on through a first transistor of and applying the second voltage to a third electrode of a discharge cell not to be turned on through the plurality of second transistors, In the reset period, the voltages of the plurality of first electrodes are gradually reduced from a fourth voltage to a fifth voltage to the plurality of first electrodes while the voltages of the plurality of first electrodes are maintained at a third voltage. A driving circuit for floating the plurality of third electrodes during at least some of the periods during which the voltage of the second electrode decreases to the fifth voltage, and the plurality of second transistors connected between the plurality of second transistors and the second power source; And a first switch that is turned off while the three electrodes are floating.

The driving circuit may further include a second switch connected between the plurality of first transistors and the first power source. And the driving circuit is at least a part of gradually increasing the voltages of the plurality of second electrodes from the sixth voltage to the seventh voltage in the reset period, and increasing the voltages of the plurality of second electrodes to the seventh voltage. The plurality of third electrodes are floated while the second switch is turned on for a period of time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 3 is a schematic concept of a plasma display panel according to an exemplary embodiment of the present invention. 4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 2, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40.

The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10.

The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

3, the plasma display panel 10 includes a plurality of address electrodes A1-Am extending in the vertical direction, a plurality of scan electrodes Y1-Yn and a plurality of sustain electrodes X1 extending in the horizontal direction. -Xn).

The sustain electrodes X1-Xn are formed corresponding to the scan electrodes Y1-Yn, and generally have one end connected in common with each other.

The plasma display panel 10 includes an insulating substrate on which sustain and scan electrodes X 1 -X n and Y 1 -Y n are arranged, and an insulating substrate on which address electrodes A 1 -A m are arranged.

The two insulating substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1-Yn and the address electrodes A1-Am and the sustain electrodes X1-Xn and the address electrodes A1-Am are orthogonal to each other. . At this time, the discharge space at the intersection of the address electrodes A1-Am and the sustain and scan electrodes X1-Xn and Y1-Yn forms the discharge cells 12.

As shown in FIG. 4, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20.

The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 4, a plasma display apparatus for dual driving is described as an example. However, in the case of a single driving, the address buffer board 100 is disposed at one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage to each address electrode A1-Am to select a discharge cell to be displayed.

The scan drive board 200 is disposed on the left side of the chassis base 20, and the scan drive board 200 is electrically connected to the scan electrodes Y1-Yn through the scan buffer board 300 and is processed. The driving signal is received from the control board 400 and a driving voltage is applied to the scan electrodes Y1-Yn. The sustain electrodes X1-Xn are biased at a constant voltage.

The scan buffer board 300 applies a voltage to the scan electrodes Y1-Yn to sequentially select the scan electrodes Y1-Yn in the address period.

In FIG. 4, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1-Am and a control signal for driving the scan electrodes Y1-Yn, respectively. ) And the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display panel according to the first exemplary embodiment of the present invention will be described with reference to FIG. 5.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 5, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. Since the X electrode is biased at the reference voltage (0 V in FIG. 5), the description of the voltage applied to the X electrode is omitted.

Referring to FIG. 5, one subfield is divided into a reset period (P _r), an address period (P _a), and a sustain period, comprising the (P _s) the reset period (P _r) is the rising period (P _r1) and the falling period (P _r2 ).

The rising period P _r1 of the reset period P _r is a period in which wall charges are formed on the Y electrode, the X electrode and the A electrode, and the falling period P _r2 is a part of the wall charges formed in the rising period P _r1 . This is a period for erasing to facilitate address discharge. An address period (P _a) is a period for selecting a discharge cell to cause sustain discharge in the sustain period (P _s) from a plurality of discharge cells. Sustain period (P _s) is a period during which sustain discharge for a discharge cell selected in the address period (P _a).

The plasma display panel is connected to a scan / hold driving circuit for applying a driving voltage to the Y electrode and the X electrode in each period P _r , P _a , and P _s , and an address driving circuit for applying the driving voltage to the A electrode. It forms one display device.

In the rising period (P _r1) of the reset period (P _r) and the lamp voltage gradually rising toward voltage Vset from the voltage V _s while maintaining the A electrode and X electrode at the reference voltage is applied to the Y electrode. In FIG. 5, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 5, a weak discharge occurs in the cell, and wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally the same voltage as that applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period P _r2 , Vnf at the voltage Vs while maintaining the A electrode at the reference voltage. A ramp voltage that slowly drops to the voltage is applied to the Y electrode. Then, while the voltage of the Y electrode decreases, a weak discharge occurs between the Y electrode and the X electrode, and between the Y electrode and the A electrode, and the negative wall charges formed on the Y electrode and the positive wall charges formed on the X electrode and the A electrode. Is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, a scan pulse of the VscL voltage is applied to the Y electrode (Y1 in FIG. 3) of the first row, and an address pulse of Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode (Y2 in FIG. 3) of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be explained. When the Vnf voltage is applied in the reset period, the wall voltage between the A and Y electrodes is applied. The sum of the external voltage Vnf between the A electrode and the Y electrode is determined by the discharge start voltage Vfay between the A electrode and the Y electrode. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, the address period (P _a) in the cell where the address discharge is generated in a pulse having the Vs voltage first to the Y electrodes been formed in the high voltage Y wall voltage (Vwxy) of the electrodes, in the sustain period of the X electrode and Y A sustain discharge is caused between the electrode and the X electrode. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is higher than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of applying the sustain discharge pulse having the Vs voltage and the -Vs voltage alternately to the Y electrode is repeated the number of times corresponding to the weight indicated by the corresponding subfield.

As described above, in the first exemplary embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

However, when the falling period P _r2 of the reset period P _r in the first embodiment of the present invention, the voltage difference between the Y electrode and the X electrode in the state where the X electrode is biased to the ground voltage is compared with the conventional driving waveform. Although there is no difference, the voltage difference between the A electrode and the Y electrode is significantly larger than that of the conventional driving waveform. In this manner, when the voltage difference between the A electrode and the Y electrode becomes large, a large amount of discharge unnecessarily occurs in the falling period P _r2 of the reset period P _r . As described above, when a large amount of discharge occurs in the reset period P _r , the reset light is counted to increase the background luminance. As a result, the contrast of the plasma display panel is reduced. In particular, the driving waveform of FIG. 5 has a low contrast ratio because a large amount of weak discharge occurs in the reset period when displaying 0 gray scale (black gray scale). Therefore, below, a method of reducing the background brightness by reducing the voltage difference between the Y electrode and the A electrode will be described in detail with reference to FIG. 6.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

As shown in FIG. 6, it is the same as the first embodiment of the present invention except that the A electrode is biased to the Vn voltage in the falling period P _r2 of the reset period P _r .

Specifically, in the falling period P _r2 of the reset period P _r , the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the A electrode is biased to the Vn voltage (a voltage lower than the reference voltage). When the voltage of the Y electrode is reduced while the voltage of the A electrode is biased to the Vn voltage, the discharge between the A electrode and the Y electrode can be reduced because the voltage difference between the A electrode and the Y electrode is smaller than in the first embodiment.

The period of biasing the voltage of the A electrode to the Vn voltage may be a part of the falling period or the whole of the falling period.

However, when the Vn voltage is used, an additional power source for supplying the Vn voltage to the A electrode must be used, thereby increasing the circuit price. Hereinafter, a method of reducing the voltage difference between the A electrode and the Y electrode without using an additional power source will be described in detail with reference to FIGS. 7 and 8.

7 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention. As shown in FIG. 7, the driving waveform according to the third embodiment of the present invention is different from the first embodiment of the present invention except that the A electrode is floated in the falling period P _r2 of the reset period P _r . same.

That is, in the falling period P _r2 of the reset period P _r , the voltage of the Y electrode gradually decreases from the voltage Vs to the voltage Vnf while the A electrode is floating. Since the capacitance component is formed by the A electrode and the Y electrode, when the A electrode is floated when the voltage of the Y electrode decreases, the voltage of the A electrode also decreases along with the voltage of the Y electrode. Therefore, since the voltage difference between the A electrode and the Y electrode is smaller than in the first embodiment, the discharge between the A electrode and the Y electrode can be reduced. And the floating period of the A electrode may be an entire portion or a falling period (P _r2) of the falling period (P _r2).

However, since the general address IC is configured as shown in FIG. 8, the voltage of the A electrode is clamped to the ground voltage when the A electrode is floating, and thus cannot be reduced to a lower voltage.

8 shows a general address IC.

As shown in Fig. 8, a general address IC includes a plurality of address selection circuits. Specifically, the address selection circuit is connected to the plurality of A electrodes, respectively, and includes two transistors A _H and A _L , respectively. The transistors A _H and A _L are field effect transistors having a body diode. A capacitance component (hereinafter referred to as panel capacitor Cp) is formed by the A electrode and the Y electrode. That is, one end of the panel capacitor Cp is connected to the address IC, and the other end of the panel capacitor Cp is connected to the scan electrode driver for applying a driving voltage to the Y electrode.

The transistor A _H is connected between the power supply Va supplying the address voltage Va and the A electrode. When the transistor A _H is turned on, the transistor A _H supplies a Va voltage to the A electrode. The transistor A _L is connected between the power supply 0V supplying the ground voltage and the A electrode, and when the transistor A _L is turned on, the transistor A _L supplies the ground voltage to the A electrode. That is, in the address period P _a , the transistor A _H is turned on to select the A electrode to which the address voltage Va is applied, and the switching element A _L is turned on to select the A electrode to which the ground voltage is applied. Do not.

However, since the general address IC shown in FIG. 8 has a body diode, when the voltage of the Y electrode is reduced to the Vnf voltage in the falling period P _r2 of the reset period P _r as shown in FIG. When the voltage of the electrode decreases along the voltage of the Y electrode and the voltage of the A electrode is lower than the ground voltage, the voltage of the A electrode is clamped to the ground voltage through the body diode of the switching element A _H of the address selection circuit. Therefore, the voltage of the A electrode cannot be reduced below the ground voltage. In this case, since the driving waveform of FIG. 6 is the same, the effect of the driving waveform of FIG. 7 does not appear. An embodiment for solving this problem will be described in detail with reference to FIG. 9.

FIG. 9 is a diagram illustrating an address IC according to a first embodiment of the present invention for generating an address driving waveform in the reset period shown in FIG. 7.

As shown in FIG. 9, the switch IC is the same as the address IC of FIG. 8 except that the switch SW1 is connected between the power supply 0V and the transistor A _L.

Specifically, the address IC according to the first embodiment of the present invention includes a plurality of address selection circuits, and the switching element SW1 is electrically connected between the address IC and the power supply 0V. The switching element SW1 is turned off when the A electrode is floating in the reset period P _r to cut off the A electrode from the power supply 0V so that the voltage of the A electrode is reduced along with the voltage of the Y electrode. As such, when the voltage of the Y electrode decreases, the voltage of the A electrode also decreases to a negative voltage, thereby reducing the voltage difference between the Y electrode and the A electrode, thereby reducing the discharge between the Y electrode and the A electrode.

In the third embodiment of the present invention, the A electrode is floated in order to lower the potential of the A electrode only in the falling period P _r2 of the reset period P _r , but the same may be applied to the rising period P _r1 .

Referring to FIG. 7, in the falling period P _r2 of the reset period P _r , the final voltage applied to the Y electrode is set to the Vnf voltage, and as described above, the final voltage Vnf is defined between the Y electrode and the X electrode. The voltage near the discharge start voltage. In general, since the discharge start voltage Vfay between the Y electrode and the A electrode is lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, the potential of the Y electrode due to the wall charge at the final voltage Vnf in the falling period. Is higher than the A electrode, the wall voltage of the Y electrode with respect to the A electrode can be set to a positive voltage. Since the sustain discharge does not occur in the cell which does not have address discharge, the reset period of the next subfield is performed while maintaining the wall charge state. In the cell in this state, the wall voltage of the Y electrode for the A electrode is higher than the wall voltage of the Y electrode for the X electrode, so that the voltage of the Y electrode increases in the rising period P _r1 of the reset period P _r . After a period of time after the voltage between the A electrode and the Y electrode exceeds the discharge start voltage Vfay, the voltage between the X electrode and the Y electrode exceeds the discharge start voltage Vfay.

프로세스라 한다. 일반적으로 플라즈마 표시 패널에서 A 전극은 색상 표현을 위해 형광체로 덮여 있는 반면, X 전극과 Y 전극은 유지방전의 효율을 위해 2차 전자 방출 계수가 높은 MgO 성분의 보호막으로 덮여 있다. 그런데 상승 기간에서 A 전극과 Y 전극 사이의 전압이 방전 개시 전압(Vfay)을 넘어도 형광체로 덮여 있는 A 전극이 음극으로 작용하기 때문에, A 전극과 Y 전극 사이에서 방전이 지연된다. 방전 지연에 의해 A 전극과 Y 전극 사이에서 실제 방전이 일어나는 시점에서는 A 전극과 Y 전극 사이의 전압이 방전 개시 전압(Vfay)보다 더 높은 전압이 된다. 따라서 이러한 높은 전압에 의해 A 전극과 Y 전극 사이에서 약 방전이 아닌 강 방전이 발생할 수 있다. 이러한 강 방전에 의해 X 전극과 Y 전극 사이에서도 강 방전이 일어나서 정상적인 상승 기간(P_r1)에서 생성되는 벽 전하보다 많은 양의 벽 전하가 셀에 형성되고 또한 많은 양의 프라이밍 입자가 생성될 수 있다.In the rising period P _r1 of the reset period P _r , since a high voltage is applied to the Y electrode, the Y electrode serves as the anode and the A electrode and the X electrode serve as the cathode. The discharge in the cell is determined by the amount of secondary electrons emitted from the cathode when the cation strikes the cathode.

It is called a process. In general, in the plasma display panel, the A electrode is covered with a phosphor for color expression, while the X electrode and the Y electrode are covered with a MgO component having a high secondary electron emission coefficient for the sustain discharge efficiency. However, in the rising period, even if the voltage between the A electrode and the Y electrode exceeds the discharge start voltage Vfay, since the A electrode covered with the phosphor acts as a cathode, the discharge is delayed between the A electrode and the Y electrode. When the actual discharge occurs between the A electrode and the Y electrode due to the discharge delay, the voltage between the A electrode and the Y electrode becomes higher than the discharge start voltage Vfay. Therefore, such a high voltage may cause a strong discharge rather than a weak discharge between the A electrode and the Y electrode. This strong discharge may cause a strong discharge between the X electrode and the Y electrode, so that a larger amount of wall charge is formed in the cell than a wall charge generated in the normal rising period P _r1 , and a large amount of priming particles may be generated. .

In general, for a stable erase operation in the falling period (P _r2 ) it is necessary to form a certain amount of wall charge in the rising period (P _r1 ). By the way, when forming a large amount of wall charges in the rise period (P _r1) as before, you have to erase a lot of wall charges on the falling period (P _r2), so the longer the falling period (P _r2). However, the reset period (P _r1) is determined because the falling period (P _r2) at the failure to erase the predetermined amount of wall charge, the falling period (P _r2) a strong discharge by the large amount of wall charges and priming particles can occur at Accordingly, as shown in FIG. 10, the wall charge may not be sufficiently erased between the X electrode and the Y electrode. In the cell in this state, a high wall voltage is formed between the X electrode and the Y electrode even after the end of the reset period, and even if an address discharge does not occur due to this wall voltage, erroneous discharge may occur between the X electrode and the Y electrode in the sustain period. An embodiment capable of preventing such a discharging will be described in detail with reference to FIG. 11.

11 is a driving waveform diagram of a plasma display panel according to a fourth exemplary embodiment of the present invention. As shown in FIG. 11, the driving waveform according to the fourth embodiment of the present invention is different from the third embodiment of the present invention except that the A electrode is floated in the rising period P _r1 of the reset period P _r . same. And the floating period of the A electrode may be an entire portion or rising period (P _r1) of the rise period (P _r1).

Specifically, in the rising period P _r1 of the reset period P _r , the voltage of the Y electrode is gradually raised from the voltage Vs to the voltage Vset while the A electrode is floating. Then, the voltage of the A electrode is increased along with the voltage of the Y electrode so that the voltage between the A and Y electrodes is smaller than in the third embodiment so that the voltage between the X and Y electrodes is the voltage between the A and Y electrodes. First, the discharge start voltage is exceeded. Then, a weak discharge occurs first between the X electrode and the Y electrode, and the voltage between the A electrode and the Y electrode exceeds the discharge start voltage while the priming particles are formed by the weak discharge. The priming particles reduce the discharge delay between the A electrode and the Y electrode, so that the weak discharge is performed without generating the strong discharge as described above, thereby forming a desired amount of wall charge. Therefore, strong discharge does not occur even during the falling period P _r2 of the reset period P _r , which can prevent erroneous discharge in the sustain period.

In FIG. 11, while the A electrode is floated during the rising period P _r1 , the A electrode may be biased to a constant voltage. At this time, if the voltage of the A electrode is biased to the Va voltage, there is no need to use an additional power supply. As described above, when the A electrode is biased to the Va voltage, the voltage between the A electrode and the Y electrode is lower than when the A electrode voltage is biased to the reference voltage, so that weak discharge may occur first between the X electrode and the Y electrode. Therefore, the same effect as in FIG. 11 can be obtained. And the period during which the bias voltage of the A electrode at a constant voltage may be an entire portion or rising period (P _r1) of the rise period (P _r1).

However, when the general address IC shown in FIG. 8 is used to float the A electrode in the rising period P _r1 of the reset period P _r , the voltage of the A electrode is clamped to the Va voltage, and the voltage of the A electrode is equal to or greater than the Va voltage. Cannot increase. Therefore, in order to supply a voltage higher than Va to the A electrode, the power supply Va and the A electrode should be cut off. This embodiment will be described in detail with reference to FIG. 12.

FIG. 12 is a diagram illustrating an address IC according to a second embodiment of the present invention for generating an address driving waveform in the reset period shown in FIG. 11.

As shown in FIG. 11, it is the same as the address IC of FIG. 9 except that the switch SW2 is connected between the power supply Va and the address IC.

Specifically, the address IC according to the second embodiment of the present invention includes a plurality of address selection circuits, and the address selection circuit includes two transistors A _H and A _L. The switching elements SW1 and SW2 are electrically connected between the address IC and the power supplies Va and 0V, respectively. The switching element SW2 is electrically connected between the power supply Va and the address IC, and the switching element SW1 is electrically connected between the power supply 0V and the address IC as described above.

When the A electrode floats in the reset period, when the voltage of the Y electrode is increased to the Vset voltage by turning off the switching elements SW1 and SW2, the voltage of the A electrode is increased to a positive voltage and the voltage of the Y electrode is reduced to the Vnf voltage. When the voltage on the A electrode is reduced to a negative voltage. At this time, since the switching elements SW1 and SW2 are turned off and the A electrode is cut off from the power supply (0 V, Va), when the voltage Vs is applied to the Y electrode, a voltage higher than the voltage Va may be applied and the -Vs is applied to the Y electrode. When voltage is applied, a voltage lower than 0V may be applied.

As described above, according to the exemplary embodiment of the present invention, the driving waveform is applied only to the Y electrode while the X electrode is biased to a predetermined voltage, thereby performing the reset operation, the address operation, and the sustain discharge operation. You can remove the board. In addition, since the pulse for sustain discharge is supplied only from the scan driving board 300, the impedance in the path to which the sustain discharge pulse is applied may be constant.

The reset period of the plurality of subfields forming one frame may be formed in the rising period P _r1 and the falling period P _r2 , but the reset period of some subfields may be formed only in the falling period P _r2 . Hereinafter, such an embodiment will be described in detail with reference to FIG. 13.

13 is a driving waveform diagram of a plasma display panel according to a fourth exemplary embodiment of the present invention. In FIG. 13, two subfields are shown for convenience, and the two subfields are shown as first and second subfields, respectively. The second subfield only shows the reset period.

Referring to FIG. 13, the reset period P _r of the first subfield among the plurality of subfields forming one frame includes the rising period P _r1 and Y for gradually increasing the voltage of the Y electrode from the voltage Vs to the voltage Vset. It is formed with a falling period (P _r2 ) that gradually lowers the voltage of the electrode from the voltage Vs to the voltage Vnf, and the reset period P _r of the second subfield gradually changes the voltage of the Y electrode from the voltage Vs to the voltage Vnf. It is formed only in the fall period P _r2 which makes it descend. That is, the first is the falling waveform, after the rising waveform applied to the reset period (P _r) of the sub-field is applied and the second is applied in only the reset falling waveform period (P _r) of the sub-field. At this time, when sustain discharge occurs in the sustain period of the first subfield, since negative (−) wall charges are formed on the Y electrode and positive (+) wall charges are formed on the X electrode and the A electrode, the voltage of the Y electrode gradually decreases. When the discharge start voltage is exceeded together with the wall voltage formed in the cell, weak discharge occurs as in the falling period of the reset period of the first subfield. Since the final voltage Vnf of the Y electrode is the same as the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield ends in the falling period of the first subfield. It becomes substantially the same as the later wall charge state.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, discharge does not occur when the voltage of the Y electrode decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge. Therefore, if the first subfield is formed like the first subfield in one field and the other subfield is formed like the second subfield, when the zero gray scale (black gray scale) is displayed, the reset discharge (weak discharge) only in the reset period of the first subfield. This will happen. That is, since no discharge occurs in other subfields when displaying the black gradation, the contrast ratio can be increased.

As described above, when the discharge start voltage is exceeded along with the wall voltage formed in the cell while the voltage of the Y electrode is gradually decreasing, a weak discharge occurs, and since the discharge start voltage is not exceeded at the beginning of the reset period P _r2 , It is also possible to lower the voltage of the electrode immediately and then gradually lower it to the Vnf voltage. In this way, there is an effect that the reset period P _r of the first and second subfields can be shortened.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the board for driving the sustain electrode can be removed. In other words, it is possible to implement an integrated board that is substantially driven by only one board, thereby reducing the unit cost.

In the case where the scan electrode and the sustain electrode are implemented as the respective driving boards, since the driving waveforms in the reset period and the address period are mainly supplied from the scan driving board, impedances formed in the scan driving board and the sustain driving board are different. Accordingly, the sustain discharge pulse applied to the scan electrode and the sustain discharge pulse applied to the sustain electrode in the sustain period may be different. However, according to the present invention, since the pulse for sustain discharge is supplied only from the scan driving board, the impedance is always constant.

In addition, in the reset period, the potential difference between the scan electrode and the sustain electrode is reduced, thereby reducing the background luminance, thereby improving the contrast.

Claims (14)

In a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In at least one subfield, Gradually decreasing a voltage of the plurality of second electrodes from a second voltage to a third voltage while biasing the plurality of first electrodes to a first voltage in a reset period, The ninth voltage is applied to a third electrode of a discharge cell to be turned on through a plurality of first transistors connected between the plurality of third electrodes and a first power supply for supplying a ninth voltage in an address period. Applying the sixth voltage to a third electrode of a discharge cell that will not be turned on through a plurality of second transistors connected between a third electrode and a second power supply for supplying a sixth voltage lower than the ninth voltage, and Sustain-discharging the discharge cells to be turned on while biasing the plurality of first electrodes to the first voltage in a sustain period, A first switch connected between the second power supply and the plurality of second transistors in a first period that is at least part of a period in which voltages of the plurality of second electrodes decrease from the second voltage to the third voltage; And driving the plurality of third electrodes in a turned off state. delete delete delete The method of claim 1, Gradually increasing the voltage of the second electrode from the seventh voltage to the eighth voltage while biasing the first electrode to the first voltage in the reset period; More,  Turn off a second switch connected between the first power supply and the plurality of first transistors in a second period during which the voltage of the second electrode is at least part of a period in which the voltage of the second electrode increases from the seventh voltage to the eighth voltage. A method of driving a plasma display panel which floats the plurality of third electrodes in one state. delete delete The method according to claim 1 or 5, And the first electrode is biased to the first voltage in the address period. The method of claim 8, And the first voltage is a ground voltage. A plasma display panel including a plurality of first electrodes and a plurality of second electrodes and a plurality of third electrodes crossing the first and second electrodes, A plurality of first transistors connected between the plurality of third electrodes and a first power supply for supplying a first voltage, and a plurality of first transistors connected between a second power supply for supplying a second voltage lower than the first voltage; And a second transistor, wherein the first voltage is applied to a third electrode of the discharge cell to be turned on through the plurality of first transistors in an address period, and the third electrode of the discharge cell is not turned on through the plurality of second transistors. A plurality of selection circuits for applying a second voltage, The voltage of the plurality of first electrodes is gradually decreased from a fourth voltage to a fifth voltage of the plurality of first electrodes while the voltages of the plurality of first electrodes are maintained at a third voltage in a reset period. A driving circuit for floating the plurality of third electrodes for at least some of the periods of decreasing to a fifth voltage, and And a first switch connected between the plurality of second transistors and the second power source and turned off while the plurality of third electrodes are floating. delete The method of claim 10, A second switch connected between the plurality of first transistors and the first power source More, The drive circuit, Gradually increasing the voltages of the plurality of second electrodes from the sixth voltage to the seventh voltage in the reset period, And the third electrodes are floated while the second switch is turned on for at least a portion of the voltages of the plurality of second electrodes increased to the seventh voltage. delete The method of claim 10 or 12, And the second electrode is biased to the third voltage in an address period and a sustain period.

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