KR100521496B1 - Plasma display device and driving method of plasma display panel - Google Patents

Abstract

In the plasma display panel, a driving waveform is applied to the scan electrode while the sustain electrode is biased to the ground voltage to perform a reset operation, an address operation, and a sustain discharge operation. Then, the driving board driving the sustain electrode can be removed. In the driving circuit for generating sustain discharge pulses having alternating high and low voltages to the scan electrodes, two inductors are connected in series and each of the two inductors contacts and supplies the low and high voltages of the sustain discharge pulses. Connect a diode to at least one of the power sources. This can reduce the freewheeling current flowing through the circuit elements due to the characteristics of the inductor.

Description

Plasma display device and plasma display panel driving method {PLASMA DISPLAY DEVICE AND DRIVING METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel and a plasma display device.

A plasma display panel is a display panel that displays characters or images by using plasma generated by gas discharge, and tens to millions or more pixels (discharge cells) are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of a plasma display panel. As shown in FIG. 1, the plasma display panel includes two insulating substrates 1 and 2 facing each other apart from each other. A plurality of scan electrodes 3a and sustain electrodes 3b are formed in pairs and in parallel on the insulating substrate 1, and the scan electrodes 3a and the sustain electrodes 3b are formed of the dielectric layer 4 and the protective film 5. Covered with. A plurality of address electrodes 6 are formed on the glass substrate 2, and the address electrodes 6 are covered with the insulating layer 7. The partition 8 is formed on the insulating layer 7 between the two address electrodes 6. In addition, the phosphor 9 is formed on the surface of the insulating layer 7 and on both sides of the partition 8. The insulating substrates 1 and 2 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 3a, the address electrode 6, the sustain electrode 3b, and the address electrode 6 are orthogonal to each other. The discharge space at the intersection of the address electrode 6 and the pair of scan electrode 3a and sustain electrode 3b forms a discharge cell (hereinafter referred to as a "cell") 12.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

Among such integrated boards, there is a technique of applying a sustain discharge pulse having an alternating voltage of Vs and -Vs only to the scan electrodes in the sustain period, and biasing the sustain electrodes to the ground voltage. In order to apply the sustain discharge pulse, the voltage of the scan electrode is changed from -Vs voltage to Vs voltage by using resonance with the inductor, and then the scan electrode voltage is maintained at Vs voltage. In this case, a large resonance current flows in comparison with the sustain discharge pulse which is changed from the ground voltage to the Vs voltage, and this resonance current is freewheeled while the scan electrode is maintained at the Vs voltage. However, since the resonant current is large, the freewheeling current is also large, which causes a large stress on the switch connected to the Vs power supply.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device capable of reducing stress of circuit elements caused by freewheeling current.

The present invention also provides a plasma display device having an integrated board capable of driving a scan electrode and a sustain electrode. Another object of the present invention is to provide a driving waveform and a driving circuit suitable for an integrated board.

In order to solve this problem, the present invention applies a drive waveform to the scan electrode while the sustain electrode is biased at a constant voltage.

According to an aspect of the present invention, a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and a sustain period The plasma display device includes a driving circuit configured to alternately apply a positive second voltage and a negative third voltage to the second electrode while biasing the voltage of the first electrode to the first voltage. The driving circuit includes a first inductor, a second inductor having a first end electrically connected to the first inductor, and a second inductor electrically connected to the second electrode, and a first power supply for supplying the second voltage; A first switching element electrically connected between the second electrode, a second power supply supplying the third voltage, and a second switching element electrically connected between the second electrode, and a third power supply supplying a fourth voltage And a third switching element electrically connected between the second end of the inductor, a fourth switching element electrically connected between the third power source and the second end of the inductor, and a contact point of the first and second inductors. And at least one diode electrically connected to at least one of between the first power source or between the contacts of the first and second inductors and the second power source. In this case, the at least one diode includes a first diode having an anode connected to the contacts of the first and second inductors and a cathode connected to the first power source, and a cathode connected to the contacts of the first and second inductors. And a second diode connected with an anode connected to the second power source.

In the driving circuit, the first electrode may be biased to the first voltage in the reset period and the address period, and the first voltage may be a ground voltage, and the fourth voltage may also be a ground voltage.

According to another aspect of the present invention, a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, A method of alternately applying a positive second voltage and a negative third voltage to the second electrode while biasing the first electrode to the first voltage during the sustain period is provided. The method includes increasing a voltage of the second electrode through first and second inductors connected in series with the second electrode, applying the second voltage to the second electrode, the first and second Reducing the voltage of the second electrode through a second inductor, and applying the third voltage to the second electrode, wherein the second voltage is applied to the second electrode and the second In at least one of the cases where the third voltage is applied to an electrode, current flows through a diode connected to the contacts of the first and second inductors.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 3 is a schematic conceptual view of a plasma display panel according to an exemplary embodiment of the present invention. 4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 2, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 3, the plasma display panel 10 includes a plurality of address electrodes A1 to Am extending in the vertical direction, a plurality of scan electrodes Y1 to Yn extending in the horizontal direction, and a plurality of sustain electrodes X1 to Xn). The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 10 includes an insulating substrate on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and an insulating substrate on which address electrodes A1 to Am are arranged. The two insulating substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. . At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a cell (12 in FIG. 1).

As shown in FIG. 4, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 4, a plasma display apparatus for dual driving is described as an example. However, in the case of a single driving, the address buffer board 100 is disposed at one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage for selecting a discharge cell to be displayed to each address electrode A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, the scan drive board 200 is electrically connected to the scan electrodes Y1 to Yn via the scan buffer board 300, and the sustain electrode. (X1 to Xn) are biased at a constant voltage. The scan buffer board 300 applies a voltage for sequentially selecting the scan electrodes Y1 to Yn in the address period to the scan electrodes Y1 to Yn. The scan driving board 200 receives a driving signal from the image processing and control board 400 and applies a driving voltage to the scan electrodes Y1 to Yn. In FIG. 4, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. Each is applied to the address driving board 100 and the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display panel according to the first embodiment of the present invention will be described with reference to FIG. 5.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 5, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (the ground voltage in FIG. 5), the description of the voltage applied to the X electrode is omitted.

5, one subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period of the reset period, the voltage of the Y electrode is gradually increased from the Vs voltage to the Vset voltage while the A electrode is maintained at the reference voltage (0 V in FIG. 5). In FIG. 5, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 5, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally a voltage higher than the voltage applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the A electrode is maintained at the reference voltage. Then, a slight discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, so that the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode The charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, a scan pulse of the VscL voltage is applied to the scan electrodes of the first row (Y1 in FIG. 3) and an address pulse of the Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode (Y2 in FIG. 3) of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be described. When the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A and Y electrodes and the external voltage Vnf between the A and Y electrodes is determined by the discharge start voltage Vfay between the A and Y electrodes. do. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, in the cell where the address discharge occurred in the address period, the wall voltage Vwxy of the Y electrode with respect to the X electrode was formed with a high voltage. In the sustain period, the Y electrode and the X electrode were first applied with a pulse having a Vs voltage to the Y electrode. It causes maintenance discharge between them. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is lower than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X are repeated the number of times corresponding to the weight indicated by the corresponding subfield. .

As described above, in the first embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

Referring to FIG. 5, in the first embodiment of the present invention, the final voltage applied to the Y electrode in the falling period of the reset period is set to the Vnf voltage, and as described above, the final voltage Vnf is determined between the Y electrode and the X electrode. The voltage near the discharge start voltage. In general, since the discharge start voltage Vfay between the Y electrode and the A electrode is lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, the potential of the Y electrode due to the wall charge at the final voltage Vnf in the falling period. Is higher than the A electrode, the wall voltage of the Y electrode with respect to the A electrode can be set to a positive voltage. Since the sustain discharge does not occur in the cell which does not have address discharge, the reset period of the next subfield is performed while maintaining the wall charge state. In the cell in this state, the wall voltage of the Y electrode for the A electrode is higher than the wall voltage of the Y electrode for the X electrode, so that the voltage between the A electrode and the Y electrode increases when the voltage of the Y electrode increases in the rising period of the reset period. After a certain period of time passes after the discharge start voltage Vfay is exceeded, the voltage between the X electrode and the Y electrode exceeds the discharge start voltage Vfay.

In the rising period of the reset period, since a high voltage is applied to the Y electrode, the Y electrode serves as an anode, and the A and X electrodes serve as a cathode. The discharge in the cell is determined by the amount of secondary electrons emitted from the cathode when the cation strikes the cathode, which is called the γ process. In general, in the plasma display panel, the A electrode is covered with a phosphor for color expression, while the X electrode and the Y electrode are covered with a material having a high secondary electron emission coefficient such as an MgO film for the efficiency of sustain discharge. However, in the rising period, even if the voltage between the A electrode and the Y electrode exceeds the discharge start voltage Vfay, since the A electrode covered with the phosphor acts as a cathode, the discharge is delayed between the A electrode and the Y electrode. When the actual discharge occurs between the A electrode and the Y electrode due to the discharge delay, the voltage between the A electrode and the Y electrode is higher than the discharge start voltage Vfay. Therefore, such a high voltage may cause a strong discharge rather than a weak discharge between the A electrode and the Y electrode. Such strong discharges also cause strong discharges between the X electrodes and the Y electrodes, so that a larger amount of wall charges are formed in the cell than the wall charges generated in the normal rising period, and a large amount of priming particles can be produced.

Then, a strong discharge may occur due to a large amount of wall charges and priming particles in the falling period, and thus, wall charges may not be sufficiently erased between the X electrode and the Y electrode as shown in FIG. 6. In the cell in this state, a high wall voltage is formed between the X electrode and the Y electrode even after the end of the reset period, and even if an address discharge does not occur due to this wall voltage, erroneous discharge may occur between the X electrode and the Y electrode in the sustain period. An embodiment capable of preventing such a discharging will be described in detail with reference to FIG. 7.

7 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

As shown in FIG. 7, the driving waveform according to the second embodiment of the present invention is the same as the first embodiment except for biasing the A electrode to a constant voltage in the rising period of the reset period.

Specifically, in the rising period of the reset period, the voltage of the Y electrode is gradually increased from the Vs voltage to the Vset voltage while the A electrode is biased to a constant voltage (voltage higher than the reference voltage). In this case, when the Va voltage is used as the bias voltage of the A electrode as illustrated in FIG. 7, an additional power source may not be used. When the voltage of the Y electrode is increased while the voltage of the A electrode is biased to the Va voltage, the voltage between the A electrode and the Y electrode is smaller than in the first embodiment, so that the voltage between the X electrode and the Y electrode is equal to the A electrode and the Y electrode. The discharge start voltage is exceeded before the voltage between the electrodes. Then, a weak discharge occurs first between the X electrode and the Y electrode, and the voltage between the A electrode and the Y electrode exceeds the discharge start voltage while the priming particles are formed by the weak discharge. The priming particles reduce the discharge delay between the A electrode and the Y electrode, so that the weak discharge is performed without generating the strong discharge as described above, thereby forming a desired amount of wall charge. Therefore, weak discharge does not occur even in the falling period of the reset period, and thus, the false discharge in the sustain period can be prevented.

In FIG. 7, the A electrode is biased at a constant voltage during the rising period. Alternatively, the A electrode may be biased at the constant voltage only at the beginning of the rising period. As described above, in order to prevent the strong discharge from occurring in the rising period, it is necessary to prevent the voltage between the A and Y electrodes from exceeding the discharge start voltage before the voltage between the X and Y electrodes. It can also be biased at a constant voltage. That is, after weak discharge occurs between the A electrode and the Y electrode, the voltage of the A electrode can be set back to the reference voltage.

In the rising period, the voltage of the A electrode may be gradually increased. If the voltage of the A electrode increases as the voltage of the Y electrode increases in the rising period, the voltage between the A electrode and the Y electrode is lower than when the A electrode voltage is biased to the reference voltage. Weak discharge may occur first. The period for increasing the voltage of the A electrode may be part of the rising period or the whole of the rising period. It is also possible to float the A electrode without increasing the voltage of the A electrode. Since the capacitance component is formed by the A electrode and the Y electrode, when the A electrode is floated when the voltage of the Y electrode increases, the voltage of the A electrode also increases along with the voltage of the Y electrode. Therefore, the same effect as in FIG. 9 can be achieved. The floating period of the A electrode may be part of the rising period or the whole of the rising period.

Next, a driving circuit capable of generating the driving waveform of FIG. 7 will be described in detail with reference to FIG. 8. FIG. 8 is a driving circuit diagram for generating the driving waveform of FIG. 7. Below each transistor may have a body diode formed with an anode connected to the source and a cathode connected to the drain.

As shown in FIG. 8, the scan driving board 200 includes a rising reset part 211, a falling reset part 212, a scan driving part 213, a sustain discharge part 214, and a reference voltage supply part 215. . In FIG. 8, only one scan electrode Y and one selection circuit 310 are illustrated for convenience of description, and the capacitive component formed by the sustain electrode X adjacent to the scan electrode Y is illustrated by the panel capacitor Cp. As shown. The sustain electrode X of the panel capacitor Cp is biased by the ground voltage.

The rising reset unit 211 includes a diode Dset, a capacitor Cset, and transistors Ypp and Yrr, and applies a voltage gradually rising from the voltage Vs to the voltage Vset to the Y electrode.

The capacitor Cset has a cathode connected between the source of the transistor Ypp and the drain of the transistor Yrr, and the drain of the transistor Ypp and the source of the transistor Yrr are respectively connected to the second node N2. At this time, the capacitor Cset is charged to the voltage (Vset-Vs) when the transistor Yg described below is turned on, and the transistor Yrr ramps the voltage of the panel capacitor Cp to the Vset voltage at turn-on. It operates to allow a minute current to flow from drain to source so as to rise slowly in shape.

The diode Dset is connected between the power supply Vset-Vs for supplying the voltage (Vset-Vs) and the contact of the drain of the transistor Yrr and the capacitor Cset, so that the capacitor Cset-diode Dset-power supply. Shut off the current path to (Vset-Vs).

The falling reset unit 212 includes transistors Ynp and Yfr, and applies a voltage falling from the voltage Vs to the voltage Vnf to the panel capacitor Cp. A drain of the transistor Yfr is connected to the first node N1 and a source of the transistor Yfr is connected to a power supply Vnf supplying a voltage Vnf which is the final voltage of the falling period. The transistor Yfr operates so that a minute current flows from the drain to the source so as to gradually decrease the voltage of the Y electrode to the voltage Vnf at turn-on. At this time, the transistor Ynp blocks the current path to the power source GND-transistor Yg-transistor Ypp-transistor Ynp-transistor Yfr that can be formed when the voltage Vnf is negative. Let's do it.

The scan driver 213 includes a selection circuit 310, a diode Dsch, a capacitor Csch, and a transistor YscL, and sequentially applies a scan voltage, VscL, to the Y electrode. In general, a selection circuit 310 is connected to each scan electrode Y1-Yn in the form of an IC so that a plurality of Y electrodes Y1-Yn can be sequentially selected in an address period. The driving circuit 210 of the scan driving board 200 is commonly connected to the scan electrodes Y1-Yn.

The selection circuit 310 includes transistors Sch and Scl, the source of the transistor Sch and the drain of the transistor Scl are connected to the Y electrode of the panel capacitor Cp, and the source of the transistor Scl. Is connected to the first node N1.

The capacitor Csch is connected between the drain of the transistor sch and the first node N1, and the diode Dsch supplies a contact between the capacitor Csch and the drain of the transistor Sch and a non-scan voltage Vsch. Is connected between the power supply (Vsch). The capacitor Csch is charged to the voltage (Vsch-VscL) at the turn-on of the transistor YscL described below, and the first stage of the capacitor Csch is connected to the drain of the transistor Sch, and the second stage is It is connected to one node N1. The transistor YscL is connected between the first node N1 and the power supply VscL supplying the scan voltage VscL and supplies the VscL voltage to the scan electrode Y forming the discharge cell to be selected.

That is, in the address period Pa, the transistor Sch is turned on to apply the non-scan voltage VscH to the unselected Y electrode, and the scan voltage VscL is applied to the Y electrode to be selected by turning on the transistor scl. do.

The reference voltage supply unit 214 includes a transistor Yg, which is connected between the third node N3 and a power supply 0V supplying a ground voltage to supply a ground voltage to the scan electrode Y. do.

The sustain discharge unit 215 includes an inductor L, transistors Yh, Yl, Yr, and Yf, and diodes Dr and Df, and supplies the voltage Vs and the voltage -Vs to the Y electrode in the sustain period.

Transistor Yh is connected to a power source Vs whose drain is supplying a Vs voltage and a source is connected to the third node N3, and a transistor Yl is connected to the third node N3 and the drain is- It is connected to the power supply (-Vs) which supplies Vs voltage.

The source of the transistor Yr is connected to the second end of the inductor L having the first end connected to the third node N3, and the drain of the transistor Yr is connected to the power supply 0V. The transistor Yf has a drain connected to the second end of the inductor L and a source connected to the power supply 0V. The diodes Dr and Df are formed in the opposite direction to the body diodes of the transistors Yr and Yf to block currents that may be formed by the body diodes of the transistors Yr and Yf. In addition, between the power supply (-Vs) and the second end of the inductor L and between the second end of the inductor L and the power supply Vs, the diodes Dyh and Dyl clamp the potential of the second end of the inductor L. It may be formed.

In the driving waveform of FIG. 7, since the VscL voltage is lower than the Vnf voltage, a current path may be formed through the body diodes of the transistors Yfr and Yer when the transistor YscL is turned on. In order to block this current path, as shown in FIG. 6, a transistor Yfr1 in which a body diode is formed in the opposite direction to the body diode of the transistor Yfr may be further formed. In addition, a diode may be connected instead of the transistors Yfr1 and Yer1.

Hereinafter, a method of generating a driving waveform in the sustain period of FIG. 7 using the driving circuit of FIG. 8 will be described in detail with reference to FIGS. 9, 10A, and 10B.

FIG. 9 is a drive timing diagram for generating a drive waveform in the sustain period of FIG. 7, and FIGS. 10A and 10B are views showing the operation of the circuit of FIG. 8 in the sustain period. Here, it is assumed that the transistor Y1 is turned on before the time point t1 and the -Vs voltage is applied to the Y electrode. In the driving circuit of FIG. 8, the current paths of the third node N3, the second node N2, the first node, and the panel capacitor Cp to the scan electrode Y may be a body diode or a transistor of the transistor Ypp. (Ynp) and through the body diode of the transistor Scl. In addition, the current paths of the panel capacitor Cp to the scan electrode Y, the first node N1, the second node N2, and the first node N1 may be a transistor Scl, a body diode of the transistor Ynp, and It is formed through the transistor Ypp. In the following, these two current paths are referred to as "main paths". When the main path is formed, the transistors Ypp, Ynp and Scl are turned on, and these transistors Ypp, Ynp and Scl are always on in the sustain period. It is assumed to be described.

At the time point t1, the transistor Yr is turned on and the transistor Y1 is turned off while the Y electrode is maintained at the voltage -Vs. Then, resonance occurs between the inductor L and the panel capacitor Cp through the path of the ground terminal GND, the transistor Yr, the inductor L, the main path, and the panel capacitor Cp. This resonance causes the voltage of the scan electrode Y to rise to near the Vs voltage (path ①).

Then, at the time point t2, the transistor Yh is turned on and the transistor Yr is turned off to maintain the voltage of the Y electrode at the voltage Vs (path ②).

10B, the transistor Yf is turned on and the transistor Yh is turned off while the voltage of the Y electrode is maintained at the voltage Vs, thereby causing the capacitor Cp, the main path, the inductor L, and the transistor Yf. And resonance occurs between the inductor L and the panel capacitor Cp through the path of the ground terminal GND. By this resonance, the voltage of the Y electrode drops to near the -Vs voltage (path ③).

Subsequently, at time t4, transistor Yf is turned off and transistor Y1 is turned on to maintain the voltage of scan electrode Y at a voltage of −Vs (path ④).

In general, if the load is only a resistance, that is, the inductance is zero, turning off the switch immediately causes the voltage on the load to be zero, so that the load current is also zero, but in a circuit with inductance, The phenomenon is different from the case with only load. Since the inductance does not increase when the current increases, and in the direction that does not decrease when the current decreases, the current flowing through the inductance cannot be changed rapidly.

That is, in the driving circuits of FIGS. 10A and 10B, the transistors Yh and Y1 are turned on at the time points t2 and t4 due to the characteristics of the inductor L that tries to prevent the current from rising or falling momentarily. The inductor current flows in the opposite direction, and the inductor currents Ids + and Ids− flow back through the diodes Dyh and Dyl (path ② 'and path ④'). This reflux current is referred to as free wheeling current or fly wheeling current. The freewheeling current, however, causes a lot of stress on the circuit elements because the current flows in the opposite direction.

Looking at the sustain period, since the voltage variation of the voltage of the Y electrode from the Vs voltage to the -Vs voltage is large, a large amount of current also flows in the inductor L. However, since the freewheeling current is proportional to the current flowing through the inductor L, the larger the current flowing through the inductor L, the greater the freewheeling current, which stresses the transistors Yh and Yl, thereby causing the transistors Yh and Yl. There is a problem that is broken.

In general, if the freewheeling current is called Ids (t), Ids (t) is expressed by Equation 1.

Where L is the inductance of the inductor, R is the parasitic resistance component, and A is an integer.

As can be seen from Equation 1, as (R / L) increases, the freewheeling current Ids can be quickly reduced to zero. In other words, as the inductance value of the inductor decreases, the freewheeling current can be reduced quickly.

At this time, when (R / L) becomes large (arrow direction), as shown in FIG. 11, the freewheeling current Ids can be reduced quickly to zero. In other words, as the inductance value of the inductor decreases, the freewheeling current decay relaxation time is faster, so that the freewheeling current can be quickly reduced to zero.

 Hereinafter, the driving circuit of the plasma display panel capable of reducing the circuit element stress caused by the freewheeling current by applying the same to the driving circuit of FIG. 8 will be described in detail with reference to FIGS. 11 to 13. 11 to 13, the driving circuit of the plasma display panel is simplified for convenience of description.

11 to 13 are driving circuit diagrams of the plasma display panel according to the first to third embodiments of the present invention, respectively.

11 and 13, in order to reduce the freewheeling current, two inductors L1 and L2 having inductance 1/2 of the inductance used in the driving circuit of FIG. 8 are connected in series and diodes Dyh, It is the same as the driving circuit of FIG. 8 except for connecting Dyl).

Referring to FIG. 11, the driving circuit of FIG. 8 is the same except that the inductors L1 and L2 are connected in series and the diode Dyh is connected to the contacts of the inductors L1 and L2. This forms a freewheeling current path (path ② ', path ④'). Looking at the freewheeling current path (path ② '), since the inductance of the inductor L2 is 1/2 of the inductance of the inductor L in the driving circuit of FIG. 8, the R / L becomes large. Therefore, the freewheeling current reduction time is reduced, so that the freewheeling current can be reduced to zero earlier than the driving circuit of FIG. 8. Therefore, device stress caused by freewheeling current can be reduced.

Since the freewheeling current path (path ④ ') passes through both inductors L1 and L2, the sum of the inductances of the inductors L1 and L2 is equal to the inductance of the inductor L in the driving circuit of FIG. The decay time is equal to the freewheeling current path (path ④ ') in the drive circuit of FIG.

12 is the same as the driving circuit of FIG. 8 except that the inductors L1 and L2 are connected in series and the diode Dyl is connected to the contacts of the inductors L1 and L2. This forms a freewheeling current path (path ② ', path ④'). As the freewheeling current path (path ② ') passes through both inductors L1 and L2, the freewheeling current attenuation relaxation time is the same as the freewheeling current path (path ②') in the driving circuit of FIG.

In addition, since the freewheeling current path (path ② ') passes only the inductor L2, the freewheeling current attenuation relaxation time is reduced, thereby reducing the freewheeling current to zero faster than the driving circuit of FIG. Therefore, device stress caused by freewheeling current can be reduced.

Next, referring to FIG. 13, it is the same as the driving circuit of FIG. 8 except that the inductors L1 and L2 are connected in series and the diodes Dyh and Dyl are connected to the contacts of the inductors L1 and L2. In this case, since the freewheeling current paths (path ② 'and path ④') all pass through the inductor L2, each of the freewheeling current paths (path ② 'and path ④') is faster than the driving circuit of FIG. Since it can be reduced to zero, the device stress caused by the freewheeling current can be reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the board for driving the sustain electrode can be removed. In other words, it is possible to implement an integrated board that is substantially driven by only one board, thereby reducing the unit cost.

In the case where the scan electrode and the sustain electrode are implemented as the respective driving boards, since the driving waveforms in the reset period and the address period are mainly supplied from the scan driving board, impedances formed in the scan driving board and the sustain driving board are different. Accordingly, the sustain discharge pulse applied to the scan electrode and the sustain discharge pulse applied to the sustain electrode in the sustain period may be different. However, according to the present invention, since the pulse for sustain discharge is supplied only from the scan driving board, the impedance is always constant.

In addition, in the sustain period, the freewheeling current flows due to a sustain discharge pulse having only a high voltage and a low voltage only in the scan electrode, thereby stressing the circuit device. In the embodiment of the present invention, an inductor in a driving circuit for generating a sustain discharge pulse By connecting the two in series and connecting the clamping diode between its contact and the high and low voltage supply of the sustain discharge pulse, the stress of the circuit element due to the freewheeling current can be reduced.

1 is a partial perspective view of a plasma display panel.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

3 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

6 is a diagram showing the wall charge state of a cell when a strong discharge occurs in the reset period.

7 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

FIG. 8 is a driving circuit diagram for generating the driving waveform of FIG. 7.

9 is a drive timing diagram for generating a drive waveform in the sustain period of FIG.

10A and 10B show the operation of the circuit of FIG. 8 in the sustain period.

11 to 13 are driving circuit diagrams of the plasma display panel according to the first to third embodiments of the present invention, respectively.

Claims (7)

A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and And a driving circuit configured to alternately apply a positive second voltage and a negative third voltage to the second electrode in a state in which the voltage of the first electrode is biased to the first voltage. The drive circuit, First inductor, A second inductor having a first end electrically connected to the first inductor and a second end electrically connected to the second electrode; A first switching element electrically connected between a first power supply for supplying the second voltage and the second electrode; A second switching element electrically connected between a second power supply for supplying the third voltage and the second electrode; A third switching element electrically connected between a third power supply for supplying a fourth voltage and a second end of the inductor; A fourth switching element electrically connected between the third power supply and the second end of the inductor, and At least one diode electrically connected between at least one of the contacts of the first and second inductors and the first power source or between at least one of the contacts of the first and second inductors and the second power source Plasma display device comprising a. The method of claim 1, The at least one diode, A first diode having an anode connected to the contacts of the first and second inductors and a cathode connected to the first power source, and A second diode having a cathode connected to the contacts of the first and second inductors and an anode connected to the second power source; Plasma display device comprising a. The method according to claim 1 or 2, And the first electrode is biased to the first voltage in a reset period and an address period. The method of claim 3, wherein And the first voltage is a ground voltage. The method of claim 1, And the fourth voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, wherein the first electrode is disposed in a first period during the sustain period. In the method of alternately applying a positive second voltage and a negative third voltage to the second electrode while being biased by a voltage, Increasing the voltage of the second electrode through first and second inductors connected in series with the second electrode, Applying the second voltage to the second electrode, Reducing the voltage of the second electrode through the first and second inductors, and Applying the third voltage to the second electrode; Plasma display in which current flows through diodes connected to the contacts of the first and second inductors in at least one of when the second voltage is applied to the second electrode and when the third voltage is applied to the second electrode. How to drive the panel. The method of claim 6, And the first electrode is biased to the first voltage in a reset period and an address period.