KR20060053345A - Plasma display device and driving method thereof - Google Patents

Abstract

In the plasma display panel, a driving waveform is applied to the scan electrode while the sustain electrode is biased to the ground voltage to perform a reset operation, an address operation, and a sustain discharge operation. Then, the driving board driving the sustain electrode can be removed.

According to the present invention, after the address operation is performed on one of the scan electrode lines, the sustain discharge operation on the scan electrode line is performed only after the address operation of the last scan electrode line is completed. In order to solve the problem that a significant time gap occurs until the occurrence of the sustain discharge operation, the cells of the plasma display panel including the plurality of scan electrodes and the plurality of sustain electrodes are divided into odd and even lines. In expressing the gradation in the frame-subfield method, it is possible to minimize the temporal gap between the address period and the sustain period so that smooth sustain discharge occurs in the sustain period.

PDP, address / hold mix period, common hold period, address discharge

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

2 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

4 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

5 is a diagram illustrating a gray scale display method of a plasma display panel according to a first exemplary embodiment of the present invention.

FIG. 6 is a diagram for describing a driving method of a plasma display device in which a scan electrode line is divided into a plurality of (n) groups, and one frame is divided into a plurality of subfields for each group.

FIG. 7 is a diagram illustrating an example in which cells of a plasma display panel according to the second exemplary embodiment are divided into odd and even scan electrode line groups.

8 is a driving waveform diagram of a plasma display device according to a second embodiment of the present invention.

9 is a driving waveform diagram of a plasma display device according to a third embodiment of the present invention.

The present invention relates to a plasma display device including a plasma display panel (PDP) and a driving method thereof.

A plasma display device is a flat display device that displays characters or images by using plasma generated by gas discharge. In the display panel, tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

An object of the present invention is to provide a plasma display device having an integrated board capable of driving a scan electrode and a sustain electrode. In addition, it is a technical object of the present invention to provide a drive waveform suitable for an integrated board and to ensure the reliability of the driving operation and discharge characteristics.

In order to solve this problem, the present invention applies a drive waveform to the scan electrode while the sustain electrode is biased at a constant voltage.

According to an aspect of the present invention, a cell of a plasma display panel including a plurality of first electrodes and a plurality of second electrodes is divided into a plurality of groups, and each frame is divided into a plurality of subfields for driving. In the driving method of the plasma display device,

The subfield includes a plurality of address periods and a plurality of sustain periods respectively corresponding to the plurality of groups, and selecting cells to be displayed from among the cells of each group in the address period of each group; And applying a pulse alternately having a sixth voltage and a seventh voltage lower than the sixth voltage to the second electrode while biasing the first electrode to the first voltage in each sustain period. Maintaining discharge;

At least one sustain period of the plurality of sustain periods is present between the adjacent address periods.

In the plasma display panel including a plurality of first electrodes and a plurality of second electrodes forming a plurality of cells according to another aspect of the present invention, the plurality of first electrodes and the second electrodes are divided into a plurality of groups, A driving method of a plasma display device in which one frame is divided into a plurality of subfields for a group to be driven,

In at least one subfield including an address period and a sustain period,

The address period and the sustain period are sequentially performed for each group, but after the end of the address operation of each group, the sustain period is performed for the cells of the addressed group, and for the cells of the other group after the end of the sustain period. Selectively performs the sustain period for the cells of another group previously addressed while performing the sustain period for the cells of either group by performing an address operation,

In a state in which the first electrode is biased to the first voltage in the subfield, the high level of the sustain discharge pulse higher than the first voltage and the low level of the sustain discharge pulse lower than the first voltage are alternated to the second electrode. It is characterized in that the sustain discharge for the selected cells in the address period is applied to.

According to another aspect of the present invention, a plasma display panel including a plurality of first electrodes and a plurality of second electrodes, and the first electrode and the second electrode are divided into a plurality of groups, and one frame is provided for each group. A plasma display device comprising a driving circuit for dividing and driving into three subfields,

The driving circuit

In at least one subfield including a reset period, a plurality of address periods, and a plurality of sustain periods,

In a state in which the first electrode is biased at a first voltage,

The address period and the sustain period of each group are sequentially performed, but after the end of the address operation of each group, the sustain period is performed for the cells of each addressed group, and for the cells of the other group after the end of the sustain period. A sustain period is selectively performed for cells of another group previously addressed while performing an address operation to perform a sustain period for any one group of cells, and in the sustain period, And controlling the driving signals applied to the first and second electrodes to alternately apply the high level of the high sustain discharge pulse and the low level of the sustain discharge pulse lower than the first voltage. .

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a schematic conceptual view of a plasma display panel according to an exemplary embodiment of the present invention. 3 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 1, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 2, the plasma display panel 10 includes a plurality of address electrodes A1 to Am extending in the vertical direction, a plurality of scan electrodes Y1 to Yn extending in the horizontal direction, and a plurality of sustain electrodes X1 to Xn). The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 10 includes an insulating substrate on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and an insulating substrate on which address electrodes A1 to Am are arranged. The two insulating substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. . At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a cell.

As shown in FIG. 3, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 3, the plasma display apparatus for dual driving is described as an example. However, in the case of the single driving, the address buffer board 100 is disposed at any one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage for selecting a discharge cell to be displayed to each address electrode A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, the scan drive board 200 is electrically connected to the scan electrodes Y1 to Yn via the scan buffer board 300, and the sustain electrode. (X1 to Xn) are biased at a constant voltage. The scan buffer board 300 applies a voltage for sequentially selecting the scan electrodes Y1 to Yn in the address period to the scan electrodes Y1 to Yn. The scan driving board 200 receives a driving signal from the image processing and control board 400 and applies a driving voltage to the scan electrodes Y1 to Yn. In FIG. 3, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. Each is applied to the address driving board 100 and the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display panel according to the first exemplary embodiment of the present invention will be described with reference to FIG. 4.

4 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 5, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (ground voltage in FIG. 4), the description of the voltage applied to the X electrode is omitted.

4, one subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period of the reset period, the voltage of the Y electrode is gradually increased from the voltage of Vs to the voltage of Vset while the A electrode is maintained at the reference voltage (0 V in FIG. 4). In FIG. 4, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 4, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally the same voltage as the voltage applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the A electrode is maintained at the reference voltage. Then, a slight discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, so that the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode The charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. At this time, the VscL voltage is called a scan voltage and the VscH voltage is called a non-scan voltage.

Meanwhile, in order to perform such an operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, for example, in the order arranged in the vertical direction in a single drive. Y electrode can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, the scan pulse of the VscL voltage is applied to the scan electrodes of the first row, and the address pulse of the Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall electrodes are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying a scan pulse of VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be described. When the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A and Y electrodes and the external voltage Vnf between the A and Y electrodes is determined by the discharge start voltage Vfay between the A and Y electrodes. do. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, in the cell where the address discharge occurred in the address period, the wall voltage Vwxy of the Y electrode with respect to the X electrode was formed with a high voltage. In the sustain period, the Y electrode and the X electrode were first applied with a pulse having a Vs voltage to the Y electrode. It causes maintenance discharge between them. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is lower than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X are repeated the number of times corresponding to the weight indicated by the corresponding subfield. .

As described above, in the first embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

Meanwhile, the driving method of the plasma display device according to the first exemplary embodiment of the present invention sequentially completes the address operation from the first scan electrode line Y1 to the last scan electrode line Yn as shown in FIG. In this period, sustain discharge operation is performed on all cells simultaneously. According to such a driving method, after an address operation is performed on one scan electrode line, the sustain discharge operation in the scan electrode line is performed only after the address operation of the last scan electrode line is completed. Therefore, there is a problem that a significant time gap occurs until the sustain discharge operation occurs in the cell in which the address operation has occurred, and the sustain discharge operation may become unstable.

Accordingly, an embodiment in which the sustain discharge operation becomes unstable due to the occurrence of the temporal gap as described above will be described with reference to FIGS. 6 to 9.

First, a driving method of the plasma display device according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 6 to 8.

FIG. 6 is a diagram for describing a driving method of a plasma display device in which a scan electrode line is divided into a plurality of (n) groups, and one frame is divided into a plurality of subfields for each group. In FIG. 6, gray levels are represented by a combination of eight subfields.

Meanwhile, in the method of dividing the scan electrode lines into a plurality of groups, groups may be formed by grouping a predetermined number of scan electrode lines in a physical arrangement order. For example, when the panel is formed of 800 scan electrode lines, the first to 100th scan electrode lines may be set as the first group and the 101st to 200th scan electrode lines may be set as the second group while being divided into eight groups. However, in grouping the scan electrode lines, adjacent neighboring lines may not be collected, but scan electrode lines spaced apart from each other may be collected in the same group. That is, the first, 9, 17, ... (8k + 1) th scan electrode lines are allocated to the first group, and the second, 10, 18, ... (8k + 2) th scan electrodes are allocated to the second group. Allocating lines. On the other hand, if necessary, it is possible to group the scan electrode lines in an arbitrary irregular manner.

FIG. 7 is a diagram illustrating an example in which scan electrodes of a plasma display panel according to a second exemplary embodiment are divided into odd and even electrode lines. One subfield includes a reset period R, an address / sustain mixing period T1, and a common sustain period T2.

In the reset period R, a reset pulse is applied to all of the scan electrode lines to initialize the wall charge state of the cell.

The address / sustain mixing period T1 sequentially performs an address operation from the first scan electrode line of the odd line Yodd to the last scan electrode line (Aodd). When all the address operations are completed for the cells of the odd line Yodd, at least one sustain pulse is applied to the scan electrode Yodd of the odd line to perform the sustain discharge operation (Sodd).

When the sustain period (Sodd) of the odd line (Yodd) is finished, the address operation for the cells of the even line (Yeven) is performed (Aeven).

When the address period Aeven of the even line Yeven ends, that is, when all address operations for the scan electrode lines belonging to the even line Yeven are completed, the sustain period Seven for the even line Yeven is performed. do. When the sustain period Seven for the even line Yeven ends, a common sustain period T2 is performed in which sustain discharge is performed in common for the odd line Yod and the even line Yeven.

 At this time, the first sustain discharge occurs once in each of the odd and even lines in the address / sustain mixing period T1, and then the sustain discharge occurs in common in the common sustain period T2 to satisfy the gray level between the odd and even lines. As described above, at least two sustain discharge pulses may be generated so that the sustain discharge is also performed on the odd line Yodd which has already been addressed in the sustain period Seven after the address period Aeven of the even line Yeven. Can be authorized. In this case, a luminance difference equal to the number of sustain discharges generated during the sustain period Seven in the odd line Yod occurs, and a predetermined additional sustain period is required to equally correct the luminance difference between the lines. For this purpose, it may further include a luminance correction period (not shown) which is a sustain discharge period selectively performed for each line so that the gray levels of the cells of each line are equally corrected with each other.

On the other hand, the common sustain period T2 is selectively used when the gradation degree specification assigned to each subfield is not satisfied by the address / sustain mixing period T1 or the address / sustain mixing period T1 and the luminance correction period. Can be performed. The common holding period T2 may be performed after the address / holding mixing period T1 as shown in FIG. 7 or may be performed after the luminance correction period.

In addition, the size of the common sustain period T2 may be appropriately changed according to the weight of the subfield.

In addition, one subfield may be implemented only in the address / sustain mixing period T1. Specifically, after the address operation and the sustain discharge operation on the odd line Yod are completed, the address operation and the sustain discharge operation of the even line Yeven are sequentially performed.

FIG. 8 is a driving waveform diagram of the plasma display device according to the second embodiment of the present invention using the driving method described with reference to FIG. 7.

In the reset period R, a reset waveform is applied to all the scan electrode lines Yodd and Yeven to initialize the wall charge state of the cell. Since the reset waveform of FIG. 8 is the waveform shown in FIG. 4, detailed description thereof will be omitted.

In the address / sustain mixing period T1, first, an address period Aodd of odd lines Yodd is performed, and a sustain period Sodd of odd lines Yodd is performed. After the sustain period (Sodd) of the odd lines (Yodd) is completed, the address period (Aeven) of the even lines (Yeven) is performed. The sustain period Seven of the even lines Yeven is then performed.

More specifically, first, the address period Aodd of the address / sustain mixing period T1 is performed on the scan electrodes of the odd line Yodd. In the address period Aodd, a scan pulse having a VscL voltage is sequentially applied to the scan electrodes Yodd of odd lines while the scan electrodes Yeven of even lines are maintained at the VscH voltage. Although not shown, an address voltage is applied to an address electrode forming a cell to be selected among cells formed by a scan electrode to which a scan pulse is applied. Then, an address discharge occurs due to a difference between the address voltage applied to the address electrode and the voltage VscL applied to the scan electrode and the wall voltage caused by the wall charges formed on the address electrode and the scan electrode, thereby forming a wall voltage on the scan electrode and the sustain electrode. do.

In the sustain period Sodd of the address / sustain mixing period T1, a sustain discharge pulse is applied to the scan electrodes Yodd and Yeven, and the sustain electrode X is biased to the reference voltage 0V. In FIG. 8, one sustain discharge pulse is applied to the scan electrodes Yodd and Yeven. The sustain discharge pulse has a high level voltage (Vs voltage in FIG. 8) and a low level voltage (-Vs voltage in FIG. 8), and the voltage Vs or -Vs is a voltage capable of causing sustain discharge along with the wall voltage. First, the Vs voltage is applied to the scan electrodes Yod and Yeven, and the sustain electrode X is biased to the reference voltage 0V, and the scan electrode Yodd and the sustain electrode (B) are addressed by the address discharge in the address period Aodd. In a cell in which a wall voltage is formed between X), sustain discharge occurs due to the wall voltage and the voltage difference Vs between the scan electrode Yodd and the sustain electrode X, thereby forming wall voltages having opposite polarities between the scan electrode and the sustain electrode. do. On the other hand, while the sustain discharge pulse Vs is also applied to the scan electrodes of the even lines Yeven in the sustain period Sodd of the address / sustain mixing period T1, the scan electrodes Yeven and the sustain electrodes (In the address period Aodd) are applied. Since no wall voltage is formed between X), sustain discharge does not occur. As such, when the address periods Aodd and the sustain periods Sod of the address / sustain mixing period T1 are completed for the scan electrodes Yodds of the odd lines, the address / holds of the scan electrodes Yeven of the even lines are subsequently performed. The address period Aeven and the sustain period Seven of the mixing period T1 are performed.

For the even-numbered scan electrodes Yeven, in the address period Aeven of the address / sustain mixing period T1, VscL is sequentially applied to the scan electrode Yeven while the other scan electrode Yodd is maintained at the VscH voltage. A scan pulse having a voltage is applied. As described above, the wall voltage is formed by applying the address voltage to the address electrode Aeven which forms the cell to be selected among the cells formed by the scan electrode Y to which the VscL voltage is applied. Although the sustain period Sodd and the address period Aeven are shown as being separated from each other, as shown in FIG. 8, the two periods Sodd and Aeven are shown as being overlapped with a part of the sustain period Sodd and the address period Aeven. You may.

In the sustain period Seven of the address / sustain mixing period T1, a sustain discharge pulse is applied to the scan electrodes Yodd and Yeven, and the sustain electrode X is biased to the reference voltage (0V). As in the sustain period (Sodd), the sustain discharge pulse has a high level voltage (Vs voltage in FIG. 8) and a low level voltage (-Vs voltage in FIG. 8), and the Vs voltage or -Vs voltage is sustained along with the wall voltage. This can cause voltage. Then, since there was no previous sustain discharge in the cells of odd lines (Yodd), the wall voltage was formed to be reverse polarity, so that sustain discharge did not occur, and cells in which the wall voltage was formed in the address period (Aeven) among the cells of even lines (Yeven) A maintenance discharge occurs at.

Then, in the common sustain period T2, sustain discharge pulses having a voltage of Vs and a voltage of -Vs are alternately applied to the scan electrodes Yodd and Yeven, and the sustain electrode X is biased to the reference voltage (0V) so that the whole The sustain discharge is performed in common with the scan electrodes Yodd and Yeven.

Therefore, in the subfield of FIG. 8, the six discharges are performed in the same manner as in the odd line scan electrode group Yodd and the even line scan electrode group Yeven.

In this manner, the number of sustain discharges in the odd line scan electrode group Yodd is limited by the number of sustain discharges in the sustain period Sodd of the address / sustain mixing period T1 so that the odd lines Yodd and the even lines Yeven ) Can be equally matched.

9 is a driving waveform diagram of a plasma display device according to a third embodiment of the present invention.

9, one subfield includes a reset period R, an address / sustain mixing period T1, and a common sustain period T2, and the reset period T includes a rising period and a falling period.

In the rising period of the reset period R, the voltage of the scan electrode Y is gradually increased from the voltage Vs to the voltage Vset while the address electrode A and the sustain electrode X are held at the reference voltage (0 V in FIG. 9). Increase. In FIG. 9, the voltage of the scan electrode Y is shown to increase in the form of a lamp. On the other hand, the detailed description of the driving waveform applied in the rising period of the reset period is the same as in the second embodiment of the present invention will be omitted.

Subsequently, in the falling period of the reset period R, the voltage of the scan electrode Y is maintained at Vs while the address electrode A and the sustain electrode X are maintained at the reference voltage and the constant voltage (Vb voltage in FIG. 9), respectively. It gradually decreases from voltage to Vnf. Then, while the voltage of the scan electrode Y decreases, a weak discharge occurs between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A, and thus the scan electrode Y The negative wall charges formed and the positive wall charges formed on the sustain electrode X and the address electrode A are erased.

In general, the difference between the Vnf voltage and the Vb voltage is set near the discharge start voltage between the scan electrode Y and the sustain electrode X. As a result, the wall voltage between the scan electrode Y and the sustain electrode X becomes almost 0 V, whereby cells that do not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the address electrode A is maintained at the reference voltage, the wall voltage between the scan electrode Y and the address electrode A is determined by the level of the Vnf voltage.

Next, in the address / sustain mixing period T1, the address periods Aodd and Aeven of the scan electrodes Yodd and Yeven of each group are sequentially performed, followed by the common sustain period T2. Here, since the operations in the address / sustain mixing period T1 and the common sustain period T2 are the same as in the second embodiment of the present invention, overlapping description is omitted.

On the other hand, the sustain electrode X is biased to the voltage Vb in the address / sustain mixing period T1 'except for the falling period and the sustain period Seven of the reset period R, but only in the address / sustain mixing period T1'. The sustain electrode X may be biased to the Vb voltage. In this case, the voltage Vnf may be set near the discharge start voltage between the scan electrode Y and the sustain electrode X in the falling period of the reset period. As a result, the wall voltage between the scan electrode Y and the sustain electrode becomes almost 0 V, thereby preventing the cells that do not have address discharge in the address period from being discharged in the sustain period.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the integrated board driving with only one board can be realized, thereby reducing the unit cost. .

In addition, according to the present invention, the cells constituting the display panel may be divided and driven by electrode lines without adding a driving circuit. In addition, when the cells constituting the display panel are divided by electrode lines without adding a driving circuit, and the gray level is expressed in a frame-subfield method, the time gap between the address period and the sustain period is minimized, thereby maintaining smooth maintenance in the sustain period. Discharge may occur.

Claims (14)

In the plasma display panel including a plurality of first electrodes and a plurality of second electrodes forming a plurality of cells, the plurality of first electrodes and the second electrodes are divided into a plurality of groups, and one frame is provided for each group. A driving method of a plasma display device which is divided and driven into three subfields, The subfield includes a plurality of address periods and a plurality of sustain periods respectively corresponding to the plurality of groups, Selecting cells to be displayed from cells of each group in the address period of each group; And The selected discharge cell is applied by alternately applying a pulse having a sixth voltage and a seventh voltage lower than the sixth voltage to the second electrode while biasing the first electrode to the first voltage in each sustain period. Sustaining discharge; At least one sustain period among the plurality of sustain periods exists between adjacent address periods. The method of claim 1, The subfield further includes a reset period, and after gradually increasing the voltage of the second electrode from the second voltage to the third voltage while biasing the first electrode to the first voltage in the reset period, 4. A method of driving a plasma display device that gradually reduces from four voltages to a fifth voltage. The method of claim 2, A first period during which the voltage of the second electrode decreases from the fourth voltage to a fifth voltage in the reset period; And A second period including at least one sustain period of the plurality of sustain periods and a plurality of address periods adjacent to the sustain period And biasing the voltage of the first electrode to a voltage higher than the first voltage in a third period of time. The method of claim 3, And driving the voltage of the first electrode to a voltage higher than the first voltage in the second period. The method of claim 1, And the first voltage is a ground voltage. In the plasma display panel including a plurality of first electrodes and a plurality of second electrodes forming a plurality of cells, the plurality of first electrodes and the second electrodes are divided into a plurality of groups, and one frame is provided for each group. In the driving method of the plasma display device divided into two sub-fields, In at least one subfield including an address period and a sustain period, The address period and the sustain period are sequentially performed for each group, but after the end of the address operation of each group, the sustain period is performed for the cells of the addressed group, and for the cells of the other group after the end of the sustain period. Selectively performs the sustain period for the cells of another group previously addressed while performing the sustain period for the cells of either group by performing an address operation, In the state in which the first electrode is biased to the first voltage in the subfield, Plasma display performing sustain discharge for the cells selected in the address period by alternately applying a high level of the sustain discharge pulse higher than the first voltage and a low level of the sustain discharge pulse lower than the first voltage to the second electrode. Method of driving the device. The method of claim 6, And the first voltage is a ground voltage. The method of claim 6, The sustain period further includes a common period in which sustain discharge is performed in common for a predetermined period for all groups. A plasma display panel including a plurality of first electrodes and a plurality of second electrodes, and the first electrode and the second electrode are divided into a plurality of groups, and each frame is driven by dividing one frame into a plurality of subfields. A plasma display device comprising a driving circuit, The driving circuit In at least one subfield including a reset period, a plurality of address periods, and a plurality of sustain periods, In a state in which the first electrode is biased at a first voltage, The address period and the sustain period of each group are sequentially performed, but after the end of the address operation of each group, a sustain period is performed for the cells of each addressed group, and for the cells of the other group after the end of the sustain period. Selectively performs the sustain period for the cells of another group previously addressed while performing the sustain period for the cells of either group by performing an address operation,  In order to perform sustain discharge by alternately applying a high level of a sustain discharge pulse higher than the first voltage and a low level of a sustain discharge pulse lower than the first voltage to the second electrode in the sustain period. A plasma display device for controlling a driving signal applied to two electrodes. The method of claim 9, The reset period includes a first period of decreasing the voltage of the second electrode from the second voltage to a third voltage. The method of claim 10, The first period; And A second period including at least one sustain period of the plurality of sustain periods and a plurality of address periods adjacent to the sustain period And biasing the voltage of the first electrode to a voltage higher than the first voltage in a third period of time. The method of claim 10, And biasing the voltage of the first electrode to a voltage higher than the first voltage in the second period. The method of claim 9, And the first voltage is a ground voltage. The method of claim 9, The sustain period further includes a common period in which sustain discharge is performed in common for a predetermined period for all groups.

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