KR100589377B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel and a plasma display device. In particular, in the driving method of the plasma display panel, a voltage lower than the final voltage of the reset period is applied to the scan electrode of the discharge cell to be selected during the address period, and a voltage higher than the voltage applied to the sustain electrode in the sustain period is applied to the sustain electrode. Is authorized. The sustain discharge pulse voltage is alternately applied to the sustain electrode and the scan electrode during the sustain period. At this time, the first sustain discharge pulse voltage greater than the voltage level of the sustain discharge pulse voltage and greater than the width of the sustain discharge pulse voltage is applied to the scan electrode or the sustain electrode.

Plasma display panel, address period, sustain period, sustain discharge pulse

Description

Plasma display panel driving method and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a partial perspective view of a typical plasma display panel.

2 is an electrode array diagram of a general plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

7A to 7B are graphs of actual measurement of driving voltage margins according to driving waveforms in the address periods of FIGS. 3 and 5 (or 6), respectively.

8A to 8C are graphs of actual measurement of driving voltage margins according to driving waveforms in the sustain period and the sustain period of FIGS. 3 and 5 (or FIG. 6), respectively.

The present invention relates to a method of driving a plasma display panel and a plasma display device.

Recently, PDPs have been in the spotlight as flat panel display devices due to their high brightness, high luminous efficiency, and wide viewing angles, compared to other display devices.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. The plurality of address electrodes A ₁ -A _m are arranged in the vertical direction, and the plurality of scan electrodes Y ₁ -Y _n and the storage electrodes X ₁ -X _n are arranged in pairs in the horizontal direction.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and gray levels are expressed by a combination of subfields. In general, each subfield includes a reset period, an address period, and a sustain period. The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

As shown in FIG. 3, in the reset period P _r , all the discharge cells are discharged by the rising ramp voltage, so that a large amount of negative charge is accumulated in the scan electrode Y, and a large amount is positive in the address electrode A. FIG. Charges accumulate. Next, a ramp voltage that is applied to the scan electrode Y is applied to the discharge cell to maintain the wall charge structure and lower the potential to the negative potential level V _n . At this time, the wall charges formed in the discharge cells are erased by the rising lamp voltage.

In the address period _Pa , while the other scan electrode Y is maintained at the V _sc voltage, the scan electrode Y is sequentially selected by applying the voltage V _n to the scan electrode Y. And it is applied to the address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by the scan electrode (Y) is applied to the voltage V _n. Then, the voltage applied to the address electrodes (A) (V _a) and the wall voltage due to the wall charges formed on the difference and the address electrode (A) and scan electrodes (Y) of the voltage (V _n) applied to the scan electrode (Y) This causes address discharge.

Next, in the sustain period P _s , sustain pulses (hereinafter, referred to as sustain discharges) are sequentially applied to the scan electrode Y and the sustain electrode X. The sustain discharge pulse is a pulse that causes the voltage difference between the scan electrode Y and the sustain electrode X to alternately become a V _s voltage and a -V _s voltage. The voltage V _{s is a} voltage lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. If the address period (P _a), the wall voltage between the scan electrode (Y) and the sustain electrode (X) by the address discharge are formed on the scan electrode by the wall voltage and V _s the voltage (Y) and the sustain electrode (X) Discharge occurs at.

In general, in order to implement a high-efficiency plasma display panel, the ratio of xenon (Xe) in the discharge gas is improved to increase luminous efficiency and luminance. However, as the ratio of xenon increases, the driving voltage increases, thereby destabilizing the driving operation of the plasma display panel. Accordingly, freedom of driving the plasma display panel while increasing the ratio of xenon has been required. In other words, in order to realize a high-efficiency plasma display panel, the partial pressure of xenon in the discharge gas is increased. To speak).

However, when the voltage (V _n) to be applied to the scan electrode (Y) at the final voltage (V _n) and the address period of the reset period, the address period, as shown in the driving waveform of the conventional plasma display panel is equal to, for stable discharging in implementing a higher voltage difference during the address period (P _a) there is a limit.

At this time, if the voltage V _n applied to the last part of the reset period is further lowered, the voltage difference applied between the address electrode and the scan electrode in the address period may increase, but the voltage V _n applied to the last part of the reset period may be increased. If lower than the predetermined range is a problem that positive (+) wall charges generated in the ramp falling section is accumulated on the scan electrode (Y) instead of accumulating on the address electrode (A).

In addition, in the sustain period P _s , when a pulse having a narrow sustain discharge pulse width, a low voltage pulse, or a pulse whose operation is slowed down is applied, the sustain discharge becomes unstable and a problem in which normal display cannot be performed occurs.

An object of the present invention is to solve the above problems, and to provide a plasma display panel driving method and a plasma display device capable of driving a high efficiency plasma panel in an address period and a sustain period.

In order to achieve the above object, according to one aspect of the present invention, a method of driving a plasma display panel including a reset period, an address period and a sustain period and applying a sustain discharge pulse voltage to the scan electrode and the sustain electrode during the sustain period. This is provided. The driving method includes applying a falling ramp voltage falling from a first voltage to a second voltage to the scan electrode in a reset period; Applying an address voltage lower than the second voltage to the scan electrode in an address period; And applying a first sustain discharge pulse voltage having a third voltage level greater than the sustain discharge pulse voltage to the scan electrode or sustain electrode in the sustain period. In the step of applying an address, a fourth voltage greater than the sustain discharge pulse voltage is applied to the sustain electrode.

In this case, the first voltage may be at the same level as the sustain discharge pulse voltage, and the third voltage may be applied to the scan electrode during the sustain period.

In addition, the first sustain discharge pulse voltage may be a sustain discharge pulse voltage applied at the beginning of the sustain period, and the width of the first sustain discharge pulse voltage may be longer than the width of the sustain discharge pulse voltage applied to the sustain electrode. have.

In addition, two or more first sustain discharge pulse voltages may be applied during the sustain period.

According to another feature of the invention, the step of applying a falling ramp voltage falling from the first voltage to the second voltage to the scan electrode in the reset period; Applying an address voltage lower than the second voltage to the scan electrode in an address period; And applying a first sustain discharge pulse voltage longer than the width of the sustain discharge pulse voltage to the scan electrode or sustain electrode in the sustain period. A fourth voltage greater than the voltage level of the sustain discharge pulse voltage is applied to the sustain electrode. At this time, the sustain discharge pulse voltage is a pulse having alternately 0 V and the sustain discharge voltage.

In this case, the sustain discharge pulse voltage may be the same voltage level as the first voltage, two or more may be applied during the first sustain discharge pulse sustain period, and the voltage level of the first sustain discharge pulse voltage is equal to the sustain discharge pulse voltage. It may be greater than the voltage level. In addition, a first sustain discharge pulse voltage may be applied to the scan electrode.

According to still another aspect of the present invention, a plasma display panel including a reset period, an address period, and a sustain period, wherein a discharge cell is formed between a scan electrode, a sustain electrode, and an address electrode, and the first electrode, during the sustain period, A plasma display device including a driving circuit for applying a sustain discharge pulse voltage to a second electrode is provided. The driving circuit applies a falling ramp voltage falling from the first voltage to the second voltage to the scan electrode in the reset period, applies a third voltage lower than the second voltage to the scan electrode in the address period, and In the sustain period, the first sustain discharge pulse voltage higher than the voltage of the sustain discharge pulse and longer than the width of the sustain discharge pulse voltage is applied to the scan electrode or the sustain electrode.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, with reference to the accompanying drawings will be described in detail to be easily carried out by those of ordinary skill in the art with respect to embodiments of the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In describing the present invention, when it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description is omitted.

4 illustrates a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address driver 300, a sustain electrode driver 400, and a scan electrode driver 500. do.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in a column direction, a plurality of sustain electrodes X1 to Xn arranged in a zigzag direction in a row direction, and a scan electrode Y1 to Yn. .

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode (X electrode) driving control signal, and a scan electrode (Y electrode) driving control signal.

The address driver 300 receives an address driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode X driving control signal from the controller 200 and applies a driving voltage to the sustain (X) electrode.

The scan electrode driver 500 receives the scan electrode Y driving control signal from the controller 200 and applies a driving voltage to the scan Y electrode.

According to the exemplary embodiment of the present invention, during the address period, the scan electrode driver 500 sequentially applies a voltage lower than the final voltage of the reset period to the plurality of scan electrodes, and applies the scan electrode of the discharge cell that is not selected to a specific voltage. Keep it. In addition, while the sustain electrode driver 400 maintains the sustain electrode at a voltage higher than the voltage applied to the sustain discharge period, the address driver 300 applies the address voltage to the address electrode of the discharge cell to be selected. Then, the sustain electrode driver 400 and the scan electrode driver 500 alternately apply sustain discharge pulses to the sustain electrode and the scan electrode during the sustain period, and the scan electrode driver 500 applies the sustain discharge pulse for a predetermined period of time. A pulse higher than and wider than the voltage of the sustain discharge pulse applied to the sustain electrode is applied to at least one sustain discharge pulse among the sustain discharge pulses. In addition, the sustain electrode driver 400 and the scan electrode driver 500 may be driven during the sustain period.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

Each of the subfields in the driving waveform according to a first embodiment of the present invention includes a reset period (P _r), an address period (P _a), and a sustain period (P _s). The reset period P _r is made up of an erase period, a rising ramp period and a falling ramp period.

The erase period of the reset period P _r is a period for erasing the electric charges formed by the sustain discharge in the sustain period P _s of the previous subfield. The rising ramp period is a period in which wall charges are formed in the scan electrode Y, the sustain electrode X, and the address electrode A, and the falling ramp period erases some of the wall charges formed in the rising lamp period to facilitate address discharge. It is a period. An address period (P _a) is a period for selecting a discharge cell to cause sustain discharge in a sustain period of the plurality of discharge cells. Sustain period (P _s) is a period for maintaining discharge in the discharge cells selected by applying a sustain pulse in turn to the scan electrode (Y) and the sustain electrode (X) during the address period (P _a).

In the plasma display panel, a scan / hold driving circuit for applying a driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods P _r , P _a , and P _s , and a driving voltage to the address electrode A, respectively. An address driving circuit for applying a is connected to form one display device.

Referring to FIG. 5, in the rising ramp period P _r2 of the reset period P _r , the voltage gradually rises from the voltage V _s toward the voltage V _set while maintaining the address electrode A and the sustain electrode X at 0V. The ramp voltage is applied to the scan electrode (Y). While this voltage rises, the first weak reset discharge occurs in each of the discharge cells from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. As a result, negative wall charges are accumulated in the scan electrode Y, and positive wall charges are accumulated in the address electrode A and the sustain electrode X at the same time.

Here, the wall charge refers to a charge that is formed on the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulates in the electrode. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

Subsequently, in the falling ramp period P _r3 , a ramp voltage that gradually falls from the V _s voltage to the -V _nf voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the voltage V _b1 . While this ramp voltage falls, the second weak reset discharge occurs again in all the discharge cells. As a result, the negative wall charges of the scan electrode Y decrease and the positive wall charges of the sustain electrode X and the address electrode A decrease.

And an address period (P _a) in the other scan electrode (Y) by a V _sch voltage applied to a state lower than the voltage -V -V _{scl nf} voltage sequentially to the scan electrode (Y) during the sustain the scan electrodes (Y) Choose. And it is applied to the address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by the V _scl voltage is applied to the scan electrode (Y). Then, the voltage applied to the address electrodes (A) (V _a) and the wall voltage due to the wall charges formed on the difference and the address electrode (A) and scan electrodes (Y) of the voltage (V _n) applied to the scan electrode (Y) This causes address discharge. In this case, according to the first exemplary embodiment of the present invention, when the scan electrode Y is applied with the V _sch voltage, the V _b2 voltage higher than the V _b1 voltage is applied to the sustain electrode X. The voltage V _b2 is higher than the voltage V _{s, and the} voltage V _b1 is lower than the voltage V _s . By doing this in the address period P _a , since a large amount of positive wall charges are formed in the address electrode A and the wall voltage is high, the magnitude of the V _a voltage can be reduced and a high efficiency plasma display panel can be obtained. To implement, it is required that the difference between the voltage applied to the scan electrode Y and the voltage applied to the address electrode is larger in the address period. In the first embodiment according to the present invention, the voltage applied to the scan electrode Y By lowering the voltage and applying a higher voltage to the sustain electrode X, a more stable address discharge occurs and a high efficiency plasma display panel can be realized.

Here, an address period (P _a) when further lowered beyond the predetermined range of voltage (-V _scl) to be applied to the scan electrode (Y) in, a problem that erroneous discharge occurs between the scan electrode (Y) and the sustain electrode (X) This happens. That is, an address period (P _a) difference (DELTA _{V = | -V scl -V nf |} ) of the voltage (V _b2) of applying a voltage (-V _scl) and the sustain electrodes to be applied to the scan electrode (Y) in the When the discharge start voltage V _f is exceeded, a discharge may occur in a place other than the discharge cell to be selected, thereby causing an erroneous discharge. Therefore, in order to properly discharge the discharge cells to be selected, the values of the voltage Ve applied to the sustain electrode X and the voltage applied to the scan electrode Y in the address period must be appropriately adjusted.

Next, in the sustain period P _s , sustain pulses (hereinafter referred to as sustain discharge pulses) are sequentially applied to the scan electrode Y and the sustain electrode X. The sustain discharge pulse is a pulse that causes the voltage difference between the scan electrode Y and the sustain electrode X to alternately become a V _s voltage and a -V _s voltage. The voltage V _{s is a} voltage lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. If the address period (P _a), the wall voltage between the scan electrode (Y) and the sustain electrode (X) by the address discharge are formed on the scan electrode by the wall voltage and V _s the voltage (Y) and the sustain electrode (X) Discharge occurs at. Hereinafter, the sustain discharge pulse voltage in the sustain period according to the first embodiment of the present invention will be described. At this time, the sustain discharge pulse voltage is divided into a first group 1G and a second group 2G.

In the first embodiment of the present invention, the first sustain discharge pulse voltage V of the first group 1G of the sustain period P _s in which the sustain discharge pulse voltage in the sustain period P _s is positioned immediately after the scan pulse. _fs ) and the sustain discharge pulse voltage (V _s ) of the second group are driven separately. At this time, the V _fs voltage is higher than the V _s voltage, and the V _fs voltage can be set within the V _s voltage and the V _smax voltage. Here, the V _smax voltage is a voltage at which misdischarge is started when the V _fs voltage is increased. In this way, the first sustain discharge is a pulse voltage of the sustain period (P _s) The first sustain discharge pulse voltage is maintained to be applied to (V _fs) to the scan electrode discharge pulse voltage (V _s) and a sustain period (P _s) higher than that of By setting the width wider than the width of the second sustain discharge pulse voltage, the period of the sustain discharge pulse can be shortened by strengthening the discharge intensity of the first sustain discharge pulse, and the width of the second sustain discharge pulse after the first group. The stable sustain discharge can be obtained even with the width of the normal sustain discharge pulse voltage.

In the first embodiment of the present invention, the first sustain discharge pulse voltage V _fs is higher than the next normal sustain discharge pulse voltage V _s in the sustain period P _s as shown in FIG. The width of the sustain discharge pulse voltage has also been changed widely, but may be different. Hereinafter, such an embodiment will be described with reference to FIG. 6.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention. The driving operation in the reset period and the address period is the same as in FIG.

In the sustain period (P _s) as shown in Fig. 6 and the sustain discharge pulse in the sustain period (P _s) comprises a first group (1G) and a second group (2G). The first group 1G includes a plurality of sustain discharge pulses in the sustain period P _s located immediately after the scan pulse. The second group 2G includes a plurality of sustain discharge pulses positioned after the first group 1G. In addition, it is assumed that the sustain discharge pulses of the second group 2G have a width and a voltage that are commonly used.

In the second embodiment according to the present invention, the first sustain discharge pulse voltage V _hs of the first group 1G is applied to a voltage higher than the normal sustain discharge pulse voltage V _s of the second group G2. The first sustain discharge pulse width of the first group 1G is set to be wider than the normal sustain discharge pulse width of the second group G2. At this time, the voltage V _hs is a voltage higher than the voltage V _s may be set in the voltage V _s and V _smax voltage. Here, the V _smax voltage is a voltage at which misdischarge is started when the V _fs voltage is increased.

The second sustain discharge pulse voltage V _hs of the first group 1G is applied in the same manner as the first sustain discharge pulse voltage V _hs of the first group 1G. At this time, the second sustain discharge pulse width of the first group 1G may be the same as or wider than the sustain discharge pulse width of the second group 1G. In addition, although the second embodiment of the present invention has been described with two sustain discharge pulses in the first group, the present invention is not limited thereto. For example, if there are five sustain discharge pulses of the first group, the voltage of the first sustain discharge pulse of the first group is applied higher than the voltage of the sustain discharge pulses of the second group, and the first sustain discharge pulse of the first group is applied. The width is made wider than the sustain discharge pulse width of the second group. And the second to fifth sustain discharge pulse voltages of the first group equal to the first sustain discharge pulse voltage, and the second to fifth sustain discharge pulse widths of the first group equal to the sustain discharge pulse widths of the second group. Or wider than that.

Thus, the first sustain discharge pulses by applying a sustain V _s the voltage a pulse voltage to the remaining sustain discharge pulses applied to its V _hs voltage than V _s the voltage is other than the first geugup (1G) of the first group (1G) By increasing the discharge intensity, the period of the sustain discharge pulse can be shortened, and wall charges can be accumulated as much as the strengthened discharge intensity to make the subsequent discharge easier. In addition, stable sustain discharge can be obtained even with the normal pulse width and the voltage of the sustain discharge pulse behind the first group.

In the first and second embodiments of the present invention, the width of the first sustain discharge pulse applied to the scan electrode is increased or the pulse voltage is increased. However, the present invention is not limited thereto. For example, the width of the sustain discharge pulse voltage may be widened or a sustain discharge pulse voltage may be applied to the sustain electrode, or the sustain discharge pulse voltage may be applied to the sustain electrode and the scan electrode. You may.

Hereinafter, the effects of the first and second embodiments of the present invention will be described in detail with reference to FIGS. 7A to 9B.

7A to 7B are graphs of actual measurement of driving voltage margins according to driving waveforms in the address periods of FIGS. 3 and 5 (or 6), respectively.

Figure 7a during the address period (P _a) as shown in FIG. 3 difference (DELTA V of the voltage (V _b2) of applying a voltage (-V _scl) and the sustain electrodes to be applied to the scan electrode (Y) in = | -V _scl - If V _nf |) is 0, it represents the driving margin actually measured. And Figure 7b in Fig. 5 or 6 address period (P _a), such as difference (DELTA V of the voltage (V _b2) of applying a voltage (-V _scl) and the sustain electrodes to be applied to the scan electrode (Y) in a = | The presence of -V _scl -V _nf |) gives the actual measured operating margin. Here, it is assumed that ㅿ V = 10. 7A and 7B, the driving voltage margin is expanded by adjusting the voltages V _scl and V _nf . That is, the address discharge generation time is shortened, and stable address discharge can be generated even at a low address voltage.

8A to 8C are graphs of actual measurement of driving voltage margins according to driving waveforms in the sustain period and the sustain period of FIGS. 3 and 5 (or FIG. 6), respectively.

Figure 8a during the address period (P _a) as shown in FIG. 3 difference (DELTA V of the voltage (V _b2) of applying a voltage (-V _scl) and the sustain electrodes to be applied to the scan electrode (Y) in = | -V _scl - When V _nf |) is 0 and the difference between the first sustain discharge pulse voltage of the sustain period P _s and the sustain discharge pulse voltage applied to the scan electrode is 0, it represents the driving voltage margin actually measured. And Figure 8b is an address period (P _a) difference (DELTA V = the voltage (V _b2) and applied to the voltage (-V _scl) and the sustain electrodes to be applied to the scan electrode (Y) in | -V -V _{scl nf} 0 is 0, and the difference between the first sustain discharge pulse voltage V _fs and the sustain discharge pulse voltage V _s applied to the scan electrode in the sustain period P _s is 10 V, which represents the actual measured driving voltage margin. . And Figure 8c is the address period (P _a) difference (DELTA V = voltage (V _b2) of applying a voltage (-V _scl) and the sustain electrodes to be applied to the scan electrode (Y) in | -V _scl -V _nf | Is 10V, and the difference between the first sustain discharge pulse voltage V _fs of the sustain period P _s and the sustain discharge pulse voltage V _s applied to the scan electrode is 20 V, the actual measured driving voltage margin.

Comparing FIGS. 8A to 8C, setting the first sustain discharge pulse voltage V _fs high in the sustain period increases the drive margin at a lower portion of the sustain discharge voltage V _s . In other words, by setting the first sustain discharge pulse potential high in the sustain period, the transition from the address discharge to the sustain discharge can be improved. Therefore, a sufficient driving voltage margin can be ensured even at the low sustain discharge pulse voltage V _s .

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the potential of the first sustain discharge pulse of the scan electrode is increased in the sustain period, and a voltage lower than the final voltage of the reset period is applied to the scan electrode of the discharge cell to be selected in the address period. In the sustain period, a voltage higher than the voltage applied to the sustain electrode may be applied to the sustain electrode to drive the plasma display panel with high efficiency.

Claims (21)

A driving method of a plasma display panel in which a voltage is applied to a scan electrode and a sustain electrode in a subfield including a reset period, an address period, and a sustain period. In the reset period, gradually decreasing a voltage of the scan electrode from a first voltage to a second voltage while applying a fourth voltage to the sustain electrode, In the address period, applying a voltage lower than the second voltage to the scan electrode while applying a fifth voltage higher than the fourth voltage to the sustain electrode; In a first period of the sustain period, applying a first sustain discharge pulse voltage having a third voltage level to the scan electrode or the sustain electrode, and In a second period of the sustain period, applying a second sustain discharge pulse voltage having a sixth voltage level less than the third voltage to the scan electrode or the sustain electrode; Method of driving a plasma display panel comprising a. The method of claim 1, And the first voltage is equal to the sixth voltage. The method of claim 1, And the fifth voltage level is greater than the sixth voltage level. The method of claim 1, And the first period includes a period during which at least two first sustain discharge pulse voltages are applied to the scan electrode or the sustain electrode. The method according to any one of claims 1 to 4, And the first sustain discharge pulse voltage is a first sustain discharge pulse voltage applied in the sustain period. The method of claim 5, And the first sustain discharge pulse voltage is applied to the scan electrode. The method of claim 6, And a width of the first sustain discharge pulse voltage is longer than a width of the second sustain discharge pulse voltage. A driving method of a plasma display panel in which a voltage is applied to a scan electrode and a sustain electrode in a subfield including a reset period, an address period, and a sustain period. In the reset period, gradually decreasing a voltage of the scan electrode from a first voltage to a second voltage while applying a third voltage to the sustain electrode, In the address period, applying a voltage lower than the second voltage to the scan electrode while applying a fourth voltage higher than the third voltage to the sustain electrode; In a first period of the sustain period, applying a first sustain discharge pulse voltage having a first width to the scan electrode or the sustain electrode, and In a second period of the sustain period, applying a second sustain discharge pulse voltage having a second width shorter than the first width to the scan electrode or the sustain electrode; Method of driving a plasma display panel comprising a. The method of claim 8, And the fourth voltage level is greater than the second sustain discharge pulse voltage level. The method of claim 9, And the first and second sustain discharge pulse voltages are at the same voltage level as the first voltage. delete The method according to any one of claims 8 to 10, And the first sustain discharge pulse voltage is a first sustain discharge pulse voltage applied in the sustain period. The method of claim 12, And the first period includes a period during which at least two first sustain discharge pulse voltages are applied to the scan electrode or the sustain electrode. The method of claim 13, And a voltage level of the first sustain discharge pulse voltage is greater than a voltage level of the second sustain discharge pulse voltage. The method of claim 14, And the first sustain discharge pulse voltage is applied to the scan electrode. A plasma display panel including a scan electrode, a sustain electrode and an address electrode, and A sub-field comprising a reset period, an address period, and a sustain period, comprising a driving circuit for applying a voltage to the scan electrode and the sustain electrode, The drive circuit, In the reset period, the voltage of the scan electrode is gradually lowered from the first voltage to the second voltage while applying a fourth voltage to the sustain electrode, In the address period, a third voltage lower than the second voltage is applied to the scan electrode while a fifth voltage higher than the fourth voltage is applied to the sustain electrode. A first sustain discharge pulse voltage having a sixth voltage level and a first width in the first period of the sustain period is applied to the scan electrode or the sustain electrode, and less than the sixth voltage level in the second period of the sustain period. And a second sustain discharge pulse voltage having a seventh voltage level and a second width shorter than the first width to the scan electrode or the sustain electrode. The method of claim 16, And the fifth voltage is higher than the first voltage. The method of claim 17, And the first voltage is at the same level as the seventh voltage level. The method of claim 18, And the first period includes a period during which at least two first sustain discharge pulse voltages are applied to the scan electrode or the sustain electrode. The method according to any one of claims 16 to 19, And the first sustain discharge pulse voltage is a first sustain discharge pulse voltage applied in the sustain period. The method of claim 20, And the first sustain discharge pulse voltage is applied to the scan electrode in the sustain period.

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