KR100589378B1 - Driving apparatus and method of plasma display panel and plasma display device - Google Patents

Abstract

In the plasma display device, a waveform rising from the first voltage to the second voltage is applied to the scan electrode while the fifth voltage is applied to the sustain electrode in the reset period, and the voltage of the scan electrode is reduced to the third voltage. Then, the waveform falling from the third voltage to the fourth voltage is applied to the scan electrode while the sixth voltage higher than the fifth voltage is applied to the sustain electrode. At this time, at least one of the difference between the first voltage and the fifth voltage or the difference between the third voltage and the fifth voltage is greater than the magnitude of the higher voltage among the voltages applied to the first electrode in the sustain period. In this way, strong discharge can be prevented in the reset period, and the reset time can be shortened.

Plasma display panel, reset period, reset waveform

Description

Driving device and driving method of plasma display panel and plasma display device {DRIVING APPARATUS AND METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a partial perspective view of a typical plasma display panel.

2 is an electrode array diagram of a general plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a circuit diagram used to apply the driving waveform shown in FIG. 5.

7 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

8 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and method for driving a plasma display panel (PDP), and a plasma display apparatus. In particular, the driving apparatus and method for a plasma display panel capable of realizing driving voltage margin expansion and stable discharge characteristics, and plasma It relates to a display device.

Recently, PDPs have been in the spotlight as flat panel display devices due to their high brightness, high luminous efficiency, and wide viewing angles, compared to other display devices.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. The plurality of address electrodes A ₁ -A _m are arranged in the vertical direction, and the plurality of scan electrodes Y ₁ -Y _n and the storage electrodes X ₁ -X _n are arranged in pairs in the horizontal direction.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and gray levels are expressed by a combination of subfields. In general, each subfield includes a reset period, an address period, and a sustain period. The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

3, the ramp-up period, the address electrode (A) and the sustain electrode is a scan electrode (Y) ramp voltage gradually rising toward the V _set voltage in V _s voltage in a holding state of (X) to 0V Is applied to. While this voltage rises, the first weak reset discharge occurs in each of the discharge cells from the scan electrode Y to the address electrode A and the sustain electrode X, respectively.

Subsequently, in the falling ramp period, a ramp voltage that gently falls from the V _s voltage to the -V _nf voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the voltage V _b1 . While this ramp voltage falls, the second weak reset discharge occurs again in all the discharge cells.

That is, in the reset period P _r , all the discharge cells are discharged by the rising ramp voltage, so that a large amount of negative charges are stored in the scan electrode Y, and a large amount of positive charges are stored in the address electrode A. Next, the ramp voltage applied to the scan electrode Y is applied to the discharge cell to maintain the wall charge structure and to lower the potential to the negative potential level V _nf . At this time, the wall charges formed in the discharge cells are erased by the rising lamp voltage.

In general, in order to implement a high-efficiency plasma display panel, the ratio of xenon (Xe) in the discharge gas is improved to increase luminous efficiency and luminance. However, as the ratio of xenon increases, the driving voltage increases, thus requiring a higher voltage difference between scan electrode Y and sustain electrode X, which can actually cause reset discharge in the reset period.

However, as the ratio of xenon increases, there is a problem in that reset discharge is not easily generated in the conventional reset waveform. Thus, there arises a problem that the reset discharge becomes unstable, thereby making it impossible to perform normal display.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and to provide a plasma display device and an apparatus and method for driving a plasma display panel to secure a driving voltage margin and prevent mis-discharge during a reset period. .

According to one aspect of the present invention, there is provided a driving method of a plasma display panel in which a discharge cell is formed between a first electrode and a second electrode and the first electrode and the second electrode. In the driving method, during the reset period, the voltage of the first electrode is gently raised from the first voltage to the second voltage while the fifth voltage is applied to the second electrode. Applying a third voltage lower than the second voltage to the first electrode while a fifth voltage is applied; and applying the sixth voltage higher than the fifth voltage to the second electrode; Gently lowering a voltage of the voltage from the third voltage to the fourth voltage, wherein at least one of the difference between the first voltage and the fifth voltage or the difference between the third voltage and the fifth voltage is a sustain period. Is greater than the magnitude of the high voltage among the voltages applied to the first electrode.

The first voltage may be higher than a high voltage among voltages applied to the first electrode in the sustain period, and the third voltage is higher than a voltage higher than the voltage applied to the first electrode in the sustain period. The voltage may be high, and the first voltage and the third voltage may be higher than the high voltage among the voltages applied to the first electrode in the sustain period.

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According to another feature of the present invention, a driving apparatus of a plasma display panel including a plurality of scan electrodes is provided. The driving device includes a first transistor connected between a first power supply for supplying a first voltage and the plurality of scan electrodes, a second power supply for supplying a second voltage lower than the first voltage, and the plurality of scan electrodes. A second transistor connected between the capacitor, a capacitor connected to a third power source having one end connected to a contact point of the first transistor and a second transistor and the other end supplied with a third voltage, and the first transistor and the second transistor A third transistor connected between a contact point and the plurality of scan electrodes, a fourth transistor connected between the third transistor and the plurality of scan electrodes, the other end of the capacitor and a contact point of the third transistor and the fourth transistor A fifth transistor coupled between the third transistor and a contact point between the third transistor and the fourth transistor and higher than the first voltage And a sixth transistor connected between the fourth power supplies for supplying the fourth voltage.

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According to still another aspect of the present invention, a plurality of first electrodes and a plurality of second electrodes formed on a first substrate, respectively, and a plurality of first electrodes and a plurality of second electrodes intersecting the first electrode and the second electrode and formed on a second substrate are provided. A plasma display panel including an address electrode, and a waveform slowly rising from a first voltage to a second voltage to the plurality of first electrodes while a fifth voltage is applied to the plurality of second electrodes in a reset period. After that, a third voltage lower than the second voltage is applied to the plurality of first electrodes, and a sixth voltage higher than the fifth voltage is applied to the plurality of second electrodes. There is provided a plasma display device including a driving circuit for applying a waveform that slowly descends from the third voltage to a fourth voltage. In this case, at least one of the difference between the first voltage and the fifth voltage or the difference between the third voltage and the fifth voltage is applied to the plurality of first electrodes and the plurality of second electrodes in a sustain period. Greater than the magnitude of the high voltage of the pulse.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, with reference to the accompanying drawings will be described in detail to be easily carried out by those of ordinary skill in the art with respect to embodiments of the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In describing the present invention, when it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description is omitted.

4 illustrates a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address driver 300, a sustain electrode driver 400, and a scan electrode driver 500. Include.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in a column direction, a plurality of sustain electrodes X1 to Xn arranged in a row direction, and a scan electrode Y1 to Yn. .

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal.

The address driver 300 receives an address drive control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode driving control signal from the controller 200 and applies a driving voltage to the sustain electrode.

The scan electrode driver 500 receives a scan electrode driving control signal from the controller 200 and applies a driving voltage to the scan electrode.

According to an exemplary embodiment of the present invention, the scan electrode driver 500 applies a waveform rising from the first voltage to the second voltage to the scan electrode during the rising ramp period and the third voltage to the scan electrode during the falling ramp period. Applies a waveform that falls to the fourth voltage at. At this time, at least one of the first voltage and the third voltage is applied higher than the sustain discharge pulse voltage in the sustain period.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

Each of the subfields in the driving waveform according to a first embodiment of the present invention includes a reset period (P _r), an address period (P _a), and a sustain period (P _s). The reset period P _r is made up of the rising ramp period P _r1 and the falling ramp period P _r2 .

The rising ramp period P _r1 of the reset period P _r is a period for forming wall charges in the scan electrode Y, the sustain electrode X, and the address electrode A, and the falling ramp period P _r2 rises. The wall charges formed in the lamp period P _r1 are partially erased to facilitate address discharge. And an address period (P _a) is a period for selecting a discharge cell to cause sustain discharge in the sustain period of the plurality of discharge cells. Sustain period (P _s) is a period for maintaining discharge in the discharge cells selected by applying a sustain pulse in turn to the scan electrode (Y) and the sustain electrode (X) during the address period (P _a).

In the plasma display panel, a scan / hold driving circuit for applying a driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods P _r , P _a , and P _s , and a driving voltage to the address electrode A, respectively. An address driving circuit for applying a is connected to form one display device.

5, in the rising ramp period P _r1 of the reset period P _r , the voltage gradually rises from the voltage V _{pr to the} voltage V _set while maintaining the address electrode A and the sustain electrode X at 0 V. The ramp voltage is applied to the scan electrode (Y). The voltage V _{pr is a} voltage higher than the level of the sustain discharge pulse voltage V _s applied to the sustain electrode X and the scan electrode Y alternately in the sustain period. In this manner, while the voltage rises, the first weak reset discharge occurs in each of the discharge cells from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. As a result, negative wall charges are accumulated in the scan electrode Y, and positive wall charges are accumulated in the address electrode A and the sustain electrode X at the same time.

On the other hand, the difference between the voltage V _pr applied to the scan electrode Y and the voltage (= 0 V) applied to the sustain electrode X in the rising ramp period P _r1 of the reset period P _r determines the discharge start voltage. If exceeded, strong discharge may occur. Therefore, the value of the voltage applied to the scan electrode Y must be appropriately adjusted.

As described above, in the first embodiment of the present invention, by applying a higher voltage V _pr to the scan electrode Y than in FIG. 3, the potential difference between the scan electrode Y and the sustain electrode X becomes larger than in the related art. The reset discharge occurs more quickly and as a result, the reset period can be shortened, and the reset discharge can be stably generated in the reset period P _r in the efficient plasma display panel.

Here, the wall charge refers to a charge that is formed on the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulates in the electrode. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

Then, applying the falling ramp period (P _r2) the sustain electrode (X) to V _b1 voltage state gradually scanning electrodes (Y) the ramp voltage falling to voltage -V _nf from voltage V _s to the sustain. While this ramp voltage falls, the second weak reset discharge occurs again in all the discharge cells. As a result, the negative wall charges of the scan electrode Y decrease and the positive wall charges of the sustain electrode X and the address electrode A decrease.

And an address period (P _a) in the other scan electrode (Y) by a V _sch voltage applied to a state lower than the voltage -V -V _{scl nf} voltage sequentially to the scan electrode (Y) during the sustain the scan electrodes (Y) Choose. And the address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by the scan electrode (Y) of the _scl -V voltage is applied. When the V _sch voltage is applied to the scan electrode Y, the V _b2 voltage higher than the V _b1 voltage is applied to the sustain electrode X.

On the other hand, an address period (P _a) of the voltage (-V _scl) and maintaining the voltage difference (V _b2) to be applied to the electrodes applied to the scan electrode (Y) in the (DELTA _{V = | -V scl -V nf |} ) is If the discharge start voltage (V _f ) is exceeded, a discharge may occur in a place other than the discharge cell to be selected, thereby causing an erroneous discharge. Therefore, in order to properly discharge the discharge cell to be selected, the values of the voltage _Ve applied to the sustain electrode X and the voltage applied to the scan electrode Y in the address period must be appropriately adjusted.

Next, in the sustain period P _s , sustain pulses (hereinafter referred to as sustain discharge pulses) are sequentially applied to the scan electrode Y and the sustain electrode X. The sustain discharge pulse is a pulse that causes the voltage difference between the scan electrode Y and the sustain electrode X to alternately become a V _s voltage and a -V _s voltage. If the address period (P _a), the wall voltage between the scan electrode (Y) and the sustain electrode (X) by the address discharge are formed on the scan electrode by the wall voltage and V _s the voltage (Y) and the sustain electrode (X) Discharge occurs at.

FIG. 6 is a diagram showing an example of a circuit diagram used to apply the drive waveform shown in FIG. 5, which is the first embodiment of the present invention. The following describes only the driving operation in the reset period according to the embodiment of the present invention. In the following, the panel capacitor Cp equivalently represents the capacitance component between the X electrode and the Y electrode.

A first terminal (i.e., the scan electrode (Y), than the scanning of the power source (V _s) and the panel capacitor (Cp), which, according to the scan electrode driver 500 according to the first embodiment of the present invention, supplying V _s voltage The transistor Ys is connected between the electrode Y), and the transistor Yg is connected between the power supply 0 for supplying the ground voltage and the scan electrode Y. A second stage of the capacitor Cset, in which a transistor Ypp is connected between a contact between two transistors Ys and Yg and a scan electrode Y, and a first end is connected to a contact between two transistors Ys and Yg. It is connected to the power supply (Vset-Vs) which supplies this (V _set -V _s ) voltage. At this time, the transistor Yg is turned on to charge the capacitor C1 with the voltage V _set -V _s . The cathode of the diode D1 is connected to the second end of the capacitor Cset, and the anode of the diode D1 is connected to the power supply Vset-Vs, and between the cathode of the diode D1 and the scan electrode Y. The transistor Yrr is connected to it. In addition, the transistor Ypr is connected between the power supply Vpr supplying the V _pr voltage and the scan electrode Y, and the transistor Yfr is provided between the power supply Vnf supplying the V _nf voltage and the scan electrode Y. It is connected. Transistor Ynp is connected between two transistors Ypr and Ynf. The diode D is connected between the transistor Vnf and the scan electrode Y.

These transistors Ys, Yg, Yrr, Ypp, Ypr, Yfr, and Ynp may be formed by connecting one or more transistors. Here, these transistors may be made of field effect transistors having body diodes, and may be made of other transistors having the same or similar functions. Such a driving circuit can generate a reset pulse stably without current backflow even when the V _pr potential is higher than the V _s potential.

The reset discharge driving circuit according to the first embodiment of the present invention thus formed operates in four modes as follows.

First, it is assumed that the capacitor Cset is charged with the voltage V _set -V _s through the same path as the mode 0 before the mode 1 starts. Such charging of the voltage can be easily performed by turning on the transistor Yg.

In mode 1, the transistors Ypr and Ynp are turned on and all other transistors are turned off. In this way, as in the first embodiment of the present invention, the voltage applied to shorten the time at which the first reset discharge occurs due to the potential difference in the reset period is applied to the scan electrode with a V _pr voltage higher than the V _s voltage in FIG. Is authorized.

In mode 2, the transistors Ys, Yrr, and Ynp are turned on and all other transistors are turned off. Then, the voltage V _s is supplied to the scan electrode Y, and the voltage C _set- V _s is charged in advance to the capacitor C1, so that the voltage at the second end of the capacitor C1 becomes V _set . The second terminal voltage V _set of the capacitor C1 is supplied to the scan electrode Y through the transistor Yrr.

In mode 3, transistors Ys, Ypp, and Ynp are turned on and all other transistors are turned off. Then, the V _s voltage is applied to the scan electrode Y.

In mode 4, only transistor Yfr is turned on. Then, a voltage _dropping from the V _s voltage to the V _nf voltage is applied to the scan electrode Y.

As described above, according to the reset driving method of the first exemplary embodiment of the present invention, the scan electrode and the sustain electrode are applied by applying a voltage V _pr higher than the voltage V _s to the scan electrode when the first reset discharge occurs in the ramp rising period. Increase the potential difference between the electrodes.

In the first embodiment of the present invention, as shown in FIG. 5, the voltage V _pr applied to the scan electrode Y in the rising ramp period P _r1 of the reset period P _r is higher than the sustain discharge pulse voltage. But you can do it differently. Hereinafter, such an embodiment will be described with reference to FIGS. 7 and 8.

7 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention. Here, the driving operation of the address period (P _a), and a sustain period (P _s) is omitted the same as in FIG.

As shown in FIG. 7, in the rising ramp period P _r1 of the reset period P _r , the address electrode A and the sustain electrode X are kept at 0 V and slowly turned toward the V _set voltage from the V _s voltage. The rising ramp voltage is applied to the scan electrode Y. Then, in the falling ramp period P _r2 of the reset period P _r , a ramp voltage gradually falling from the V _pr voltage toward the -V _nf voltage is applied to the scan electrode Y. The voltage V _pr is higher than the level of the sustain discharge pulse voltage V _s applied to the sustain electrode X and the address electrode Y alternately in the sustain period.

As described above, in the second embodiment of the present invention, reset discharge can be stably generated by applying a voltage higher than that in FIG. 3 at the start of the falling ramp voltage applied in the falling ramp period P _r2 . If the voltage suddenly drops from the V _set voltage to the V _s voltage after the rising ramp period P _r1 , strong discharge may occur at that portion. This strong discharge may cause false discharge, which may significantly reduce the display quality of the PDP. Therefore, as in the second embodiment of the present invention, by setting the V _pr voltage higher than the V _s voltage, it is possible to suppress the sudden drop in voltage and prevent strong discharge.

Hereinafter, a reset driving method according to a second embodiment of the present invention will be described with reference to FIG. 6.

The reset waveform according to the second embodiment of the present invention first assumes that the capacitor Cset is charged with the voltage V _set -V _s through the same path as the mode 0 (M0) before the mode 1 (M1) starts. do. This charging of the voltage can be easily performed by turning on the transistor Yg.

First, in mode 1, the transistors Ys, Ypp, and Ynp are turned on and all other transistors are turned off. Then, the voltage V _s is applied to the scan electrode Y.

Next, in mode 2, the transistors Ys, Yrr, and Ynp are turned on and all other transistors are turned off. Then, since the voltage V _s is supplied to the scan electrode Y, and the voltage V _set -V _s is charged in advance to the capacitor C1, the voltage at the second terminal of the capacitor C1 becomes V _set . . The voltage of the voltage V _set of the second terminal of the capacitor C1 is supplied to the scan electrode Y through the transistor Yrr.

In mode 3, the transistors Ypr and Ynp are turned on and all other transistors are turned off. In this manner is applied to the scan electrode to a high voltage V _pr than V _s of the voltage in FIG. 3 as in the second embodiment of the present invention.

In mode 4, only transistor Yfr is turned on. Then, a voltage falling to the ramp from the voltage V _{pr to the} voltage V _nf is supplied to the scan electrode Y.

8 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention. Here, the driving operation of the address period (P _a), and a sustain period (P _s) is omitted the same as in FIG.

As shown in FIG. 8, the ramp voltage gradually rising from the voltage V _{pr to the} voltage V _set while maintaining the address electrode A and the sustain electrode X during the reset period P _r is maintained at 0 V. Is applied to Y). In the falling ramp period P _r2 , a ramp voltage that gradually falls from the voltage V _{pr to the} voltage -V _{nf is} applied to the scan electrode Y. The voltage V _pr is higher than the level of the sustain discharge pulse voltage V _s applied to the sustain electrode X and the address electrode Y alternately in the sustain period. By doing this, as described above, the reset discharge occurs more quickly, and therefore, the reset time can be shortened and erroneous discharge can be prevented.

Hereinafter, a reset driving method according to a third embodiment of the present invention will be described with reference to FIG. 6.

First, it is assumed that the reset waveform according to the third embodiment of the present invention is charged with the voltage V _set -Vs to the capacitor Cset through the same path as the mode 0 M0 before the mode 1 M1 starts. . This charging of the voltage can be easily performed by turning on the transistor Yg.

First, in mode 1, the transistors Ypr and Ynp are turned on and all other transistors are turned off. In this manner is applied to the scan electrode to a high voltage V _pr than V _s of the voltage in FIG. 3 as in the second embodiment of the present invention.

Next, in mode 2, the transistors Ys, Yrr, and Ynp are turned on and all other transistors are turned off. Then, since the voltage V _s is supplied to the first terminal of the capacitor C1 and the voltage V _set -V _s is precharged to the capacitor C1, the voltage of the second terminal of the capacitor C1 is V. _{is set} . The voltage of the voltage V _set of the second terminal of the capacitor C1 is supplied to the scan electrode Y through the transistor Yrr.

In mode 3, the transistors Ypr and Ynp are turned on and all the other transistors are turned off. In this manner is applied to the scan electrode to a high voltage V _pr than V _s of the voltage in FIG. 3 as in the second embodiment of the present invention.

In mode 4, only transistor Yfr is turned on. Then, a voltage falling to the ramp from the voltage V _{pr to the} voltage V _nf is supplied to the scan electrode Y.

As described above, according to the reset driving method according to the first to third embodiments of the present invention, the driving voltage margin can be enlarged and the reset discharge is stable by increasing the potential difference between the sustain electrode and the scan electrode, the scan electrode, and the address electrode. This can be done with a short reset time.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the driving voltage margin can be expanded and stable reset discharge can be achieved in the reset period.

Claims (15)

In the driving method of the plasma display panel, the discharge cell is formed between the first electrode and the second electrode, and the first electrode and the second electrode, In the reset period, Gently raising the voltage of the first electrode from the first voltage to the second voltage while applying a fifth voltage to the second electrode; Applying a third voltage lower than the second voltage to the first electrode while applying the fifth voltage to the second electrode, and Gently lowering the voltage of the first electrode from the third voltage to a fourth voltage while applying a sixth voltage higher than the fifth voltage to the second electrode, At least one of the difference between the first voltage and the fifth voltage or the difference between the third voltage and the fifth voltage is greater than the magnitude of the higher voltage among the voltages applied to the first electrode in the sustain period. Way. The method of claim 1, And the first voltage is higher than a higher voltage among voltages applied to the first electrode in the sustain period. The method of claim 1, And the third voltage is higher than a higher voltage among voltages applied to the first electrode in the sustain period. The method of claim 1, And the first voltage and the third voltage are higher than a higher voltage among voltages applied to the first electrode in the sustain period. delete In the driving apparatus of the plasma display panel including a plurality of scan electrodes, A first transistor connected between a first power supply for supplying a first voltage and the plurality of scan electrodes, A second transistor connected between a second power supply for supplying a second voltage lower than the first voltage and the plurality of scan electrodes; A capacitor having one end connected to a contact point of the first transistor and a second transistor and the other end connected to a third power supply for supplying a third voltage; A third transistor connected between the contacts of the first and second transistors and the plurality of scan electrodes, A fourth transistor connected between the third transistor and the plurality of scan electrodes, A fifth transistor connected between the other end of the capacitor and the contacts of the third and fourth transistors, and And a sixth transistor connected between a contact point of the third transistor and a fourth transistor and a fourth power supply for supplying a fourth voltage higher than the first voltage. The method of claim 6, And the first voltage is a voltage equal to a higher voltage among voltages applied to the scan electrodes in a sustain period. The method of claim 6, And a seventh power source for supplying a voltage applied to the scan electrodes of the cells to be selected in the address period and a seventh transistor connected between the plurality of scan electrodes. The method of claim 8, A first diode connected between the third power supply and the capacitor; And And a second diode connected between the seventh transistor and the plurality of scan electrodes. The method of claim 9, And the third voltage is a voltage having the same level as a difference between the highest voltage applied to the plurality of scan electrodes and the first voltage. delete A plasma display panel including a plurality of first electrodes and a plurality of second electrodes respectively formed on a first substrate, and a plurality of address electrodes intersecting the first and second electrodes and formed on a second substrate; And In the reset period, when a fifth voltage is applied to the plurality of second electrodes, a waveform slowly rising from a first voltage to a second voltage is applied to the plurality of first electrodes, and then the When the third voltage lower than the second voltage is applied, and the sixth voltage higher than the fifth voltage is applied to the plurality of second electrodes, the third voltage to the fourth voltage is gentle to the plurality of first electrodes. It includes a driving circuit for applying a waveform that descends, At least one of the difference between the first voltage and the fifth voltage or the difference between the third voltage and the fifth voltage is applied to the sustain discharge pulses applied to the plurality of first electrodes and the plurality of second electrodes in a sustain period. Plasma display device larger than the magnitude of the high voltage. The method of claim 12, And the magnitude of the first voltage is greater than the magnitude of the high voltage of the sustain discharge pulse. The method of claim 12, And the third voltage is larger than the high voltage of the sustain discharge pulse. The method of claim 12, And the magnitudes of the first voltage and the third voltage are greater than the magnitude of the high voltage of the sustain discharge pulse.

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