KR100551037B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel and a plasma display device, wherein a voltage of a first electrode is changed from a first voltage to a second voltage in order to prevent erroneous discharge in a subfield after a large priming subfield. After lowering with an average slope, the voltage of the first electrode is lowered with a second average slope greater than the first average slope from the second voltage to the third voltage. In this case, the first and second average slopes are formed by repeating the operation of lowering the voltage of the first electrode and the operation of floating the first electrode.

In this case, a weak discharge larger than the first average slope is generated, so that a large amount of wall charges formed on each electrode can be erased, thereby preventing address erroneous discharge and shortening the reset period.

PDP, slope, reset, floating, address, mis-discharge

Description

Plasma display panel driving method and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a partial perspective view of a typical plasma display panel.

2 is an electrode array diagram of a general plasma display panel.

3 is a driving waveform diagram of a conventional plasma display panel.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

6A and 6B are diagrams illustrating a rising voltage waveform and a falling voltage waveform according to a second embodiment of the present invention.

7A and 7B are diagrams illustrating a rising voltage waveform and a falling voltage waveform according to a third embodiment of the present invention.

8 is a driving waveform diagram of a plasma display panel according to a fourth embodiment of the present invention.

The present invention relates to a method of driving a plasma display panel and a plasma display device.

Recently, PDPs have been in the spotlight as flat panel display devices due to their high brightness, high luminous efficiency, and wide viewing angles, compared to other display devices.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. The plurality of address electrodes A ₁ -A _m are arranged in the vertical direction, and the plurality of scan electrodes Y ₁ -Y _n and the storage electrodes X ₁ -X _n are arranged in pairs in the horizontal direction.

According to a general method of driving a plasma display panel, one frame is driven by being divided into a plurality of subfields, and a gray level is expressed by a combination of each subfield. Each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. That is, the reset period serves to create an optimal wall charge state for address operations in subsequent address periods. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

Next, a driving method of the conventional plasma display panel will be described with reference to FIG. 3.

3 is a driving waveform diagram of a conventional plasma display panel.

Referring to Fig. 3, the reset period consists of the erasing period, the ramp up period and the ramp down period.

In the erase period, an erase ramp waveform gradually rising toward the voltage V _e at 0 V is applied to the sustain electrode X. Then, the wall charges formed on the sustain electrode X and the scan electrode Y are gradually erased.

Next, in the rising ramp period, the address electrode A and the sustain electrode X are held at 0 V, and a ramp waveform gradually rising from the V _s voltage to the V _set voltage is applied to the scan electrode Y. While this ramp waveform is rising, a weak reset discharge occurs in each of the discharge cells from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. As a result, negative wall charges are accumulated in the scan electrode Y, and positive wall charges are accumulated in the address electrode A and the sustain electrode X at the same time.

Subsequently, in the falling ramp period, while the sustain electrode X is held at the voltage V _e , a ramp waveform that gradually falls toward 0 V _{at the} voltage V _{s is} applied to the scan electrode Y. While this ramp waveform is falling, again weak discharge discharge occurs in all the discharge cells. As a result, the negative wall charge of the scan electrode Y decreases and the positive wall charge of the sustain electrode X decreases.

However, if a reset waveform as shown in FIG. 3 is applied to a subfield in which a large amount of priming occurs due to sustain discharge in the sustain period, that is, a subfield after a high weight subfield, false discharge may occur even in a cell not selected in the address period. . Therefore, in this case, a certain amount of wall charges must be erased in the reset period. However, the wall charge cancellation amount in the falling ramp waveform is determined by the final voltage of the falling ramp waveform if the slope of the falling ramp waveform is constant. Therefore, in order to erase a certain amount of wall charges, the final voltage of the falling ramp waveform must be lowered, so the falling ramp period becomes longer.

In particular, in the case where the weight of the immediately preceding subfield is high, there are many priming particles, which increases the possibility of mis-discharge in the address period. Therefore, in this case, the falling ramp period becomes longer because more wall charges must be erased in the reset period.

In addition, for a stable erasing operation in the falling ramp period, it is necessary to form a certain amount of wall charges in the rising ramp period. The amount of wall charge formation in the rising ramp waveform is determined by the final voltage of the rising ramp waveform if the slope of the rising ramp waveform is constant. Therefore, in order to form a certain amount of wall charge, the final voltage of the rising ramp waveform needs to be high, thereby increasing the rising ramp period.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and to provide a plasma display panel driving method and a plasma display device capable of preventing address mis-discharge and shortening reset time.

According to one aspect of the present invention, a method of driving a plasma display panel in which discharge cells are formed by a first electrode, a second electrode, and a third electrode is provided.

The driving method includes, in a reset period, a) lowering a voltage of the first electrode with a first average slope from a first voltage to a second voltage, and b) lowering a voltage of the first electrode to the second voltage. And descending with a second average slope greater than the first average slope to a third voltage. And lowering the voltage of the first electrode with a third average slope greater than the first average slope from the fourth voltage higher than the first voltage to the first voltage.

In this case, the first and second average slopes may be formed by repeatedly lowering the voltage of the first electrode and floating the first electrode. The first and second average slopes may be different by adjusting the width of the falling voltage, and the first and second average slopes may be different by adjusting the floating period.

According to another feature of the invention, the driving method comprises, in a reset period: a) raising the voltage of the first electrode with a first average slope from a first voltage to a second voltage, and b) the first Increasing the voltage of the electrode from the second voltage to a third voltage with a second average slope greater than the first average slope. The method may further include increasing the voltage of the first electrode with a third average slope greater than the first average slope from the fourth voltage lower than the first voltage to the first voltage.

According to still another aspect of the present invention, a plasma display panel in which a discharge cell is formed between a first electrode, a second electrode, and a third electrode, and the first electrode, the second electrode, and A drive circuit for applying a drive voltage to the third electrode is provided. The driving circuit, in the reset period, raises the voltage of the first electrode with a first average slope from the first voltage to the second voltage during the first period, and raises the voltage of the first electrode from the second voltage. Raise the second average slope up to three voltages with the second average slope greater than the first average slope; during the second period, the voltage of the first electrode is dropped with the third average slope from the fourth voltage to the fifth voltage and the first The voltage of the electrode is lowered from the fifth voltage to the sixth voltage with a fourth average slope greater than the third average slope.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, with reference to the accompanying drawings will be described in detail to be easily carried out by those of ordinary skill in the art with respect to embodiments of the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In describing the present invention, when it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description is omitted. In addition, the same code | symbol is attached | subjected about the similar part throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also a case where another part is connected in between.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, a plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. Include.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in a column direction, a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn arranged in pairs in a row direction. do.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield is represented by a reset period, an address period, and a sustain period.

The address electrode driver 300 receives an address electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives a scan electrode driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

The present invention provides a method of driving a plasma display panel in which the inclination of the rising ramp waveform and the falling ramp waveform applied to the scan electrode (Y) in the reset period is adjusted to adjust the degree of formation of the wall voltage.

Hereinafter, a driving method of the plasma display panel according to the first embodiment of the present invention will be described in detail with reference to FIG. 5. In the following, it is assumed that the reference voltage is 0 V, and the description of the address period and the sustain period is omitted, and only the reset period is described. The wall charges are charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

As it is shown in Figure 5, and each of the subfields in the driving waveform of the plasma display panel according to a first embodiment of the present invention includes a reset period (P _r), an address period (P _a), and a sustain period (P _s) The reset period P _r includes the erase period P _r1 , the rising ramp period P _r2 , and the falling ramp period P _r3 .

The erase period P _r1 of the reset period P _r is a period for erasing electric charges formed by sustain discharge in the sustain period P _s of the previous subfield. The rising ramp period P _r2 is a period for forming wall charges in the scan electrode Y, the sustain electrode X, and the address electrode A, and the falling ramp period P _r3 is in the rising ramp period P _r2 . This is a period in which the formed wall charges are partially erased to facilitate address discharge. And an address period (P _a) is a period for selecting a discharge cell to cause sustain discharge in the sustain period among the plurality of discharge cells. Sustain period (P _s) is a period for maintaining discharge in the discharge cells selected by applying a sustain pulse in turn to the scan electrode (Y) and the sustain electrode (X) during the address period (P _a).

In the plasma display panel, a scan / hold driving circuit for applying a driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods P _r , P _a , and P _s , and a driving voltage to the address electrode A, respectively. An address driving circuit for applying a is connected to form one display device.

In general, after the last sustain discharge in the sustain period P _s , a positive wall charge and a negative wall charge are formed on the sustain electrode X and the scan electrode Y, respectively. Therefore, in the erase period P _r1 of the reset period P _r , the voltage V _e at the reference voltage is applied to the sustain electrode X while the scan electrode Y is held at the reference voltage after the sustain period P _s is over. Apply a ramp waveform that rises to. The wall charges formed on the sustain electrode X and the scan electrode Y are then erased.

Next, in the rising ramp period P _r2 of the reset period P _r , V _{at the} voltage V _s at the scan electrode Y while maintaining the address electrode A and the sustain electrode X at the reference voltage (0 V). A rising voltage waveform that rises toward the _set voltage is applied. During this voltage waveform rise, reset discharge occurs in all discharge cells, negative wall charges are formed on the scan electrode Y, and positive wall charges are formed on the sustain electrode X and the address electrode A. .

Subsequently, in the falling ramp period P _r3 of the reset period P _r , the falling voltage waveform falls toward the reference voltage from the V _s voltage to the scan electrode Y while the sustain electrode X is maintained at the V _e voltage. Is applied. While this voltage waveform falls, reset discharge occurs in all the discharge cells again, the negative wall charge of the scan electrode Y decreases, and the positive wall charge of the sustain electrode X and the address electrode A decreases. .

As shown in FIG. 5, the falling ramp period P _r3 according to the first embodiment of the present invention includes a first period P _r31 and a second period P _r32 .

In the first period P _r31 , a falling voltage waveform having a slope D1 is applied to adjust the overall stable wall charge. Then, in the second period P _r32 , a falling voltage waveform having a slope D2 is applied to generate a weaker discharge more than the first period P _r31 , thereby eliminating more wall charges. At this time, the slope D1 is smaller than the slope D2.

In this manner, in the first period P _r31 corresponding to the beginning of the falling ramp period P _r3 , the voltage of the scan electrode Y is lowered with a gentle slope D1 to adjust the overall stable wall charge. In the second period P _r32 of the falling ramp period P _r3 , when the voltage of the scan electrode Y is lowered with a steep slope D2, the second period P _r32 is the first period P. The intensity of the discharge is stronger than that of _r31 ), and as a result, more wall charges can be erased. Therefore, the falling ramp period P _r3 can be shortened, and when the wall charges are excessively formed in the high-weight subfield and address mis-discharge can occur in the address period of the subfield after the high-weight subfield, It is possible to prevent erroneous discharge.

In the falling ramp period P _r3 , the inclination of the second half portion is sharply applied, but the same applies to the rising ramp period P _r2 as shown in FIG. 5.

As shown in FIG. 5, the rising ramp period P _r2 includes a first period P _r21 and a second period P _r22 .

In the first period P _r21 , a rising voltage waveform having a slope C1 is applied to adjust the overall stable wall charge. Then, in the second period P _r22 , a rising voltage waveform having a slope C2 is applied to generate a larger weak discharge than the first period P _r21 to form a larger amount of wall charge. At this time, the slope C1 is smaller than the slope C2.

In this manner, in the first period P _r21 corresponding to the beginning of the rising ramp period P _r2 , the voltage of the scan electrode Y is raised with a gentle slope C1 to adjust the overall stable wall charge. In the second period P _r22 corresponding to the second half of the rising ramp period P _r2 , if the voltage of the scan electrode Y is increased with the steep slope D2, the second period P _r22 is set to _zero . The intensity of the discharge becomes stronger than in one period P _r21 , and as a result, more wall charges can be formed. Therefore, the V _set voltage can be lowered, and the rising ramp period P _r2 can be shortened.

And 5, the ramp-up period (P _r2) and the ramp-down period, a second period (P _r22, P _r32) slope the slope steep the voltage of the scan electrode (Y) in corresponding to the second half of the (P _r3) (C2, D2) with the rising (or falling) but may also be applied only in the rising ramp period (P _r2 ) or falling ramp period (P _r3 ).

As in the first embodiment of the present invention, in order to raise (or lower) the voltage of the scan electrode Y with two slopes during the rising ramp period P _r2 (or falling ramp period P _r3 ), Two lamp switches shall be used. However, there is a way to control two tilts with one driver. Hereinafter, such an embodiment will be described in detail with reference to FIGS. 6A and 6B.

6A is a diagram illustrating a rising voltage waveform according to a second embodiment of the present invention, and FIG. 6B is a diagram showing a falling voltage waveform according to a second embodiment of the present invention.

6A and 6B, the rising ramp waveform (or falling ramp waveform) applied in the reset period increases (or decreases) the voltage applied to the scan electrode Y by a predetermined amount, and then scan electrode Y for a predetermined period. )). The voltage of the scan electrode Y is increased (or decreased) by a predetermined amount and the floating operation of the scan electrode Y for a predetermined period is repeated.

If the voltage difference between the voltage of the sustain electrode X and the voltage of the scan electrode Y becomes equal to or greater than the discharge start voltage while repeating this operation, a discharge occurs between the sustain electrode X and the scan electrode Y. When the scan electrode Y is in a floating state after the discharge is started between the sustain electrode X and the scan electrode Y, since there is no charge flowing from the external power source, the voltage of the scan electrode Y is determined by the amount of wall charge. Will change accordingly. Therefore, the amount of change in the wall charge immediately decreases the voltage inside the discharge space (discharge cell), and the discharge disappears even with a small change in the wall charge.

Specifically, when the discharge occurs due to the voltage rise of the scan electrode Y in the rising ramp period, a negative wall charge is formed on the scan electrode Y, and the voltage in the discharge space rapidly decreases, resulting in a strong discharge inside the discharge space. Extinction occurs. Then, when the voltage of the scan electrode Y is increased again to form a discharge, and then the scan electrode Y is floated again, negative wall charges are formed on the scan electrode Y as before, and at the same time, the discharge space is formed. Strong discharge disappears inside.

When the discharge occurs due to the decrease in the voltage of the scan electrode Y, the wall charges formed in the sustain electrode X and the scan electrode Y decrease, and the voltage in the discharge space rapidly decreases, resulting in a strong discharge in the discharge space. Extinction occurs. Then, when the voltage of the scan electrode Y is again reduced to form a discharge, and then the scan electrode Y is floated, the wall charge decreases as in the previous step, and strong discharge disappears inside the discharge space.

When the operation of increasing (or decreasing) the scan electrode Y voltage and floating the scan electrode Y is repeated a predetermined number of times in the rising ramp period or the falling ramp period, the sustain electrode X and the scan electrode Y are repeated. The desired amount of wall charge is formed in.

Each slope of the rising voltage waveform (or falling voltage waveform) can be controlled by adjusting the width or floating period of the rising voltage (or falling voltage) applied to the scan electrode (Y).

First, as shown in FIG. 6A, during the rising ramp period P _r2 , the width of the voltage applied to the scan electrode Y is set to be equal, and in the rising ramp period P _r2 , the first period P _r21 has the same width. The floating period Δt1 is set long and the floating period Δt2 of the second period P _r22 is set short. Then, the slope C2 in the second period P _r22 may be formed more sharply than the slope C1 in the first period. By adjusting the floating period in this way, it is possible to control the slope of the rising voltage waveform.

And as in Figure in Figure 6b 6a, and hold the floating period (Δt3) of the ramp-down period (P _r3) the first period (P _r31) from the set equal to the width of the lowered voltage to the ramp-down period (P _r3) for And the floating period Δt4 of the second period P _r32 is shortened. Then, the inclination D2 in the second period P _r32 may be formed more sharply than the inclination D1 in the first period P _r31 . By adjusting the floating period in this way, it is possible to control the slope of the falling voltage waveform.

6A and 6B, the inclination of the rising voltage waveform (or falling voltage waveform) is controlled by adjusting the floating period, but may be different. Hereinafter, such an embodiment will be described in detail with reference to FIGS. 7A to 7B.

7A is a diagram illustrating a rising voltage waveform according to a third embodiment of the present invention, and FIG. 7B is a diagram showing a falling voltage waveform according to a third embodiment of the present invention.

First, as shown in Figure 7a, the ramp period (P _r2) set equal to a shorter width (ΔV1) of the threshold voltage of the first period (P _r21) in a ramp period (P _r2) set the floating period during The width ΔV2 of the rising voltage in the second period P _r22 is set longer. Then, the slope C2 in the second period P _r22 may be formed more sharply than the slope C1 in the first period. By adjusting the width of the rising voltage in this way, it is possible to control the slope of the rising voltage waveform.

And as shown in Figure 7b, the ramp-down period (P _r3) set equal to the floating period during and set a shorter width (ΔV3) of the falling voltage of the first period (P _r31) from the ramp-down period (P _r3) and The width ΔV4 of the falling voltage in the second period P _r32 is set longer. Then, the slope D2 in the second period P _r32 may be formed more rapidly than the slope D1 in the first period P _r31 . By adjusting the width of the falling voltage in this way, it is possible to control the slope of the falling voltage waveform.

In the first, second, and third embodiments of the present invention, the slope of the rising voltage waveform (or falling voltage waveform) is described as an example, but the slope of the rising voltage waveform (or falling voltage waveform) may be set more. have. Hereinafter, this embodiment will be described with reference to FIG. 8.

8 is a driving waveform diagram of a plasma display panel according to a fourth embodiment of the present invention.

As shown in FIG. 8, the voltage of the scan electrode Y in the first period P _r21 (or the first period P _r31 ) of the rising ramp period P _r2 (or the falling ramp period P _r3 ). It is the same as in the first embodiment of the present invention except that is raised (or lowered) with two slopes.

In the first period P _r21 of the rising ramp period P _r2 , the rising voltage waveform having the slope C1 ′ is applied to the scan electrode Y and then the slope C1 ′ is applied to the scan electrode Y. Apply a rising voltage waveform. At this time, the slope C1 'is formed more rapidly than the slope C1', and the slope C1 'is formed more gently than the slope C1 shown in FIG. In general, the scan electrode in the early (a) of the initial (a) a first period (P _r21) of the ramp-up period (P _r2) discharge does not occur in the first period (P _r21) of the ramp-up period (P _r2) If the voltage of (Y) is raised rapidly, the reset time can be shortened.

Subsequently, in the first period P _r31 of the falling ramp period P _r3 , the falling voltage waveform having the slope D1 ′ is applied to the scan electrode Y, and then the slope D1 s is applied to the scan electrode Y. Apply a falling voltage waveform with At this time, the slope D1 'is formed more sharply than the slope D1', and the slope D1 'is formed more gently than the slope D1 shown in FIG. Increase the first period (P _r31) of the initial (b) the ramp-down period (P _r3) DO discharge does not occur in the first period (P _r31) of the ramp period (P _r2) the ramp-down period (P _r3) as in If the voltage of the scan electrode Y is sharply lowered at the initial stage of b, the reset time can be shortened.

In FIG. 8, the slope of the rising voltage waveform (or falling voltage waveform) applied to the scan electrode Y in the first period of the rising ramp period P _r2 (or falling ramp period P _r3 ) is as described above. It can be controlled by adjusting the floating period or adjusting the width of the rising voltage (or falling voltage).

In addition, in the first to fourth embodiments of the present invention, during the rising ramp period P _r2 (or the falling ramp period P _r3 ), the voltage of the scan electrode Y rises with two or three slopes (or You can use three or more slopes, or divide them into groups and use different slopes for each group. At this time, in the rising ramp period P _r2 (or falling ramp period P _r3 ), when the voltage of the scan electrode Y is increased (or decreased) with one or more slopes, the last rising voltage waveform ( Alternatively, the inclination of the falling voltage waveform is made higher than the inclination of the rising voltage waveform (or falling voltage waveform) applied immediately before, so that a large amount of wall charges can be formed (or erased). Similarly, the rising ramp period (P _r2) (or ramp-down period (P _r3)) the rising ramp period (P _r2), even when using a different slope for each group divided into a plurality of groups (or ramp-down period (P _r3) The slope of the last group applied at the end of) is sharper than the slope of the previous group so that a large amount of wall charges can be formed (or erased).

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the reset time can be shortened, and in the rising ramp period of the reset period, a large number of wall charges can be formed, thereby lowering the V _set voltage applied to the rising ramp period, and the reset period. In the falling ramp period, a large number of wall charges can be erased, thereby preventing address mis-discharge that may occur after a high-weight subfield or a subprime formed subfield.

Claims (14)

A method of driving a plasma display panel in which discharge cells are formed by a first electrode, a second electrode, and a third electrode, In the reset period, Lowering the voltage of the first electrode with a first average slope from a first voltage to a second voltage, and Lowering the voltage of the first electrode with a second average slope greater than the first average slope from the second voltage to a third voltage Including; And the first and second average slopes are formed by repeating the operation of lowering the voltage of the first electrode and the floating of the first electrode. delete The method of claim 1, And controlling the width of the falling voltage to form the first and second average slopes. The method of claim 1, And controlling the floating period to form the first and second average slopes. The method according to any one of claims 1, 3 or 4, Lowering the voltage of the first electrode with a third average slope greater than a first average slope from a fourth voltage higher than the first voltage to the first voltage The driving method of the plasma display panel further comprising. A method of driving a plasma display panel in which discharge cells are formed by a first electrode, a second electrode, and a third electrode, In the reset period, Raising the voltage of the first electrode with a first average slope from a first voltage to a second voltage, and Raising the voltage of the first electrode with a second average slope greater than the first average slope from the second voltage to a third voltage Including; And the first and second average slopes are formed by repeatedly increasing the voltage of the first electrode and floating the first electrode. delete The method of claim 6, And controlling the width of the rising voltage to form the first and second average slopes. The method of claim 6, And controlling the floating period to form the first and second average slopes. The method according to any one of claims 6, 8 or 9, Raising the voltage of the first electrode with a third average slope greater than a first average slope from a fourth voltage lower than the first voltage to the first voltage The driving method of the plasma display panel further comprising. A plasma display panel in which discharge cells are formed between the first electrode, the second electrode, and the third electrode; and A driving circuit for applying a driving voltage to the first electrode, the second electrode, and the third electrode during a reset period, an address period, and a sustain period, The drive circuit, In the reset period, Raising the voltage of the first electrode with a first average slope from the first voltage to the second voltage and then raising the voltage from the second voltage to the third voltage with a second average slope greater than the first average slope, The voltage of the first electrode is lowered from the fourth voltage to the fifth voltage with a third average slope, and then the voltage of the first electrode is lowered from the fifth voltage to the sixth voltage with a fourth average slope greater than the third average slope; The first to fourth average slopes are formed by repeatedly changing the voltage of the first electrode and floating the first electrode. The method of claim 11, And the driving circuit raises the voltage of the first electrode with a fifth average slope greater than a first average slope from the seventh voltage lower than the first voltage to the first voltage. The method of claim 11, And the driving circuit lowers the voltage of the first electrode with a sixth average slope greater than a third average slope from an eighth voltage higher than the fourth voltage to the fourth voltage. delete

Images