KR100521483B1 - Driving method of plasma display panel - Google Patents

Abstract

The driving method of the plasma display panel according to the present invention applies an erase waveform for erasing the wall voltage between the first electrode and the second electrode after the sustain period when the plasma display panel is powered off. Then, low discharge does not occur when the plasma display panel is powered on.

Description

Driving Method of Plasma Display Panel {{DRIVING METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel (PDP) and a plasma display device.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

In such an AC plasma display panel, scan electrodes and sustain electrodes parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

1 is a partial perspective view of a typical AC plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 4 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

2 shows an electrode arrangement diagram of a plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix form of n × m. Specifically, the address electrodes A ₁ to A _m extend in the column direction and the scan electrode Y in the row direction. _{1 to} Y _n and the sustain electrodes X _{1 to} X _n extend. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

In general, according to the driving method of the plasma display panel, an image is displayed on the plasma display panel by driving one frame into a plurality of subfields. Each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cell.

On the other hand, when the off signal is input to the plasma display panel, one subfield having a reset period, an address period, and a sustain period is driven once more. That is, when a power-off signal of the plasma display panel is input while one subfield is driven, all the subfields are driven, and then a reset period is performed again, and a voltage corresponding to black data is applied to the address electrode in the address period. Is applied to turn off the plasma display panel. At this time, the black data applied to the address electrode is as if no voltage is applied to the address electrode because the gray level is zero. Therefore, no image is displayed in the sustain period because not all discharge cells are selected in the address period. In this way, it was possible to prevent screen glare generated during the off operation of the plasma display panel.

However, when the plasma display panel is turned off in this way, since a large amount of wall charges are already formed in the discharge cells emitting in the sustain period of the previous subfield by the sustain discharge, the reset operation is performed to initialize all the cells. Since the wall charge state formed in the reset period of the previous subfield is not changed in the discharge cells that do not emit light in the sustain period of, the reset operation is not performed again in the next subfield. In such a state, the wall charges may change between cells over time, and may be neutralized or dissipated to change the wall charge states of the cells. When the plasma display panel is turned off by inserting black data in the address period in a state where the wall charge states between the cells are different from each other, the state of the wall charges in the cell is not defined properly when the plasma display panel is turned on. Discharge may occur. Low discharge in the plasma display panel means that the discharge is not maintained normally. This low discharge is caused by the address discharge in the address period due to the lack of priming particles in the cell or the wall charge structure which is not controlled by the reset period. It happens because it is not done properly.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve such a conventional problem, and to provide a method of driving a plasma display panel capable of preventing low discharge when the panel is in an off state and the panel is turned on. will be.

To solve this problem, in the present invention, when the power signal of the plasma display panel is applied, the erase waveform is placed after the sustain period of the corresponding subfield.

According to one aspect of the present invention, there is provided a method of driving a plasma display panel including a reset period, an address period, and a sustain period, wherein a discharge cell is formed by a first electrode, a second electrode, and a third electrode. The driving method applies an erase waveform for erasing the wall voltage between the first electrode and the second electrode after the sustain period when the plasma display panel is powered off.

The erase waveform may be a waveform for gradually increasing a voltage difference between the first electrode and the second electrode from a first voltage to a second voltage, wherein the erase waveform may include the first waveform for sustain discharge in the sustain period. It may be a pulse having a first voltage for a period narrower than the width of the sustain discharge pulse applied to one electrode. The erase waveform may be a pulse having a first voltage for a period longer than a width of a sustain discharge pulse applied to the first electrode for sustain discharge in the sustain period.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. In addition, the wall charges mentioned below refer to charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed on the wall of the discharge cell by the wall charge.

Hereinafter, a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address driver 300, a sustain electrode driver 400, and a scan electrode driver 500. do.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, a plurality of sustain electrodes X1 to Xn arranged in the row direction, and scan electrodes Y1 to Yn.

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode X driving control signal, and a scan electrode Y driving control signal. The controller 200 divides and drives one frame into a plurality of subfields to display an actual image, and each subfield includes a reset period, an address period, and a sustain period.

According to an embodiment of the present disclosure, when the off signal of the plasma display panel is input from the outside, the controller 200 may include an address driving control signal, a sustain electrode X driving control signal, and a scan electrode Y for outputting an erase driving waveform. Output the drive control signal.

The address driver 300 receives an address driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode X driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives the scan electrode Y driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

4 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention. 4 is a driving waveform diagram in the normal operation of the plasma display panel, in which one frame is driven by being divided into a plurality of subfields, each of which includes a reset period, an address period, and a sustain period. And the reset period includes a rising period and a falling period.

The rising period of the reset period is a period during which the wall charges are formed in the scan electrode Y, the sustain electrode X, and the address electrode A. The falling period of the reset period partially erases the wall charges formed in the rising period and discharges the address. To facilitate the period. The address period is a period for selecting a discharge cell to cause sustain discharge in the sustain period among the plurality of discharge cells, and the sustain period is a discharge selected in the address period by applying sustain pulses to the scan electrode Y and the sustain electrode X in order. It is the period of sustain discharge of the cell.

The plasma display panel is connected with a scan / hold driving circuit for applying a driving voltage to the scan electrode Y and the sustain electrode Y and an address driving circuit for applying a driving voltage to the address electrode A in each period. Achieves the display device.

4, in the rising period of the reset period, the address electrode A and the sustain electrode X are held at 0 V, and the voltage of the scan electrode Y is gradually increased from the V _s voltage to the V _set voltage. While the voltage of the scan electrode Y increases, weak reset discharges occur from the scan electrode Y to the address electrode A and the sustain electrode X, respectively, in all the discharge cells. As a result, negative wall charges are formed on the scan electrode Y, and positive wall charges are formed on the address electrode A and the sustain electrode X at the same time.

In the falling period of the reset period, while the sustain electrode X is maintained at the constant voltage V _{e, the} voltage of the scan electrode Y is gradually lowered from the voltage V _s toward the voltage V _nf . Then, while the voltage of the scan electrode Y drops, reset discharge occurs again in all the discharge cells, the negative wall charge of the scan electrode Y decreases, and the (+) of the sustain electrode X and the address electrode A decrease. The wall charge is reduced. In general, in the falling period, the final applied voltage _{Ve e} -V _nf between the scan electrode Y and the sustain electrode X is applied to the sustain start voltage by the discharge start voltage between the sustain electrode X and the scan electrode Y. The wall voltage between (X) and scan electrode Y is set to approximately 0V.

In the address period, while the sustain electrode X and the other scan electrode Y are maintained at the V _e voltage and the V _scH voltage, V _scL voltage is sequentially applied to the scan electrode Y to scan _cell Y. Choose. And it applies an address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by the V _scL voltage is applied to the scan electrode (Y). Then, the voltage applied to the address electrodes (A) (V _a) and the wall voltage due to the wall charges formed on the difference and the address electrode (A) and scan electrodes (Y) of the voltage (V _scL) applied to the scan electrode (Y) This causes address discharge between the address electrode A and the scan electrode Y, and between the sustain electrode X and the scan electrode Y. As a result, (+) wall charges are formed on the scan electrode (Y) and (-) wall charges are formed on the sustain electrode (X).

Next, in the sustain period, sustain pulses are sequentially applied to the scan electrode Y and the sustain electrode X. FIG. The sustain pulse is a pulse that causes the voltage difference between the scan electrode Y and the sustain electrode X to alternately become a V _s voltage and a -V _s voltage. The voltage V _{s is a} voltage lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. When the wall voltage is formed between the scan electrode Y and the sustain electrode X by the address discharge in the address period, the discharge occurs at the scan electrode Y and the sustain electrode X by the wall voltage and the V _s voltage. .

After the last sustain discharge ends, it starts from the reset period of the next subfield. The reset period, the address period and the sustain period are made the same as described above. However, each subfield corresponding to the weighting for the process of applying a sustain pulse of V _s voltage to the course and the sustain electrode (X) for applying a sustain pulse V _s voltage to the scan electrode (Y) show the corresponding subfield The number of times is repeated to show the actual luminance.

In this manner, the plasma display panel displays an image while performing the reset period, the address period, and the sustain period in each subfield according to the input image signal. When the off signal of the plasma display panel is applied from the outside, all the wall charges of the discharge cells are erased after the sustain period of the corresponding subfield.

Hereinafter, driving waveforms of the plasma display panel operated when the OFF signal is applied to the plasma display panel from the outside will be described in detail with reference to FIGS. 5 and 6 to 9.

FIG. 5 is a diagram illustrating a wall charge state formed in each electrode after the sustain period is finished, and FIGS. 6 and 7 are driving waveform diagrams of the plasma display panel according to the first and second embodiments of the present invention, respectively.

In general, after the last sustain discharge in the sustain period, the positive (+) wall charge and the negative (-) wall charge are formed on the sustain electrode (X) and the scan electrode (Y) as shown in FIG.

First, as shown in FIG. 6, the plasma display panel performs a normal operation as shown in FIG. 4, but when the off signal is applied, the plasma display panel performs the erase period after the sustain period of the corresponding subfield.

In general, after the last sustain discharge in the sustain period, the positive (+) wall charge and the negative (-) wall charge are formed on the sustain electrode (X) and the scan electrode (Y) as shown in FIG. Therefore, in the erase period according to the first exemplary embodiment of the present invention, the voltage of the sustain electrode X is maintained at the reference voltage (V _e -V _nf ) while the scan electrode Y is maintained at the reference voltage after the sustain period ends. Raise to voltage. Then, discharge occurs in all the discharge cells while the voltage of the sustain electrode X increases, the negative wall charge of the scan electrode Y decreases, and the positive wall charge of the sustain electrode X and the address electrode A is reduced. Decreases. At this time, when the final applied voltage _{Ve e} -V _nf between the scan electrode Y and the sustain electrode X becomes the discharge start voltage V _fxy between the scan electrode Y and the sustain electrode X, the sustain voltage is maintained. The wall charges formed on the electrode X and the scan electrode Y are erased so that the wall voltage between the sustain electrode X and the scan electrode Y becomes 0V.

In FIG. 6, the voltage of the sustain electrode X is increased to the (V _e -V _nf ) voltage. However, unlike the sustain electrode in the state in which the last sustain pulse is applied as in the second embodiment of the present invention illustrated in FIG. (X) may be biased to the V _e voltage and the voltage of the scan electrode Y may be gradually lowered to the V _nf voltage. Then, as described above in the falling period of the reset period, discharge occurs in all the discharge cells while the voltage of the scan electrode Y is falling, and the negative wall formed on the scan electrode Y and the sustain electrode X is caused by this discharge. The charge and the positive wall charge are erased. When the final applied voltage V _e -V _nf between the scan electrode Y and the sustain electrode X becomes the discharge start voltage V _fxy between the scan electrode Y and the sustain electrode X, the sustain electrode ( The wall charges formed in X) and scan electrode Y are erased so that the wall voltage between sustain electrode X and scan electrode Y becomes 0V.

In FIGS. 6 and 7, the voltage of the scan electrode Y is gradually changed (increased or decreased) to erase the wall charges formed in each electrode. However, the wall charges may be erased in a different form. Hereinafter, such an embodiment will be described in detail with reference to FIGS. 8 and 9.

8 and 9 are driving waveform diagrams of the plasma display panel according to the third and fourth embodiments of the present invention, respectively.

Referring to FIG. 8, in the driving waveform according to the third embodiment of the present invention, the wall charges between the sustain electrode X and the scan electrode Y are erased by narrow pulses. Here, the narrow pulse refers to a pulse having a voltage substantially similar to that of the sustain discharge pulse applied in the sustain period and a narrower width than the sustain discharge pulse.

Specifically, in the state where the voltage V _s is applied to the scan electrode Y in the sustain period and the cell is as shown in FIG. 5, the reference voltage is applied to the scan electrode Y and the voltage V _s is applied to the sustain electrode X. Apply a narrow pulse. Then, discharge occurs between the scan electrode Y and the sustain electrode X by the wall voltage and V _s voltage formed between the scan electrode Y and the sustain electrode X, and the V _s voltage is removed before the discharge is completed. do. Then, since the wall charges formed on the scan electrode Y and the sustain electrode X are involved in the discharge, the V _s voltage is removed before the reverse polarity charges are accumulated on the scan electrode Y and the sustain electrode X. The wall charges formed on the Y) and the sustain electrode X can be removed.

9, in the driving waveform according to the fourth embodiment of the present invention, the wall charge between the scan electrode Y and the sustain electrode X is erased by a wide pulse. Here, the wide pulse refers to a pulse having a lower voltage than the sustain pulse applied in the sustain period and a wider width than the sustain pulse. However, the voltage of the wide pulse is a voltage which can cause discharge along with the wall voltage.

Specifically, in the state where the V _s voltage is applied to the scan electrode Y in the sustain period and the cell is as shown in FIG. 5, the reference voltage is applied to the scan electrode Y and lower than the V _s voltage to the sustain electrode X. A narrow pulse having a voltage V _s1 is applied. Then, discharge occurs between the scan electrode Y and the sustain electrode X by the wall voltage and V _s1 voltage formed between the scan electrode Y and the sustain electrode X. At this time, unlike the general sustain discharge, a small amount of discharge occurs so that wall charges formed on the scan electrode Y and the sustain electrode X are erased by participating in the discharge. That is, the wall charges formed in the scan electrode and the sustain electrode can be erased.

As described above, in the exemplary embodiment of the present invention, when the plasma signal is applied to the plasma display panel, an erase waveform is applied to erase all the wall charges in the cell so that the wall charge states between the cells are the same. When it is turned on, low discharge or false discharge do not occur in the reset period.

In addition to the erase waveforms shown in the first to fourth embodiments of the present invention, all of the waveforms for erasing the wall voltage between the scan electrode Y and the sustain electrode X are possible.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Thus, according to this invention, the low discharge which may generate | occur | produce when turning on the power supply of a panel can be prevented.

1 is a schematic partial perspective view of an AC plasma display panel.

2 is an arrangement diagram of electrodes of a plasma display panel.

3 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

4 is a driving waveform diagram of a plasma display panel in a normal operation.

FIG. 5 is a diagram illustrating wall charge states between electrodes after a sustain period in the driving waveform of FIG. 4.

6 to 9 are driving waveform diagrams according to the first to fourth embodiments of the present invention.

Claims (4)

A method of driving a plasma display panel including a reset period, an address period, and a sustain period, wherein a discharge cell is formed by a first electrode, a second electrode, and a third electrode, And applying an erase waveform for erasing the wall voltage between the first electrode and the second electrode after the sustain period when the power-off signal is applied to the plasma display panel. The method of claim 1, The erase waveform is a waveform for gradually increasing the voltage difference between the first electrode and the second electrode from the first voltage to the second voltage. The method of claim 1, And the erase waveform is a pulse having a first voltage for a period narrower than a width of a sustain discharge pulse applied to the first electrode for sustain discharge in the sustain period. The method of claim 1, And the erase waveform is a pulse having a first voltage for a period longer than a width of a sustain discharge pulse applied to the first electrode for sustain discharge in the sustain period.