KR20080049409A - Plasma display device - Google Patents

Abstract

A plasma display apparatus is provided to enhance image quality by reducing the length of a set-down interval and by extending the length of a set-up interval. In a plasma display apparatus including a plasma display panel with plural scan electrodes on an upper substrate, a reset interval, which is used for initiating discharge cells of the plasma display panel, sequentially includes a set-up interval(b) where voltages supplied to the scan electrodes are gradually increased and a set-down interval where the voltages are gradually decreased. The length of a pre-reset interval(a) before the reset interval is different from that of the set-down interval.

Description

Plasma display device

1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

2 is a diagram illustrating an embodiment of an electrode arrangement of a plasma display panel.

FIG. 3 is a diagram illustrating an embodiment of a method in which one frame of an image is time-divided and driven into a plurality of susfields in a plasma display device.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel.

5 to 7 are timing diagrams illustrating embodiments of a driving signal waveform supplied to a scan electrode in a reset period according to the present invention.

The present invention relates to a plasma display device, and more particularly, to a plasma display device having a driving device for applying a reset signal to a plasma display panel for initializing a plurality of discharge cells. It is about.

BACKGROUND ART In general, a plasma display panel is an apparatus that displays an image by applying a predetermined voltage to electrodes provided in a discharge space and causing a discharge, and the plasma generated during gas discharge excites a phosphor.

Such a plasma display panel is not only large in size and thin in thickness, but also has a simple structure, which makes the plasma display panel easier to manufacture and has a higher luminance and higher luminous efficiency than other flat panel display devices.

The plasma display panel is time-divisionally driven into a reset section for initializing all the discharge cells, an address section for selecting a cell in which discharge is to be generated, and a sustain section for generating sustain discharge in the selected cell. . Also, in general, the reset period is a setup period that gradually rises from the first voltage to the second voltage, a falling period that rapidly falls from the second voltage to the third voltage, and gradually falls from the third voltage to the fourth voltage. It is divided into a set-down section.

In the case of the conventional plasma display panel, there is a problem in that the image quality of the display image is deteriorated due to the occurrence of bright spot discharge and flicker and an increase in black brightness.

SUMMARY In order to solve the above problems in the plasma display device, a technical object of the present invention is to provide a plasma display device capable of improving image quality of a display image by reducing bright spot mis-discharge, blinking, and black brightness. There is a purpose.

In the plasma display device according to the present invention for solving the above technical problem, the reset period for initializing the discharge cells of the plasma display panel is a set-down period of gradually increasing the voltage supplied to the scan electrode and a set down gradually decreases. And a section sequentially and the length of the pre-reset section before the reset section is different from the length of the set-down section.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a perspective view illustrating an embodiment of a structure of a plasma display panel according to the present invention.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, a lower dielectric layer 24 and a partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in one embodiment of the present invention, although each of the R, G, and B discharge cells are shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is also possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, an address signal is applied to the address electrode X, and a scan signal corresponding to each scan electrode Y is sequentially applied by one scan electrode line.

In each of the sustain periods S1, ..., S8, a sustain signal is alternately applied to the scan electrode Y and the sustain electrode Z, so that wall charges are formed in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield is sequentially different at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of sustain signals can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells; .

The reset section includes a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharges in all discharge cells. Thus, wall charges are generated. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all the scan electrodes (Y), thereby eliminating discharge discharge in all the discharge cells. Generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, a scan signal 410 having a negative scan voltage Vsc is sequentially applied to the scan electrode, and an address signal having a positive address voltage Va on the address electrode X so as to overlap the scan signal. 400 is applied. The address discharge is generated by the voltage difference between the scan signal 410 and the address signal 400 and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage is applied to the sustain electrode during the set down period and the address period.

In the sustain period, a sustain signal is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are first embodiments of signals for driving the plasma display panel according to the present invention, and the present invention is not limited by the waveforms shown in FIG. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary, and an erase signal for erasing wall charge may be applied to the sustain electrode after the sustain discharge is completed. It may be. In addition, a single sustain drive in which a sustain signal is applied to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge is also possible.

5 through 7 illustrate timing diagrams of embodiments of a driving signal waveform supplied to a scan electrode in a reset period according to the present invention.

Referring to FIG. 5, a signal is provided to the scan electrode aberrationally including a pre-reset section that gradually descends during a, a set-up section that gradually rises during a, and a set-down section that gradually descends during b, to initialize the discharge cells. .

In order to reduce the black luminance, the length b of the set down period is preferably shorter than the length a of the prereset period.

In order to secure the driving margin of the panel, the length of the reset section of each subfield should have a certain range of values. Therefore, the length of the setup section is increased by reducing the length (b) of the setdown section as described above. It is possible to improve the bright spots caused by afterglow discharge.

In order to maximize the image quality through the bright point improvement and the black luminance reduction and to effectively initialize the discharge cells, the length (a) of the preset period is preferably 1.3 to 1.8 times the length (b) of the setdown period.

For example, the length a of the preset period may have a value of 90 to 130 ms, and the length b of the set down period may have a value of 50 to 90 ms.

As the length (b) of the setdown section is shorter than the length (a) of the prereset section, the falling voltage (V2) in the setdown section may be smaller than the falling voltage (V1) in the preresetting section.

In order to maximize the image quality through the bright point reduction and the black luminance reduction and to effectively initialize the discharge cell, the falling voltage V1 in the preset period is 1.2 to 1.5 times the falling voltage V2 in the setdown period. desirable.

For example, the magnitude of the falling voltage V1 in the preset period may have a value of 170 to 210V, and the falling voltage V2 in the setdown period may have a value of 120 to 170V.

As shown in FIG. 6, the setdown section may have a floating section after a section that gradually descends. Even in this case, the length (b) of the set-down section including the falling section and the floating section is preferably shorter than the length (a) of the pre-reset section.

In order to maximize the image quality through the bright point improvement and the black luminance reduction and to effectively initialize the discharge cells, the length (a) of the preset period is preferably 1.3 to 1.8 times the length (b) of the setdown period.

For example, the length a of the preset period may have a value of 90 to 130 ms, and the length b of the set down period may have a value of 50 to 90 ms.

As the length (b) of the setdown section is shorter than the length (a) of the prereset section, the falling voltage (V2) in the setdown section may be smaller than the falling voltage (V1) in the preresetting section.

For example, the magnitude of the falling voltage V1 in the preset period may have a value of 170 to 210V, and the falling voltage V2 in the setdown period may have a value of 120 to 170V.

Referring to FIG. 7, a reset signal including a setup period and a setdown period may be supplied to the scan electrode twice in succession during the reset period. That is, during the reset period, the first reset signal including the first setup period and the first setdown period and the second reset signal including the second setup period and the second setdown period may be supplied to the scan electrode.

When the reset signal is supplied to the scan electrode once, the wall charges of all the discharge cells may not remain appropriate for the address discharge due to the imperfection of the plasma display panel. Therefore, as shown in FIG. 7, by applying the reset signal twice, wall charges of all the discharge cells can be set to a state necessary for address discharge, thereby reducing the occurrence of bright spots.

Preferably, the length c of the second set-down period has the same value as the length a of the pre-reset period. Accordingly, the falling voltage V3 in the second set-down period is also the falling voltage V1 in the pre-reset period. It is preferable that the same as).

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

According to the plasma display device of the present invention configured as described above, by increasing the length of the set-up period and the length of the set-down period in the reset period for initializing the discharge cell, the bright point according to the afterimage and afterglow mis-discharge of the panel The image quality of the display image may be improved by reducing the black luminance while improving the generation.

Claims (7)

A plasma display apparatus comprising a plasma display panel having a plurality of scan electrodes formed on an upper substrate, The reset period for initializing the discharge cells of the panel sequentially includes a setup period in which the voltage supplied to the scan electrode gradually increases and a setdown period in which the voltage gradually decreases. And a length of the pre-reset section before the reset section is different from a length of the set-down section. The method of claim 1, wherein the length of the set down period is And a time from a time when the voltage supplied to the scan electrode gradually decreases to a time when the voltage increases rapidly. The method of claim 1, wherein the reset period is And at least two reset signals including the setup period and the set down period. The method of claim 1, wherein the reset period is The length of the set down period is shorter than the length of the pre-reset period. The method of claim 1, And the length of the pre-reset section is 1.3 to 1.8 times the length of the set-down section. The method of claim 1, The magnitude of the voltage falling during the set down period is smaller than the magnitude of the voltage falling during the pre-reset period. The method of claim 1, And the magnitude of the voltage falling during the pre-reset period is 1.2 to 1.5 times the magnitude of the voltage falling during the set-down period.

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