KR100573162B1 - Driving method of plasma display panel - Google Patents

Abstract

The present invention determines whether the subfield of the displayed frame is low or high gradation to perform address discharge by dividing the panel in the case of low gradation, but does not perform address discharge by dividing the panel in the case of high gradation. The present invention relates to a plasma display panel driving method for preventing over discharge. The method may include determining whether the subfield of the displayed frame is low or high gradation, and when the subfield is high gradation, splitting the plasma display panel in the address section and not performing address discharge. Sequentially applying scan pulses to the scan electrode lines and applying address data voltages to the address electrode lines, and when the subfields are low gray, in the address section, the plasma display panel is divided into a predetermined number of addresses. And performing a discharge. Thus, according to the present invention, it is possible to determine whether the panel is divided according to whether the subfield is high or low gradation to secure a sufficient amount of charge necessary for address discharge.

Description

Driving method of plasma display panel

1 is a plan view briefly showing an electrode arrangement of a plasma display panel.

2 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of a plasma display panel.

3 is a timing diagram for explaining an example of a drive signal of a plasma display panel.

4 is a diagram illustrating a panel divided into three parts.

5 is a timing diagram for describing a driving signal of a conventional plasma display panel.

6 is a view showing the structure of a conventional plasma display panel.

7 is a view showing a driving device of a plasma display panel according to the present invention.

8 is a diagram illustrating a panel divided into two parts.

9 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.

10 is a timing diagram illustrating a driving signal of a plasma display panel according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

A ₁ , A ₄ , ..., A _m-2 : address electrode line for red light emission,

A ₂ , A ₅ , ..., A _m-1 : green light _- emitting address electrode line,

A ₃ , A ₆ , ..., A _m : address electrode line for blue light emission,

112R: red light emitting phosphor, 112G: green light emitting phosphor,

112B: blue light emitting phosphor,

PR: reset section, PA: address section,

PS: sustain discharge section, V _SC-H : 1st voltage,

V _SC-H1 : second voltage, V _SC-L1 : third voltage.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel driving method for displaying a screen by applying a discharge pulse to an electrode structure forming a display cell coated with color phosphors such as a plasma display panel (PDP). It is determined whether the subfield of the frame is low gradation or high gradation. In case of low gradation, the panel is divided to perform address discharge. In the case of high gradation, the panel is not divided to perform address discharge. The present invention relates to a plasma display panel driving method.

1 is a plan view briefly showing an electrode arrangement of a plasma display panel. Referring to FIG. 1, scan electrode lines Y ₁ , Y ₂ , ..., Y _n and common electrode lines X ₁ , X ₂ , ..., X _n are in a horizontal direction of the plasma display panel. Disposed parallel to the electrodes (collectively referred to as sustain electrode lines), the scan electrode lines (Y ₁ , Y ₂ ,..., Y _n ) and common electrode lines (X ₁ , X ₂ ,... ., the address electrode lines are arranged to intersect in _{X n) (a 1, a} 2, ..., a has _m). At a portion where the scan electrode lines, the common electrode lines, and the address electrode lines A ₁ , A ₂ , ..., A _m cross each other, a discharge cell Ce is partitioned by a partition wall, and the discharge cell ( Ce) serves as one pixel of the plasma display panel. In the space of the discharge cell Ce, there are R, G and B phosphors and a plasma forming gas, and wall charges are discharged inside the discharge cell Ce by the voltage applied to each of the scan electrode, the common electrode and the address electrode. Is generated. Plasma is formed from the plasma forming gas by the wall charge, and phosphors of the discharge cells Ce are excited by ultraviolet radiation from the plasma to generate light.

Hereinafter, the scan electrode lines Y ₁ , Y ₂ , ..., Y _n are referred to as Y electrode lines, and the common electrode lines X ₁ , X ₂ , ..., X _n are X. It is called electrode lines.

On the other hand, US Patent No. 5,541, 618 discloses an address-display separation driving method which is mainly used as a driving method of a plasma display panel. 2 shows a conventional address-display separation driving method for Y electrode lines of a plasma display panel.

Referring to the drawing, a unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 in order to realize time division gray scale display. Each subfield SF1, ..., SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain discharge section S1, ..., S8. .

In each address section A1, ..., A8, a display data signal is applied to the address electrode lines and a scan pulse corresponding to each of the Y electrode lines Y ₁ , Y ₂ , ..., Y _n is applied. It is applied sequentially.

In each sustain discharge period S1, ..., S8, the Y electrode lines Y ₁ , Y ₂ , ..., Y _n and the X electrode lines X ₁ , X ₂ , ..., X _n ) pulses for display discharge are alternately applied to cause display discharge in discharge cells in which wall charges are formed in the address sections A1, ..., A8.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge sections S1, ..., S8 occupied in the unit frame. In the case where one frame forming one image is represented by eight subfields and 256 gray levels, each subfield in turn is different at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of sustain pulses can be assigned. In order to obtain luminance of 133 gray levels, cells may be addressed and sustained and discharged during the subfield 1 period, the subfield 3 period, and the subfield 8 period.

The number of sustain discharges allocated to each subfield may be variably determined according to the weights of the subfields according to the APC (Automatic Power Control) step. The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34. In addition, the number of subfields forming one frame can be variously modified according to design specifications.

FIG. 3 is a timing diagram illustrating an example of a driving signal of a plasma display panel, and includes address electrode lines A ₁ , A ₂ ,..., A _m in one subfield SF in an ADS driving method of an AC PDP. ), the common electrode lines _{(X 1, X 2, ...} , X n) , and the scan electrode lines _{(Y 1, Y 2, ...} , Y n) denotes a driving signal applied to. Referring to FIG. 3, one subfield SF includes a reset section PR, an address section PA, and a sustain discharge section PS.

The reset section PR applies a reset pulse to all of the scan lines of all groups to force write discharge, thereby initializing the wall charge states of all cells. The reset section PR is performed before entering the address section PA, which is carried out over the entire screen, thus creating a fairly even, wall-distribution arrangement of the desired distribution. The cells initialized by the reset section PR have similar wall charge conditions in the cells.

After the reset section PR is performed, the address section PA is performed. At this time, the address period (PA), the common electrode (X) to a bias voltage (Ve) is applied to the scanning electrode in a cell position to be displayed, and _{(Y 1, Y 2, ...} , Y n) and the address electrode ( The display cells are selected by turning on A ₁ , A ₂ , ..., A _m ) simultaneously. In the address section PA, a negative scanning pulse is applied to the scan electrodes Y ₁ , Y ₂ , ..., Y _n , and an address is applied to the address electrodes A ₁ , A ₂ , ..., A _m . The address discharge is generated by applying the data voltage V _A.

After the address section PA is performed, the sustain pulse Vs is applied to the common electrodes X ₁ , X ₂ ,..., X _n and the scan electrodes Y ₁ , Y ₂ , ..., Y _n . By applying alternately, the sustain discharge section PS is performed. The display cells are selected by the wall charge distribution formed by the address discharge (which accumulates a large amount of negative charge near the scanning electrode), thereby generating sustain discharge. In the sustain discharge, the phosphor applied on the address electrode is excited by ultraviolet radiation formed by the discharge between the scan electrode and the common electrode to emit light. A low level voltage VG is applied to the address electrodes A ₁ , A ₂ ,..., A _m during the sustain discharge period PS. In PDP, the brightness is adjusted by the number of sustain discharge pulses. If the number of sustain discharge pulses in one subfield or one TV field is large, the luminance increases.

4 is a diagram illustrating a panel divided into three parts. 5 is a timing diagram for describing a driving signal of a conventional plasma display panel. Are also plane and 4, the panel is divided into three parts of the first scan electrode line in the upper part _{(Y 1, Y 2, ...} , Y n / 3) is disposed and has a second scan electrode line central (Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} ) are disposed and the third scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2} , ..., Y _n ) are arranged.

Referring to FIG. 5, in the address section PA, an address data voltage is applied to the address electrode lines, and sequentially to the first scan electrode lines Y ₁ , Y ₂ ,..., Y _{n / 3} . After the scan pulse is applied, the scan pulse is sequentially applied to the second scan electrode lines Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} , and then the third Scan pulses are sequentially applied to the scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2} ,..., Y _n . The auxiliary reset is performed before the sequential scan pulses are applied to the second scan electrode lines Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} . In addition, the auxiliary reset is performed before the sequential scan pulses are applied to the third scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2} ,..., And Y _n . The auxiliary reset may include second scan electrode lines Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} or third scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2, ...,} Y n) a first voltage (V _SC-H) a second voltage (V _SC-H1) signal is applied to the second voltage (V _SC-H1 immediately after that falls in the ) May be performed by applying the falling ramp signal to the third voltage V _SC-L1 . By performing an auxiliary reset, address discharge can be made better in the middle panel and the lower panel.

In this case, when the subfield is in high gradation, a large number of sustain pulses are applied, so that sufficient charges for address discharge are accumulated. In this case, when the panel is divided into blocks, and the address discharge is performed, over discharge occurs in the address section PA so that the wall The problem of reduced charge can occur. For this problem, it is necessary to ensure a sufficient amount of charge necessary for the address discharge so that no over discharge occurs.

The technical problem to be solved by the present invention is to solve the above disadvantages, to determine whether the sub-field of the displayed frame is low or high gradation in the case of low gradation to divide the panel to perform the address discharge, but the high gradation In this case, the present invention provides a plasma display panel driving method which prevents overdischarge from occurring in an address section by dividing the panel and not performing address discharge.

The present invention provides a plasma display panel including address electrode lines, scan electrode lines crossing the address electrode lines, and common electrode lines. In the plasma display panel driving method comprising a plurality of subfields, each of the subfields comprises a reset section, an address section, and a sustain discharge section,

Determining whether the subfield of the displayed frame is low gradation or high gradation;

When the subfield has a high gray level, in the address section, the plasma display panel is not divided to perform address discharge. In this case, scan pulses are sequentially applied to the scan electrode lines, and an address is applied to the address electrode lines. Applying a response data voltage; And

And dividing the plasma display panel into a predetermined number in the address section to perform an address discharge when the subfield has a low gray level.

Preferably, when the subfield is low gradation, in the address section, dividing the plasma display panel into two parts to perform an address discharge, wherein the scan electrode lines are divided into first scan electrode lines and After dividing into second scan electrode lines, an address data voltage is applied to the address electrode lines, and a scan pulse is sequentially applied to the first scan electrode lines, and then the second scan electrode The scan pulses are sequentially applied to the lines, and the auxiliary reset is performed before the sequential scan pulses are applied to the second scan electrode lines.

The auxiliary reset may be performed by applying a signal falling from a first voltage to a second voltage and applying a falling ramp signal from the second voltage to a third voltage to the second scan electrode lines.

Also preferably, when the subfield has a low gray level, in the address period, the plasma display panel is divided into three parts to perform an address discharge, wherein the scan electrode lines are arranged in the first scan electrode lines. And dividing the second scan electrode lines into the third scan electrode lines. In the address section, an address data voltage is applied to the address electrode lines, and a scan pulse is sequentially applied to the first scan electrode lines. After the scan pulse is sequentially applied to the second scan electrode lines, the scan pulse is sequentially applied to the third scan electrode lines, and the scan pulse is sequentially applied to the second scan electrode lines. Auxiliary reset is performed before application, and Auxiliary reset is performed before sequential scanning pulse is applied to the third scan electrode lines. All.

The auxiliary reset may be performed by applying a signal falling from a first voltage to a second voltage to the second or third scan electrode lines and applying a falling ramp signal from the second voltage to a third voltage.

The present invention also relates to a plasma display panel having address electrode lines, scan electrode lines intersecting the address electrode lines and common electrode lines, for driving the plasma display panel in three parts. The scan electrode lines may include first scan electrode lines, second scan electrode lines, and third scan electrode lines, and a unit frame may be divided into a plurality of subfields for time division gray scale display. In the plasma display panel driving method comprising a reset section, an address section, and a sustain discharge section,

In the address section, an address data voltage is applied to the address electrode lines, a scan pulse is sequentially applied to the first scan electrode lines, and a scan pulse is sequentially applied to the second scan electrode lines. Next, scan pulses are sequentially applied to the third scan electrode lines.

Performing an auxiliary reset before sequential scan pulses are applied to the second scan electrode lines;

Performing an auxiliary reset before the sequential scan pulses are applied to the third scan electrode lines; And

Determining whether the subfield of the displayed frame is low gradation or high gradation,

When the subfield has a high gray level, the polling reset time of the auxiliary reset performed in the address section is made smaller than the polling reset time of the main reset performed in the reset section.

On the other hand, the methods can be realized through a computer by means of a recording medium which records a program for execution on the computer.

Hereinafter, the configuration and operation of a plasma display panel driving method according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6 is a view showing the structure of a conventional plasma display panel. Japanese Laid-Open Patent Publication No. 1999-120924 discloses a structure of a conventional plasma display panel. Referring to FIG. 6, between the front and rear glass substrates 100 and 106 of the conventional surface discharge plasma display panel 1, the address electrode lines A ₁ , A ₂ ,..., A _m , Dielectric layers 102 and 110, Y electrode lines Y ₁ , Y ₂ , ..., Y _n , X electrode lines X ₁ , X ₂ , ..., X _n , fluorescent layer 112 As a partition wall 114 and a protective layer, the magnesium monoxide (MgO) layer 104 is provided, for example. The Y electrode lines (Y ₁ , Y ₂ , ..., Y _n ) and the X electrode lines (X ₁ , X ₂ , ..., X _n ) are collectively referred to as 'hold electrode lines', and the Y electrode The lines Y ₁ , Y ₂ , ..., Y _n are also referred to as scan electrode lines, and the X electrode lines X ₁ , X ₂ , ..., X _n are also referred to as common electrode lines. do.

The address electrode lines A ₁ , A ₂ ,..., A _m are formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 is applied in front of the address electrode lines A ₁ , A ₂ ,..., A _m . In front of the lower dielectric layer 110, barrier ribs 114 are formed in a direction parallel to the address electrode lines A ₁ , A ₂ ,..., A _m . The partition walls 114 function to partition the discharge area of each display cell and to prevent optical interference between the display cells. The fluorescent layers 112R, 112G and 112B are applied in front of the dielectric layer 110 on the address electrode lines A ₁ , A ₂ ,..., A _m between the partition walls 114, and sequentially red fluorescent light. The layer 112R, the green fluorescent layer 112G, and the blue fluorescent layer 112B are disposed.

Among the phosphors constituting the phosphor layer 112 on the address electrode lines A ₁ , A ₂ , ..., A _m , a red phosphor 112R typically employed; for example, (Y, Gd) BO ₃ : Eu ) Has a positively charged anode and the blue phosphor 112G (eg, BaMgAl ₁₀ O ₁₇ : Eu) has weak positive charge characteristics, while the green phosphor 112B (eg, Zn ₂ SiO ₄ : Mn) has a negative charge with a negative charge.

The X electrode lines X ₁ , X ₂ ,..., X _n and the Y electrode lines Y ₁ , Y ₂ ,..., Y _n are address electrode lines A ₁ , A ₂ ,. . ,, A _m ) is formed in a predetermined pattern on the back of the front glass substrate 100 to be orthogonal. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , X ₂ , ..., X _n ) and each Y electrode line (Y ₁ , Y ₂ , ..., Y _n ) are made of a transparent conductive material such as indium tin oxide (ITO). The transparent electrode lines X _na and Y _na may be formed by combining the metal electrode lines X _nb and Y _nb to increase conductivity. The front dielectric layer 102 has a front surface behind the X electrode lines X ₁ , X ₂ , ..., X _n and the Y electrode lines Y ₁ , Y ₂ , ..., Y _n . It is applied and formed. A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

A driving scheme generally applied to the plasma display panel is a scheme in which reset, address and display holding steps are sequentially performed in the unit sub-field. In the reset step, the charge states of the display cells to be driven are made uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display holding step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells performing display discharge, and the fluorescent layer of the display cells is excited by ultraviolet radiation from the plasma to generate light.

It should be noted that the plasma display panel driving method according to the present invention is not limited to the plasma display panel having the above structure, and can be applied to the plasma display panel driven by all driving waveforms having a reset period.

7 is a block diagram illustrating a general driving device of the plasma display panel.

Referring to the drawings, a typical driving apparatus of the plasma display panel includes an image processor 200, a logic controller 202, an address driver 206, an X driver 208, and a Y driver 204. The image processing unit 200 converts an external analog image signal into a digital signal, and internal image signals, for example, 8-bit red (R), green (G) and blue (B) image data, clock signals, vertical and horizontal, respectively. Generate synchronization signals. The logic controller 202 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 200. The address driver 206 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 202 to generate a display data signal, and generates the display data signal. Is applied to the address electrode lines. The X driver 208 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the logic controller 202 and applies the X driving control signal S _X to the X electrode lines. The Y driver 204 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 202, and applies the Y driving control signal S _Y to the Y electrode lines.

In the present invention, it is determined whether the subfield of the displayed frame is low gradation or high gradation.

In one embodiment of the present invention, when the subfield is of high gradation, a driving signal as shown in FIG. 3 may be applied to the reset section PR, the address section PA, and the sustain discharge section PS. That is, when the subfield is in high gradation, a large amount of sustain pulses are applied, thereby ensuring sufficient wall charge necessary for address discharge. Therefore, the address discharge is not performed by dividing the panel by blocks in the address section PA. Accordingly, overdischarge that may occur when the address discharge is performed by dividing the panel by blocks in the address section PA can be prevented.

On the other hand, when the subfield is low gradation, the address discharge may be performed by dividing the plasma display panel by a predetermined number in the address section PA. Hereinafter, the driving signal in the address section PA in the panel divided into two parts will be described with reference to FIGS. 8 and 9.

8 is a diagram illustrating a panel divided into two parts, and FIG. 9 is a timing diagram for describing a driving signal of a plasma display panel according to an exemplary embodiment of the present invention. 8, the panel 2 is divided into the upper part of a first scan electrode lines (Y _1, Y _2, ..., Y _{n / 2)} the second scan electrode line is positioned and the lower part ( Y _{n / 2 + 1} , Y _{n / 2 + 2} , ..., Y _n ) are disposed.

Referring to FIG. 9, in the address section PA, an address data voltage is applied to the address electrode lines, and sequentially to the first scan electrode lines Y ₁ , Y ₂ ,..., Y _{n / 2} . After the scan pulse is applied, the scan pulses are sequentially applied to the second scan electrode lines Y _{n / 2 + 1} , Y _{n / 2 + 2} ,..., And Y _n . The auxiliary reset is performed before the sequential scan pulses are applied to the second scan electrode lines Y _{n / 2 + 1} , Y _{n / 2 + 2} ,..., Y _n . The sub-reset is the second scanning electrode lines _{(Y n / 2 + 1,} Y n / 2 + 2, ..., Y n) a second voltage in the first voltage _{(V SC-H) (V} SC- in It may be performed by applying the falling ramp signal from the second voltage V _SC-H1 to the third voltage V _SC-L1 immediately after the signal falling to _H1 is applied. As described above, when the subfield is low gray level, an auxiliary reset is performed to obtain sufficient wall charge by performing address discharge for each block.

On the other hand, when the subfield is low gradation, the address discharge may be performed by dividing the plasma display panel into three parts in the address section PA. Hereinafter, the driving signal in the address section PA in the panel divided into three parts will be described with reference to FIGS. 4 and 5.

The driving signal shown in FIG. 5 is used to perform address driving by dividing the panel into three parts as shown in FIG. Referring to FIG. 4, the panel is divided into three parts such that the first scan electrode lines Y ₁ , Y ₂ ,..., And _{n n / 3} are arranged on the upper part, and the second scan electrode lines ( Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} are disposed and the third scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2,.} .., Y _n ) is disposed.

Referring to FIG. 5, in the address section PA, an address data voltage is applied to the address electrode lines, and sequentially to the first scan electrode lines Y ₁ , Y ₂ ,..., Y _{n / 3} . After the scan pulse is applied, the scan pulse is sequentially applied to the second scan electrode lines Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} , and then the third Scan pulses are sequentially applied to the scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2} ,..., Y _n . The auxiliary reset is performed before the sequential scan pulses are applied to the second scan electrode lines Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} . In addition, the auxiliary reset is performed before the sequential scan pulses are applied to the third scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2} ,..., And Y _n . The auxiliary reset may include second scan electrode lines Y _{n / 3 + 1} , Y _{n / 3 + 2} ,..., Y _{2n / 3} or third scan electrode lines Y _{2n / 3 + 1} , Y _{2n / 3 + 2, ...,} Y n) a first voltage (V _SC-H) a second voltage (V _SC-H1) signal is applied to the second voltage (V _SC-H1 immediately after that falls in the ) May be performed by applying the falling ramp signal to the third voltage V _SC-L1 .

As described above, when the subfield is low gradation, an auxiliary reset may be performed in the address section PA to secure wall charges necessary for the address discharge.

Another embodiment of the present invention will now be described with reference to FIG. 10. 10 is a timing diagram illustrating a driving signal of a plasma display panel according to another exemplary embodiment of the present invention. In the present invention, when the subfield is low gradation, as described above, the panel is divided into a predetermined number to perform address discharge.

On the other hand, even when the sub-field is high gradation, the address discharge may be performed by dividing the panel into a predetermined number, for example, three parts. At this time, the polling reset time of the auxiliary reset performed in the address section PA is made smaller than the polling reset time of the main reset performed in the reset section PR.

Referring to FIG. 10, it can be seen that the polling reset time of the auxiliary reset performed in the address section PA is shorter than the polling reset time of the main reset performed in the reset section PR.

Therefore, when the subfield is in high gradation, a large number of sustain pulses are applied, and thus sufficient charge is accumulated for the address discharge. Thus, when performing the address discharge by dividing the panel into blocks, the polling reset time of the auxiliary reset is reduced. PA) can prevent overdischarge.

Although the present invention has described a method for driving a panel divided into two or three, it should be noted that the present invention is not limited thereto and may be applied to a method for driving a panel divided into four or more. In addition, although the present invention has described a method for driving a panel divided into two or three evenly, it should be noted that the present invention can be applied to a method for driving a panel divided differently.

Meanwhile, the display panel driving method according to the present invention described above may be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores programs or data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory and optical data storage. Here, the program stored in the recording medium refers to a series of instruction instructions used directly or indirectly in an apparatus having an information processing capability such as a computer to obtain a specific result. Thus, the term computer is used to mean all devices having an information processing capability for performing a specific function by a program, including a memory, an input / output device, and an arithmetic device, regardless of the name actually used. Even in the case of a device for driving a panel, its use is limited to a specific field of panel driving, and in reality, it is a kind of computer.

In particular, the display panel driving method according to the present invention is an integrated circuit, for example, a field programmable gate array (FPGA), which is prepared by a schematic or ultra high-speed integrated circuit hardware description language (VHDL) on a computer, and connected to a computer. It can be implemented by. The recording medium includes such a programmable integrated circuit.

Although the preferred embodiments of the present invention have been described in detail above, those of ordinary skill in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the present invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, according to the present invention, it is possible to determine whether the panel is divided according to whether the subfield is high or low gradation to secure a sufficient amount of charge necessary for the address discharge.

In the case where the subfield has a high gradation, since the panel is not divided to perform address discharge, over discharge can be prevented in the address section. Therefore, a sufficient amount of charge necessary for address discharge can be ensured. In addition, when the subfield is divided into high gradations, even when the panel is divided and the address discharge is performed, over discharge can be prevented in the address section by shortening the execution time of the reset in the address section.

On the other hand, when the subfield is low gradation, the panel may be divided to perform address discharge to secure a sufficient amount of charge during the address period.

Claims (7)

For a plasma display panel including address electrode lines, scan electrode lines intersecting the address electrode lines, and common electrode lines, a unit frame is divided into a plurality of subfields for time division gray scale display, and a subfield In each of the plasma display panel driving method comprising a reset section, an address section, and a sustain discharge section, Determining whether the subfield of the displayed frame is low gradation or high gradation; When the subfield has a high gray level, in the address section, the plasma display panel is not divided to perform address discharge. In this case, scan pulses are sequentially applied to the scan electrode lines, and the address electrode lines are applied to the address electrode lines. Applying an address data voltage; And And dividing the plasma display panel into a predetermined number in the address section to perform an address discharge when the subfield is low gradation. The method of claim 1, When the subfield is low gradation, in the address section, dividing the plasma display panel into two parts to perform an address discharge; Dividing the scan electrode lines into first scan electrode lines and second scan electrode lines, In the address section, an address data voltage is applied to the address electrode lines, a scan pulse is sequentially applied to the first scan electrode lines, and a scan pulse is sequentially applied to the second scan electrode lines. , And performing an auxiliary reset before the sequential scan pulses are applied to the second scan electrode lines. The method of claim 2, The auxiliary reset may be performed by applying a signal falling from a first voltage to a second voltage to the second scan electrode lines and applying a falling ramp signal from the second voltage to a third voltage. Panel driving method. The method of claim 1, When the subfield is low gradation, in the address section, dividing the plasma display panel into three parts to perform address discharge; Dividing the scan electrode lines into first scan electrode lines, second scan electrode lines, and third scan electrode lines; In the address section, an address data voltage is applied to the address electrode lines, a scan pulse is sequentially applied to the first scan electrode lines, and a scan pulse is sequentially applied to the second scan electrode lines. Next, scan pulses are sequentially applied to the third scan electrode lines. Performing an auxiliary reset before the sequential scan pulses are applied to the second scan electrode lines; And performing an auxiliary reset before the sequential scan pulses are applied to the third scan electrode lines. The method of claim 4, wherein The auxiliary reset may be performed by applying a signal falling from a first voltage to a second voltage and applying a falling ramp signal from the second voltage to a third voltage to the second or third scan electrode lines. Plasma display panel driving method. For the plasma display panel including address electrode lines, scan electrode lines intersecting the address electrode lines, and common electrode lines, the scan electrode lines may be divided into three parts to drive the plasma display panel. The first scan electrode lines, the second scan electrode lines, and the third scan electrode lines each include a unit frame divided into a plurality of subfields for time division gray scale display, and each of the subfields includes a reset section and an address section. In the plasma display panel driving method comprising a, and a sustain discharge period, In the address section, an address data voltage is applied to the address electrode lines, a scan pulse is sequentially applied to the first scan electrode lines, and a scan pulse is sequentially applied to the second scan electrode lines. Next, scan pulses are sequentially applied to the third scan electrode lines. Performing an auxiliary reset before sequential scan pulses are applied to the second scan electrode lines; Performing an auxiliary reset before the sequential scan pulses are applied to the third scan electrode lines; And Determining whether the subfield of the displayed frame is low gradation or high gradation, And the polling reset time of the auxiliary reset performed in the address section is smaller than the polling reset time of the main reset performed in the reset section when the subfield has a high gray level. A recording medium on which a program for executing the method of any one of claims 1 to 6 is recorded on a computer.

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