KR20060010914A - Driving method of plasm display panel - Google Patents

Abstract

According to an embodiment of the present invention, first and second address electrodes, first and second electrodes intersecting the address electrodes, a phosphor having positive charge characteristics on the first address electrodes, and the second address are provided. A display panel driving method in which a gray scale is expressed by a combination of subfields consisting of a reset section, an address section, and a sustain discharge section, for a plasma display panel including phosphors having negative charge characteristics on electrodes, wherein the reset section includes: A reset waveform pulse is applied to the first electrode to accumulate negative charge corresponding to an address discharge condition near the first electrode, and the reset waveform pulse is terminated at least on the first electrode to the second address electrode. Previously, a plasma display panel driving method in which a negative pulse is applied is provided.

  According to the present invention, address discharge-free discharge can occur in discharge cells of all colors regardless of the types of red light emitting phosphors, green light emitting phosphors, and blue light emitting phosphors having different charge characteristics, thereby improving reliability of address discharges.

Description

Driving method of plasma display panel

1 is a timing diagram illustrating an example of a drive signal of a plasma display panel.

2 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 3 shows a typical driving apparatus of the plasma display panel shown in FIG. 2.

FIG. 4 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 2.

5 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.

6 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.

7 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.

8 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.                 

9 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.

10 is a timing diagram illustrating a driving signal of a plasma display panel according to an embodiment of the present invention.

11 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

AR: Red light emitting address electrode line

AG: Green line address electrode line

AB: Address electrode line for blue light emission

112R: Red Light Emitting Phosphor

112G: Green Light Emitting Phosphor

112B: Blue light emitting phosphor

Vb: negative pulse applied to the second address electrode line

PR ... Reset period

PA ... address period

PS ... oil fat war

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel driving method for displaying a screen by applying a discharge pulse to an electrode structure forming a display cell coated with color phosphors such as a plasma display panel (PDP), and more particularly, to negative charge characteristics. The present invention relates to a plasma display panel driving method for differently applying a pulse to drive a cell coated with a phosphor having a phosphor and a cell coated with a phosphor having a positive charge characteristic.

FIG. 1 is a timing diagram illustrating an example of a driving signal of a plasma display panel, and includes an address electrode A, a common electrode X, and a scan electrode Y1 to one subfield SF in an ADS driving method of an AC PDP. Yn) indicates a drive signal applied to the device. Referring to FIG. 1, one subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS.

The reset period PR initializes the wall charge state of all cells by applying reset pulses to the scan lines of all groups and forcibly performing a write discharge. The reset period PR is performed before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a wall distribution of wall charges with a fairly even and desired distribution. The cells initialized by the reset period PR have similar wall charge conditions in the cells.

The address period PA is performed after the reset period PR is performed. At this time, in the address period PA, the bias voltage Ve is applied to the common electrode X, and the scan electrodes Y1 to Yn and the address electrodes A1 to Am are simultaneously turned on at the cell positions to be displayed. Select the display cell. In the address period PA, a negative scan pulse is applied to the scan electrodes Y1 to Yn, and an address data voltage Va is applied to the address electrodes A1 to Am, thereby generating address discharge.

After the address period PA is performed, the sustain pulse Vs is alternately applied to the common electrodes X and the scan electrodes Y1 to Yn to perform the sustain discharge period PS. The display cells are selected by the wall charge distribution formed by the address discharge (which accumulates a large amount of negative charge near the scanning electrode), thereby generating sustain discharge. In the sustain discharge, the phosphor applied on the address electrode is excited by ultraviolet radiation formed by the discharge between the scan electrode and the common electrode to emit light. During the sustain discharge period PS, a low level voltage VG is applied to the address electrodes A1 to Am. In PDP, the brightness is adjusted by the number of sustain discharge pulses. If the number of sustain discharge pulses in one subfield or one TV field is large, the luminance increases.

However, red phosphors (for example, (Y, Gd) BO ₃ : Eu) commonly employed among the phosphors applied on the address electrode have positively charged anode properties and blue phosphors (eg, For example, BaMgAl ₁₀ O ₁₇ : Eu has a weak positive charge property, whereas a green phosphor (eg, Zn ₂ SiO ₄ : Mn) has a negative charge property.

In particular, in order for the address discharge to be smoothly performed in the address discharge section PA, positive charges must be sufficiently accumulated near the address electrode line, and the address data voltage is applied and the scanning pulse is applied to the Y electrode lines Y1 to Yn. Address discharge occurs.

However, in a discharge cell through which an address electrode coated with a phosphor having negative charge characteristics passes, it is difficult to accumulate positive charge relatively more than a discharge cell through which an address electrode with no negative charge characteristics or a phosphor coated with positive charge characteristics passes. Low discharge is likely to occur.

Therefore, when the heights of the red, green, and blue phosphor layers are the same as the heights of the partition walls, there is a problem in that the address discharge voltage for the green phosphor is relatively higher than the address discharge voltage for the red and blue phosphors. In order to solve such a problem, Japanese Patent Laid-Open No. 2001-236893 discloses that a green phosphor having a negative polarity is mixed with a green phosphor having a positive polarity and changed to bipolar. However, as the polarity of the green phosphor is changed as described above, the characteristics of the address discharge are changed, thereby affecting the characteristics of the sustain discharge performed after the address discharge.

SUMMARY OF THE INVENTION The present invention has been made in view of the prior art and various other problems, and an object of the present invention is to provide a plasma display panel driving method for improving the reliability of the address discharge.

Another object of the present invention is to apply a negative bias voltage to some address electrode lines before the address period starts according to the charge characteristics of the phosphors by RGB colors, thereby addressing all cells regardless of the charge characteristics of the phosphors by RGB colors. Disclosed is a method for driving a plasma display panel in which discharge can be suitably generated.

In accordance with another aspect of the present invention, there is provided a plasma display panel driving method including first address electrodes and second address electrodes, first and second electrodes intersecting the address electrodes, and the first address electrode. For a plasma display panel including a phosphor having a positive charge characteristic on the light emitting element and a phosphor having a negative charge characteristic on the second address electrodes, a gray scale is formed by a combination of subfields including a reset section, an address section, and a sustain discharge section. In the display panel driving method to be expressed,

In the reset section, a reset waveform pulse is applied to the first electrode to accumulate negative charge corresponding to an address discharge condition near the first electrode.

The second address electrode is provided with a plasma display panel driving method in which a negative pulse is applied to at least the first electrode before the reset waveform pulse is terminated.

In an exemplary embodiment of the plasma display panel driving method, when an erase pulse is applied to the first electrode or the second electrode, the negative pulse may be applied to the second address electrode.

In an embodiment of the plasma display panel driving method, the pulse of the reset waveform applied to the first electrode includes a rising ramp pulse and a falling ramp pulse, and a rising ramp pulse is applied to the first electrode. When applied, the negative pulse may be applied to the second address electrode.

Further, in one embodiment of the plasma display panel driving method according to the present invention, the pulse of the reset waveform applied to the first electrode includes a rising ramp pulse and a falling ramp pulse, the falling ramp pulse on the first electrode When is applied, the negative pulse may be applied to the second address electrode.

In one embodiment of the plasma display panel driving method according to the present invention, when the pulse of the reset waveform applied to the first electrode has already accumulated a sufficient negative charge corresponding to an address discharge condition on the first electrode. And a falling ramp pulse to maintain a predetermined voltage below a discharge start voltage, and when the pulse maintaining the predetermined voltage is applied to the first electrode, the negative pulse may be applied to the second address electrode. .

In one embodiment of the plasma display panel driving method according to the present invention, when the pulse of the reset waveform applied to the first electrode has already accumulated a sufficient negative charge corresponding to an address discharge condition on the first electrode. And a falling ramp pulse to maintain a predetermined voltage below a discharge start voltage, and the negative pulse may be applied to the second address electrode when the falling ramp pulse is applied to the first electrode.

Further, in one embodiment of the plasma display panel driving method according to the present invention, when the last sustain pulse of the previous subfield is applied to the first electrode or the second electrode, the negative pulse may be applied to the second address electrode. Can be.

Further, in one embodiment of the plasma display panel driving method according to the present invention, the negative pulse may be a negative square wave pulse or a negative falling ramp pulse.                     

In one embodiment of the plasma display panel driving method, the phosphor having positive charge characteristics on the first address electrodes is a red light emitting phosphor, and the phosphor having negative charge characteristics on the second address electrodes is green light emitting. It may be a phosphor.

On the other hand, the methods can be realized through a computer by means of a recording medium which records a program for execution on the computer.

Hereinafter, the configuration and operation of a plasma display panel driving method according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The plasma display panel driving method according to the present invention has a negative charge characteristic before an address period in order to prevent address misdischarge which may occur due to a difference in the amount of wall charges accumulated according to the charge characteristics of the phosphors applied on the address electrode lines. Positive charges are accumulated by applying a negative pulse to the address electrode lines corresponding to the phosphor having

2 is a view showing the structure of a conventional three-electrode surface discharge type plasma display panel. Referring to FIG. 2, between the front and rear glass substrates 100 and 106 of the conventional surface discharge plasma display panel 1, the address electrode lines A ₁ , A ₂ ,..., A _m , Dielectric layers 102 and 110, Y electrode lines Y ₁ , ..., Y _n , X electrode lines X ₁ , ..., X _n , fluorescent layer 112, barrier rib 114, and As a protective layer, the magnesium monoxide (MgO) layer 104 is provided, for example. Hereinafter, the Y electrode lines Y ₁ , ..., Y _n and the X electrode lines X ₁ , ..., X _n are collectively referred to as 'hold electrode lines', and the Y electrode lines ( Y ₁ , ..., Y _n are also called scan electrode lines, and X electrode lines X ₁ , ..., X _n are also called common electrode lines.

The address electrode lines A ₁ , A ₂ ,..., A _m are formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 is applied in front of the address electrode lines A ₁ , A ₂ ,..., A _m . In front of the lower dielectric layer 110, barrier ribs 114 are formed in a direction parallel to the address electrode lines A ₁ , A ₂ ,..., A _m . The partition walls 114 function to partition the discharge area of each display cell and to prevent optical interference between the display cells. The fluorescent layers 112R, 112G and 112B are applied in front of the dielectric layer 110 on the address electrode lines A ₁ , A ₂ ,..., A _m between the partition walls 114, and sequentially red fluorescent light. The layer 112R, the green fluorescent layer 112G, and the blue fluorescent layer 112B are disposed.

Among the phosphors constituting the phosphor layer 112 on the address electrode lines A ₁ , A ₂ ,..., A _m , a red phosphor 112R typically employed; for example, (Y, Gd) BO ₃ : Eu ) Has a positively charged anode and the blue phosphor 112G (eg, BaMgAl ₁₀ O ₁₇ : Eu) has weak positive charge characteristics, while the green phosphor 112B (eg, Zn ₂ SiO ₄ : Mn) has a negative charge with a negative charge.

The X electrode lines X ₁ , ..., X _n and the Y electrode lines Y ₁ , ..., Y _n are address electrode lines A ₁ , A ₂ , ..., A _m . It is formed in a predetermined pattern on the back of the front glass substrate 100 to be orthogonal to the. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are transparent electrode lines (X _na ) made of a transparent conductive material such as indium tin oxide (ITO). , Y _na ) and metal electrode lines X _nb and Y _nb for increasing conductivity may be formed. The front dielectric layer 102 is formed by applying the entire surface to the rear of the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ ,..., Y _n ). A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

A driving scheme generally applied to such a plasma display panel is a method in which initialization, address, and display holding steps are sequentially performed in a unit sub-field. In the initialization step, the charge states of the display cells to be driven are made uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display holding step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells performing display discharge, and the fluorescent layer 112 of the display cells is excited by ultraviolet radiation from the plasma to generate light.

3 illustrates a general driving device of the plasma display panel of FIG. 2.

Referring to the drawings, a typical driving device of the plasma display panel 1 includes an image processor 200, a controller 202, an address driver 206, an X driver 208, and a Y driver 204. The image processing unit 200 converts an external analog image signal into a digital signal, and internal image signals, for example, 8-bit red (R), green (G) and blue (B) image data, clock signals, vertical and horizontal, respectively. Generate synchronization signals. The controller 202 generates the driving control signals SA, SY, and SX according to the internal image signal from the image processor 200. The address driver 206 processes the address signal SA among the drive control signals SA, SY, and SX from the controller 202 to generate a display data signal, and generates the display data signal through the address electrode lines. To apply. The X driver 208 processes the X driving control signal SX among the driving control signals SA, SY, and SX from the controller 202 and applies the X driving control signal SX to the X electrode lines. The Y driver 204 processes the Y driving control signal SY among the driving control signals SA, SY, and SX from the controller 202 and applies the Y driving control signal SY to the Y electrode lines.

As a driving method of the plasma display panel 1 having the structure described above, an address-display separation driving method which is mainly used is disclosed in US Pat.

FIG. 4 shows a conventional address-display separation driving method for the Y electrode lines of the plasma display panel of FIG. 2.                     

Referring to the drawings, a unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ..., SF8 is divided into a reset section (not shown), an address section A1, ..., A8, and a sustain discharge section S1, ..., S8. do.

In each address section A1, ..., A8, a display data signal is applied to the address electrode lines AR1, AG1, ..., AGm, ABm in FIG. Scan pulses corresponding to..., Yn) are sequentially applied.

In each sustain discharge section S1, ..., S8, pulses for display discharge alternately in the Y electrode lines Y1, ..., Yn and the X electrode lines X1, ..., Xn. Is applied to cause display discharge in discharge cells in which wall charges are formed in the address periods A1, ..., A8.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge sections S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gray levels, each subfield is sequentially held at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128 in order. The number of pulses can be assigned. In order to obtain luminance of 133 gray levels, cells may be addressed and sustained and discharged during the subfield 1 period, the subfield 3 period, and the subfield 8 period.

The number of sustain discharges allocated to each subfield may be variably determined according to the weights of the subfields according to the APC (Automatic Power Control) step. The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34. In addition, the number of subfields forming one frame can be variously modified according to design specifications.

Meanwhile, in the plasma display panel driving method according to the present invention, each address electrode line corresponding to at least one of the phosphors 112R, 112G, and 112B for each RGB color having different charge characteristics before starting in the address period PA is obtained. A negative bias pulse is applied to the field to sufficiently accumulate positive charges.

  Hereinafter, it is assumed that the red light emitting (R) phosphor has a positive charge characteristic, the green light emitting (G) phosphor has a negative charge characteristic, and the blue light emitting (B) phosphor has a neutral characteristic or a weak positive charge characteristic. However, it should be noted that this assumption is merely for convenience of description and falls within the scope of the present invention even when the charge characteristic for each RGB color is different from the above assumption.

5 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 5, in the reset period PR, reset pulses are applied to all of the scan lines of all groups, thereby forcing write discharge, thereby initializing the wall charge states of all cells. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. The cells initialized by the reset period PR have similar wall charge conditions inside the cells.

The address period PA is performed after the reset period PR is performed. At this time, in the address period PA, the bias voltage Ve is applied to the common electrode X, and the scan electrodes Y1 to Yn and the address electrodes A1 to Am are simultaneously turned on at the cell positions to be displayed. Select the display cell.

After the address period PA is performed, the sustain pulse Vs is alternately applied to the common electrodes X and the scan electrodes Y1 to Yn to perform the sustain discharge period PS. During the sustain discharge period PS, a voltage V _G having a low level (ground potential) is applied to the address electrodes A1 to Am. In PDP, the brightness is adjusted by the number of sustain discharge pulses. If the number of sustain discharge pulses in one subfield or one TV field is large, the luminance increases.

In general, in the ramp-down period of the reset period PR, negative charges are emitted from the Y electrode and positive charges are emitted from the X electrode and the address electrode, so that the secondary weak discharge is generated and the initialization is completed in all the discharge cells. After the pulse, an appropriate amount of negative charge remains near the Y electrode (dielectric layer on the Y electrode). In the address period PA, the address discharges are the scan low-level voltages V _{SC -L} and Y of the scanning pulses applied to the Y electrodes at the potentials of the voltage Va of the display data signal and the positive charge accumulated near the address electrodes. This is caused by the energy minus the potential due to the negative charge accumulated near the electrode (that is, the sum of the absolute values of all the potentials). In order for the address discharge to occur sufficiently, wall charges must be appropriately formed on the address electrode and the scan electrode until immediately before the address discharge, which is called an address discharge condition.

However, since a phosphor having negative charge characteristics, for example, a green phosphor composed of Zn ₂ SiO ₄ : Mn has a negative polarity, a positive charge is attracted to the dielectric on the corresponding address electrode lines and thus attracts the green phosphor. The positive charges tend to not accumulate sufficiently. That is, some of the positive charges do not contribute to the discharge due to the phosphor having negative charge characteristics.

Accordingly, in the method of driving the plasma display panel according to the exemplary embodiment of the present invention, as shown in FIG. 5, in the reset period PR, negative pulses are applied to address electrode lines corresponding to phosphors having negative charge characteristics. (Vb) is applied. In FIG. 5, green light emitting address electrode lines AG within the period t0 to t1 during which an erase pulse of a rising ramp waveform is applied to the X electrode lines X1 to Xn. The negative pulse Vb is applied to Am-1).

In FIG. 5, the erase pulses t0 to t1 are applied to the common electrodes X1 to Xn, but the address electrode lines are applied even when the erase pulses t0 to t1 are applied to the scan electrodes Y1 to Yn. It should be noted that a negative pulse Vb may be applied to.

In the waveform diagram of FIG. 5, since an erase pulse of a rising ramp waveform is applied to the X electrode lines X1 to Xn, positive charges may be emitted from the X electrode lines X1 to Xn. A part of the positive charges emitted from the X electrode lines X1 to Xn is formed by the dielectric on the green light-emitting address electrode lines AG (A2, A5, ..., Am-1) to which the negative pulse Vb is applied. 110, and thus, the dielectric 110 on the green light emitting address electrode lines AG (A2, A5, ..., Am-1) may have other red light emitting address electrode lines AR; More positive charges may be accumulated than the dielectric 110 corresponding to A1, A4, ..., Am-2) or the blue light-emitting address electrode lines AB (A3, A6, ..., Am).

Therefore, in the address period PA, since a sufficient amount of positive charges are accumulated on the green light emitting address electrode lines AG (A2, A5, ..., Am-1), despite the negative charge characteristics of the green light emitting phosphor 112G. And, as with the other red or blue light emitting address electrode lines, it has a potential due to a large amount of positive charge. Therefore, the address low discharge does not occur even in the green light-emitting address electrode lines AG (A2, A5, ..., Am-1).

Meanwhile, the bias voltage Ve is applied to the X electrode lines X1 to Xn. The role of the bias voltage Ve is to prepare a sustain discharge, which firstly accumulates a sufficient negative charge near the common electrodes X1 to Xn when the positive charge is accumulated near the Y electrode due to the address discharge. And secondly, to strengthen the counter discharge between the address electrodes A1 to Am and the Y electrode lines Y1 to Yn. The term 'enhancing opposite discharge' means that the positive discharge emitted from the dielectric on the address electrode does not come toward the X electrode lines X1 to Xn, but toward the scan electrode, so that the address discharge can be smoothly performed between the address electrode and the Y electrode. This means that the counter discharge between the Y electrode and the address electrode is strengthened.

The operation in the sustain discharge section PS will be described below.

At the time when the first sustain pulse is applied in the sustain discharge period PS, positive charges accumulated in the address period are accumulated on the Y electrode lines and negative charges are accumulated on the X electrode lines. When the sustain voltage Vs is applied to the Y electrode lines, the positive charge is discharged from the Y electrode lines and the negative charge is discharged into the space charge from the X electrode lines, thereby performing the primary sustain discharge. This primary sustain discharge is characterized by the difference between the sum of the positive charge and the Vs voltage accumulated near the Y electrode lines and the negative charge (ie the sum of the absolute values of all potential values) accumulated near the X electrode lines. It is done while exceeding. When the primary sustain discharge occurs, negative charges accumulate near the Y electrode lines and positive charges accumulate near the X electrode lines.

After the first sustain discharge, when the sustain voltage Vs is applied to the X electrode lines X1 to Xn, positive charges begin to be discharged into the space charges on the X electrode lines, and negative charges are space charges on the Y electrode lines. Is discharged to perform secondary sustain discharge. The secondary sustain discharge is obtained by subtracting the potential of the negative charge accumulated near the scan electrode lines from the potential due to the Vs voltage applied to the X electrode lines X1 to Xn and the positive charge accumulated near the X electrodes (ie , The sum of the absolute values of all potential values) exceeds the discharge start voltage. When the primary sustain discharge occurs, positive charges accumulate near the Y electrode lines, just as before the primary sustain discharge, and negative charges accumulate near the X electrode lines. After that, the third sustain discharge occurs by the same action as the first sustain discharge, and then the fourth sustain discharge occurs by the same action as the second sustain discharge. Alternate sustain pulses are maintained for a predetermined time for each subfield, and such sustain discharge is continued.

6 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention. As can be seen in FIG. 6, a reset waveform pulse is applied to the Y electrode lines Y1 to Yn to accumulate negative charges corresponding to the address discharge conditions near the Y electrode lines Y1 to Yn. . The reset waveform pulse for accumulating negative charges near the Y electrode lines Y1 to Yn ranges from a predetermined voltage (for example, Vs in FIG. 6) to a very high voltage (expressed as Vset + Vs in FIG. 6). Rising ramp pulses and rising ramp pulses that fall to a voltage near the scan pulse at a predetermined voltage (eg, Vs).

In the embodiment of FIG. 6, within the period t1 to t2 during which the rising ramp pulse is applied to the Y electrode lines Y1 to Yn, the green light-emitting address electrode lines AG which are negatively charged characteristics (AG; A2, The negative pulse Vb is applied to A5, ..., Am-1.

In this case, since a rising ramp pulse is applied to the Y electrode lines Y1 to Yn, very large negative charges may be accumulated on the Y electrode lines Y1 to Yn, and positive charges may be emitted therefrom. A part of the positive charges emitted from the Y electrode lines Y1 to Yn is formed by the dielectric on the green light-emitting address electrode lines AG (A2, A5, ..., Am-1) to which the negative pulse Vb is applied. 110, and thus, the dielectric 110 on the green light emitting address electrode lines AG (A2, A5, ..., Am-1) may have other red light emitting address electrode lines AR; More positive charges may be accumulated than the dielectric 110 corresponding to A1, A4, ..., Am-2) or the blue light-emitting address electrode lines AB (A3, A6, ..., Am).

Therefore, in the address period PA, since a sufficient amount of positive charges are accumulated on the green light emitting address electrode lines AG (A2, A5, ..., Am-1), despite the negative charge characteristics of the green light emitting phosphor 112G. And, as with the other red or blue light emitting address electrode lines, it has a potential due to a large amount of positive charge. Therefore, the address low discharge does not occur even in the green light-emitting address electrode lines AG (A2, A5, ..., Am-1).

Since the operation of the address discharge and the sustain discharge generated in the sustain discharge section PS which are sequentially generated in the address discharge section PA are the same as those of the embodiment of FIG. 5, the description thereof will be omitted.

7 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention. As shown in FIG. 7, a reset waveform pulse is applied to the Y electrode lines Y1 to Yn to accumulate negative charges corresponding to the address discharge conditions near the Y electrode lines Y1 to Yn. . The reset waveform pulse for accumulating negative charge near the Y electrode lines Y1 to Yn rises from a predetermined voltage (for example, Vs in FIG. 7) to a very high voltage (indicated by Vset + Vs in FIG. 7). The rising ramp pulse, and the falling ramp pulse falling to a voltage near the scan pulse at a predetermined voltage (for example, Vs).

In the embodiment of FIG. 7, within the period t1 to t2 during which the falling ramp pulse is applied to the Y electrode lines Y1 to Yn, the green light-emitting address electrode lines AG which are negatively charged characteristics (AG; A2, The negative pulse Vb is applied to A5, ..., Am-1.

In this case, since the falling ramp pulse is applied to the Y electrode lines Y1 to Yn, a part of the negative charge accumulated on the Y electrode lines Y1 to Yn is emitted, thereby causing the Y electrode lines Y1 to Yn to be discharged. ), A positive amount of negative charge necessary for address discharge remains. A part of the negative charges emitted from the Y electrode lines Y1 to Yn may be discharged to the space in the discharge cell and drawn out near the address electrode lines to cancel the positive charges. Therefore, in the driving method of the plasma display panel according to the present invention, the green light-emitting address electrode lines AG which are phosphors having negative charge characteristics within the falling ramp pulse period t4 to t5 of FIG. The negative pulse Vb is applied to Am-1 to prevent the negative charges emitted from the Y electrode lines Y1 to Yn from accumulating so that the amount of positive charges accumulated is sufficient. As a result, other red light emitting address electrode lines AR are arranged on the dielectric 110 on the green light emitting address electrode lines AG (A2, A5, ..., Am-1). More positive charges may be accumulated than the dielectric 110 corresponding to Am-2) or the blue light-emitting address electrode lines AB (A3, A6, ..., Am).

Therefore, in the address period PA, since a sufficient amount of positive charges are accumulated on the green light emitting address electrode lines AG (A2, A5, ..., Am-1), despite the negative charge characteristics of the green light emitting phosphor 112G. And, as with the other red or blue light emitting address electrode lines, it has a potential due to a large amount of positive charge. Therefore, the address low discharge does not occur even in the green light-emitting address electrode lines AG (A2, A5, ..., Am-1).

8 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention. Referring to the reset section PR in FIG. 8, in order to prevent waste of power loss when the negative charge corresponding to the address discharge condition is already accumulated in the Y electrode lines Y1 to Yn, the Y electrode lines ( The pulse of the reset waveform applied to Y1 to Yn includes a pulse holding a predetermined voltage (for example, Vs + V1) equal to or lower than the discharge start voltage and a falling ramp pulse.                     

As shown in FIG. 8, a reset waveform without a rising ramp pulse is commonly referred to as an auxiliary reset waveform, and the auxiliary reset waveform is a discharge start voltage to prevent strong discharge from occurring in the Y electrode lines Y1 to Yn during reset discharge. After applying the following predetermined pulses to accumulate a large amount of negative charges, the falling ramp pulse is applied to form a positive charge suitable for the address discharge in all the discharge cells. A more detailed description of the auxiliary reset is disclosed in Korean Patent Application No. 2001-15246 and Korean Patent Application No. 2001-62355.

As can be seen in FIG. 8, in the Y electrode lines Y1 to Yn in which a large number of negative charges have already been accumulated, auxiliary for accumulating negative charges corresponding to the address discharge conditions near the Y electrode lines Y1 to Yn. The pulse of the reset waveform is applied. The pulse of the auxiliary reset waveform is a square wave pulse that maintains a predetermined voltage (eg, Vs + V1 in FIG. 8) and a drop that falls down to a voltage near the scanning pulse (eg, V _{SC -L} in FIG. 8). It may consist of a ramp pulse. In the embodiment of FIG. 8, within the periods t1 to t3 where the square wave pulses are maintained in the Y electrode lines Y1 to Yn, the green light-emitting address electrode lines AG, A2 and A5 which are phosphors having negative charge characteristics , ..., Am-1) is applied with a negative pulse (Vb).

In this case, since a square wave pulse having a predetermined voltage (for example, Vs + V1 in FIG. 8) is applied to the Y electrode lines Y1 to Yn, more on the Y electrode lines Y1 to Yn. Negative charges build up. At this time, in the driving method of the plasma display panel according to the present invention, green light-emitting address electrode lines AG which are negative phosphors within the falling ramp pulse period t4 to t5 of FIG. 8. When the negative pulse Vb is applied to Am-1, positive charges emitted from the Y electrode lines Y1 to Yn are transmitted to the green light-emitting address electrode lines AG; A2, A5, ..., Am. And negative charges from the green light-emitting address electrode lines AG (A2, A5, ..., Am-1) to be accumulated on the Y electrode lines (Y1 to Yn).

As a result, other red light emitting address electrode lines AR are arranged on the dielectric 110 on the green light emitting address electrode lines AG (A2, A5, ..., Am-1). More positive charges may be accumulated than the dielectric 110 corresponding to Am-2) or the blue light-emitting address electrode lines AB (A3, A6, ..., Am).

Therefore, in the address period PA, since a sufficient amount of positive charges are accumulated on the green light emitting address electrode lines AG (A2, A5, ..., Am-1), despite the negative charge characteristics of the green light emitting phosphor 112G. And, as with the other red or blue light emitting address electrode lines, it has a potential due to a large amount of positive charge. Therefore, the address low discharge does not occur even in the green light-emitting address electrode lines AG (A2, A5, ..., Am-1).

9 is a timing diagram illustrating a driving signal of a plasma display panel according to an exemplary embodiment of the present invention. Referring to the reset section PR in FIG. 9, an auxiliary reset waveform is applied. That is, as in the embodiment of FIG. 8, in order to prevent waste of power loss when negative charges corresponding to the address discharge conditions are already accumulated in the Y electrode lines Y1 to Yn, the Y electrode lines Y1 to Yn. The pulse of the reset waveform applied to Yn) includes a pulse holding a predetermined voltage below the discharge start voltage (for example, Vs + V1) and a falling ramp pulse.

In the embodiment of FIG. 9, within the periods t1 to t3 in which the falling ramp pulses t4 to t5 are maintained in the Y electrode lines Y1 to Yn, the green light-emitting address electrode lines that are phosphors having negative charge characteristics. The negative pulse Vb is applied to (AG; A2, A5, ..., Am-1).

In this case, since a square wave pulse having a predetermined voltage (for example, Vs + V1 in FIG. 9) is applied to the Y electrode lines Y1 to Yn, more on the Y electrode lines Y1 to Yn. Negative charges build up. Thereafter, the falling ramp pulses t4 to t5 are applied to the Y electrode lines Y1 to Yn to the voltage V _{SC -L} near the scan pulse at a predetermined voltage (for example, Vs). As a part of the negative charges accumulated on the Y electrode lines Y1 to Yn is released, an appropriate amount of negative charges necessary for the address discharge remains on the Y electrode lines Y1 to Yn. A part of the negative charges emitted from the Y electrode lines Y1 to Yn may be discharged to the space in the discharge cell and drawn out near the address electrode lines to cancel the positive charges. Therefore, in the driving method of the plasma display panel according to the present invention, the green light-emitting address electrode lines AG which are phosphors having negative charge characteristics within the falling ramp pulse period t4 to t5 of FIG. The negative pulse Vb is applied to Am-1 to prevent the negative charges emitted from the Y electrode lines Y1 to Yn from accumulating so that the amount of positive charges accumulated is sufficient. As a result, other red light emitting address electrode lines AR are arranged on the dielectric 110 on the green light emitting address electrode lines AG (A2, A5, ..., Am-1). More positive charges may be accumulated than the dielectric 110 corresponding to Am-2) or the blue light-emitting address electrode lines AB (A3, A6, ..., Am).

10 is a timing diagram illustrating a driving signal of a plasma display panel according to an embodiment of the present invention.

In the embodiment of FIG. 10, a green light emitting address that is a phosphor having negative charge characteristics within a period t9 to t10 in which the last sustain pulse Vs of the sustain discharge interval PS occurs in one subfield SF _n . The negative pulse Vb is applied to the electrode lines AG (A2, A5, ..., Am-1), and thus the green light emitting address electrode lines (AG; The accumulation of positive charges at −1) then affects the next subfield SF _{n +1} .

For example, as shown in FIG. 10, a positive charge is emitted from the vicinity of the X electrodes when the last sustain pulse is applied to the X electrode lines X1 to Xn. The positive charges thus emitted generate a discharge together with the negative charges from the Y electrode lines Y1 to Yn. In the plasma display panel driving method according to an embodiment of the present invention, when the last sustain pulse occurs, the green light-emitting address electrode lines AG (A; A2, A5, ..., Am-1), which are phosphors having negative charge characteristics, are applied. By applying the negative pulse Vb, a part of the positive charges emitted from the sustain electrode (X electrode or Y electrode) is taken in and accumulated.

The green light-emitting address electrode lines AG (A2, A5, ..., Am-1) having a large amount of positive charges thus accumulated are stored in the address section PA of the next subfield SF _{n +1} . Sufficient address discharge conditions for generating address discharge can be provided.

Meanwhile, in the waveform diagrams of FIGS. 5 to 10, the negative pulse Vb applied to the green light emitting address electrode lines AG (A2, A5, ..., Am-1) represents a square wave pulse. However, negative pulses of falling ramp waveforms may also be applied.

For example, FIG. 11 is a timing diagram modified from FIG. 5, and illustrates a state in which a negative falling ramp pulse Vb is applied to address electrode lines corresponding to phosphors having negative charge characteristics in the reset period PR. .

In FIG. 11, the green light-emitting address electrode lines AG within the period t0 to t1 where the erase pulse of the rising ramp waveform is applied to the X electrode lines X1 to Xn. The negative falling ramp pulse Vb is applied to Am-1).

As described above, when the negative pulse Vb applied to the address electrode lines AG corresponding to the phosphor having negative charge characteristics (AG; A2, A5, ..., Am-1) is a negative pulse of the falling ramp waveform, the square wave Compared to the negative pulse, positive charges can be slowly and stably accumulated on the address electrodes while preventing an erroneous discharge between the address electrode and the sustain electrode (the X electrode or the Y electrode), that is, an unintended strong discharge occurs.

It should be noted that all of the negative pulses of the falling ramp waveform may be deformably applied to the negative pulses Vb of FIGS. 5 to 10.

Meanwhile, the display panel driving method according to the present invention described above may be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores programs or data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory and optical data storage. Here, the program stored in the recording medium refers to a series of instruction instructions used directly or indirectly in an apparatus having an information processing capability such as a computer to obtain a specific result. Thus, the term computer is used to mean all devices having an information processing capability for performing a specific function by a program, including a memory, an input / output device, and an arithmetic device, regardless of the name actually used. Even in the case of a device for driving a panel, its use is limited to a specific field of panel driving, and in reality, it is a kind of computer.

In particular, the display panel driving method according to the present invention is an integrated circuit, for example, a field programmable gate array (FPGA), which is prepared by a schematic or ultra high-speed integrated circuit hardware description language (VHDL) on a computer, and connected to a computer. It can be implemented by. The recording medium includes such a programmable integrated circuit.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the plasma display panel driving method of the present invention has the following effects.

First, if a negative pulse for accumulating positive charges is applied to an address electrode corresponding to a specific phosphor in advance according to a kind of phosphor having different charge characteristics in an address section, there is no false discharge in all discharge cells regardless of the kind of phosphor. Since address discharge may occur, the reliability of the address discharge is improved.

Second, according to the red light emitting phosphor, green light emitting phosphor, and blue light emitting phosphor having different charge characteristics, one of the timings of erasing pulse, rising ramp pulse, falling ramp pulse, or last sustain pulse of the previous subfield is applied to the scan electrode. A negative pulse can be selectively applied to the address electrode corresponding to each phosphor.

Third, the manufacturing cost of the phosphor is reduced and applied to the address electrode according to the type of the phosphor, compared with the conventional technique of changing the charge characteristics of the phosphor by mixing the phosphor having a polarity with the green light emitting phosphor in order to improve the reliability of the address discharge. Since the application timing of the negative pulse can be adjusted flexibly, the degree of freedom in designing the address discharge is improved.

The invention is not limited to the examples described above and represented in the drawings. Those skilled in the art taught by the above-described embodiments, many modifications to the above-described embodiments are possible by substitution, erasure, merging, etc. within the scope and object of the present invention described in the following claims.

Claims (11)

First and second address electrodes, first and second electrodes intersecting the address electrodes, phosphors having positive charge characteristics on the first address electrodes, and on the second address electrodes. A display panel driving method in which a gradation is expressed by a combination of subfields consisting of a reset section, an address section, and a sustain discharge section, for a plasma display panel having phosphors having negative charge characteristics in In the reset section, a reset waveform pulse is applied to the first electrode to accumulate negative charge corresponding to an address discharge condition near the first electrode. And a negative pulse is applied to the second address electrode before at least the reset waveform pulse is terminated on the first electrode. The method of claim 1, And when the erase pulse is applied to the first electrode or the second electrode, the negative pulse is applied to the second address electrode. The method of claim 1, The reset waveform pulse applied to the first electrode includes a rising ramp pulse and a falling ramp pulse, And a negative pulse is applied to the second address electrode when a rising ramp pulse is applied to the first electrode. The method of claim 1, The reset waveform pulse applied to the first electrode includes a rising ramp pulse and a falling ramp pulse, And when the falling ramp pulse is applied to the first electrode, the negative pulse is applied to the second address electrode. The method of claim 1, The pulse of the reset waveform applied to the first electrode includes a pulse for maintaining a predetermined voltage below the discharge start voltage and a falling ramp pulse when a sufficient negative charge corresponding to an address discharge condition is already stored in the first electrode. and, And when the pulse for maintaining the predetermined voltage is applied to the first electrode, the negative pulse is applied to the second address electrode. The method of claim 1, The pulse of the reset waveform applied to the first electrode includes a pulse for maintaining a predetermined voltage below the discharge start voltage and a falling ramp pulse when a sufficient negative charge corresponding to an address discharge condition is already stored in the first electrode. and, And when the falling ramp pulse is applied to the first electrode, the negative pulse is applied to the second address electrode. The method of claim 1, And when the last sustain pulse of the previous subfield is applied to the first electrode or the second electrode, the negative pulse is applied to the second address electrode. The method of claim 1, And the negative pulse is a negative square wave pulse. The method of claim 1, The negative pulse is a plasma display panel driving method, characterized in that the negative falling ramp pulse. The method of claim 2, The phosphor having positive charge characteristics on the first address electrodes is a red light emitting phosphor, and the phosphor having negative charge characteristics on the second address electrodes is a green light emitting phosphor. A recording medium having recorded thereon a program for executing the method of any one of claims 1 to 10 on a computer.

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