KR100578848B1 - Drving method of plasma display panel and plasma display device - Google Patents

Abstract

The method for driving a plasma display panel of the present invention provides a method for driving a plasma display panel that can be addressed without using an internal wall voltage.

In particular, the present invention provides a method of driving a plasma display panel that prevents strong discharge that may occur in a reset period of a method of driving an addressable plasma display panel that does not use an internal wall voltage.

Wall Charge, Wall Voltage, Reset Period, PDP

Description

Driving method of plasma display panel and plasma display device {DRVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a partial perspective view of a typical plasma display panel.

2 shows an electrode arrangement diagram of a typical plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

5 is a diagram illustrating a relationship between a falling ramp voltage and a wall voltage when a falling ramp voltage is applied to a discharge cell.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

The present invention relates to a method of driving a plasma display panel (PDP).

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, a structure of a general plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. Address electrodes A1-Am are arranged in the column direction, and n rows of scan electrodes Y1-Yn and sustain electrodes X1-Xn are arranged in pairs in the row direction.

As a method of driving a conventional plasma display panel, there is a method described in US Pat. No. 6,294,875 to Kurata et al. The driving method of 875 is a method of dividing one field into eight subfields and then different waveforms applied in the reset period of the first subfield and the second to eighth subfields.

As shown in Fig. 3, each subfield includes a reset period, an address period, and a sustain period. In the reset period of the first subfield, a ramp voltage gradually rising from the Vp voltage smaller than the discharge start voltage to the Vr voltage exceeding the discharge start voltage is first applied to the scan electrodes Y1-Yn. While this ramp voltage is rising, weak discharge occurs from the scan electrodes Y1-Yn to the address electrodes A1-Am and the sustain electrodes X1-Xn, respectively. This discharge causes negative wall charges to accumulate in the scan electrodes Y1-Yn, and positive wall charges accumulate in the address electrodes A1-Am and sustain electrodes X1-Xn. Referring to FIG. 1, wall charges are formed on the surface of the protective film 3 of the scan electrode 4 and the sustain electrode 5, but are described below as being formed on the scan electrode 4 and the sustain electrode 5 for convenience of description.

Subsequently, a ramp voltage gently falling to 0 V is applied to the scan electrodes Y1-Yn at a voltage Vq lower than the discharge start voltage. Then, while the ramp voltage falls, the weak discharge occurs from the sustain electrodes X1-Xn and the address electrodes A1-Am to the scan electrodes Y1-Yn by the wall voltage formed in the discharge cells. By this discharge, the wall charges formed in the sustain electrodes X1-Xn, the scan electrodes Y1-Yn and the address electrodes A1-Am are partially erased and set to a state suitable for addressing. Similarly, referring to FIG. 1, wall charges are formed on the surface of the insulator layer 7 of the address electrode 8, but are represented below as being formed on the address electrode 8 for convenience of description.

Next, in the address period, the positive voltage Vw is applied to the address electrodes A1-Am of the discharge cells to be selected, and 0 V is applied to the scan electrodes Y1-Yn. Then, between the address electrodes A1-Am and the scan electrodes Y1-Yn and the sustain electrodes X1-Xn and the scan electrodes Y1- by the wall voltage and the positive voltage Vw caused by the wall charges formed in the reset period. Address discharge occurs between Yn). This discharge accumulates positive wall charges in the scan electrodes Y1-Yn and negative wall charges in the sustain electrodes X1-Xn and the address electrodes A1-Am. In the discharge cells in which the wall charges are accumulated by the address discharge, sustain discharge occurs by a sustain pulse applied in the sustain period.

Next, the voltage level of the last sustain pulse applied to the scan electrodes Y1-Yn in the sustain period of the first subfield is equal to the Vr voltage in the reset period, and the Vr voltage and the sustain voltage ( The voltage Vr-Vs corresponding to the difference of Vs) is applied. Then, in the discharge cells selected in the address period, discharge occurs from the scan electrodes Y1-Yn to the address electrodes A1-Am by the wall voltage formed by the address discharge, and from the scan electrodes Y1-Yn to the sustain electrode X1. Sustain discharge occurs at -Xn). This discharge corresponds to the discharge generated by the rising ramp voltage in the reset period of the first subfield. In the discharge cells that are not selected, there is no address discharge, so no discharge occurs.

In the subsequent reset period of the second subfield, the voltage Vh is applied to the sustain electrodes X1-Xn, and a ramp voltage that gradually decreases from the voltage Vq to 0V is applied to the scan electrodes Y1-Yn. That is, a voltage equal to the falling ramp voltage applied in the reset period of the first subfield is applied to the scan electrodes Y1-Yn. Then, a weak discharge occurs in the discharge cell selected in the first subfield, and no discharge occurs in the discharge cell that is not selected.

In the subsequent reset period of the remaining subfields, the same waveform as the reset period of the second subfield is applied. Meanwhile, in the eighth subfield, an erase period is formed after the sustain period. In the erase period, a ramp voltage that rises slowly from 0 V to the Ve voltage is applied to the sustain electrodes X1-Xn. The wall charges formed in the discharge cells are erased by this lamp voltage.

In this conventional driving waveform, since addressing is sequentially performed for all scan electrodes in the address period using the internal wall voltage, there is a problem that the internal wall voltage is lost in the scan electrode which is selected later. This loss of wall voltage eventually worsens the margin. Also, a waveform such as a reset period of the second subfield discharges only the cells selected in the previous subfield to form a wall charge state suitable for addressing, so that cells not selected in the previous subfield are selected after being not continuously selected. In this case, the wall voltage is lost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the related art, and to provide a method of driving a plasma display panel that can be addressed without using an internal wall voltage.                         

Another object of the present invention is to provide a method of driving a plasma display panel that prevents strong discharge that may occur in a reset period of a method of driving an addressable plasma display panel that does not use an internal wall voltage.

A driving method of a plasma display panel according to a feature of the present invention for achieving the above object is

A plurality of first electrodes and second electrodes formed side by side on a first substrate, and a plurality of third electrodes intersecting the first and second electrodes and formed on a second substrate; A driving method of a plasma display panel in which discharge cells are formed by a second electrode and a third electrode,
In reset period
(a) a first period in which the voltage gradually rises from the second voltage to the third voltage is applied to the first electrode while the second electrode is biased to the first voltage; Biasing the third electrode to a fourth voltage that is higher than the first voltage; And
(b) applying a voltage slowly falling from a fifth voltage to a sixth voltage to the first electrode after the rising voltage is applied;
The sixth voltage is substantially less than the negative value of the voltage corresponding to half of the difference between the voltage applied to the first electrode and the second electrode for sustain discharge in the sustain period.
Plasma display device according to another aspect of the present invention
First substrate,
A plurality of first electrodes and second electrodes formed on the first substrate, respectively;
A second substrate facing away from the first substrate,
A plurality of third electrodes formed on the second substrate in a direction crossing the first and second electrodes, and
A driving circuit for supplying a driving voltage to the first electrode, the second electrode, and the third electrode to discharge the discharge cells formed by the adjacent first, second, and third electrodes;
The driving circuit applies a voltage that rises slowly from the second voltage to the third voltage to the first electrode while biasing the second electrode to the first voltage,
Biasing the third electrode to a fourth voltage greater than the first voltage during a first period during which the rising voltage is applied;
Applying a voltage gently falling from the fifth voltage to the sixth voltage to the first electrode,
The sixth voltage is substantially less than the negative value of the voltage corresponding to half of the difference between the voltage applied to the first electrode and the second electrode for sustain discharge in the sustain period.

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DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a method of driving a plasma display panel according to a first embodiment of the present invention will be described in detail with reference to FIG. 4. In the following description, the reference numerals denoted by the address address electrodes A, the scan electrodes Y, and the sustain electrodes X indicate that the same voltage is applied to all the address electrodes, the scan electrodes, and the sustain electrodes. Indicated by Ai) and scan electrode Yj indicates that a corresponding voltage is applied to only part of the address electrode and scan electrode.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

As shown in Fig. 4, the driving waveform according to the first embodiment of the present invention includes a reset period, an address period, and a sustain period. Here, the driving method according to the first embodiment of the present invention is the same in that the waveform to which the reset period is applied as shown in FIG. 3 is different. In the plasma display panel, a scan / hold driving circuit (not shown) for applying a driving voltage to the scan electrode Y and the sustain electrode X in each period and an address for applying the driving voltage to the address electrode A are shown. A drive circuit (not shown) is connected. The driving circuit and the plasma display panel are connected to form one plasma display device.

In the reset period of the first subfield, a ramp voltage gradually rising from the Vrp voltage smaller than the discharge start voltage to the Vset voltage exceeding the discharge start voltage is first applied to the scan electrode Y. While this lamp voltage is applied, weak discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. By this discharge, negative wall charges are accumulated on the scan electrode Y, and positive wall charges are accumulated on the address electrode A and the sustain electrode X.

Next, a ramp voltage that gently falls from the Vg voltage to the Vn voltage is applied to the scan electrode Y. At this time, a reference voltage (assuming 0 V in FIG. 4) is applied to the address electrode A, and the sustain electrode X is biased with a Ve voltage. When the discharge start voltage between the address electrode and the scan electrode in the discharge cell is called Vfay voltage, the last voltage Vn of the falling ramp voltage is a voltage corresponding to -Vfay.

In general, when the voltage between the scan electrode and the address electrode or between the scan electrode and the sustain electrode is higher than the discharge start voltage in the discharge cell, discharge occurs between the scan electrode and the address electrode or between the scan electrode and the sustain electrode. In particular, when the ramp voltage is gently applied as in the first embodiment of the present invention and discharge occurs, the wall voltage inside the discharge cell is also reduced at the same rate as the ramp lamp voltage. Since this principle is described in detail in US Patent No. 5,745,086, detailed description thereof will be omitted.

Hereinafter, with reference to FIG. 5, the discharge characteristics when the ramp voltage falling down to the -Vfay voltage is applied.

5 is a diagram illustrating a relationship between a falling ramp voltage and a wall voltage when a falling ramp voltage is applied to a discharge cell. In FIG. 5, the scan electrode and the address electrode will be described, and a negative wall charge and a positive wall charge are accumulated on the scan electrode and the address electrode, respectively, before the falling ramp voltage is applied. Thus, a predetermined amount of the wall voltage Vo is formed. Assume that there is.

As shown in FIG. 5, the discharge occurs when the difference between the wall voltage Vwall and the voltage Vy applied to the scan electrode exceeds the discharge start voltage Vfay while the voltage applied to the scan electrode is slowly decreased. . As described above, when the discharge occurs, the wall voltage Vwall inside the discharge decreases at the same speed as the falling ramp voltage Vy. At this time, the difference between the falling ramp voltage Vy and the wall voltage Vwall maintains the discharge start voltage Vfay. Therefore, as shown in FIG. 5, when the voltage Vy applied to the scan electrode is reduced to the -Vfay voltage (which is the -Vf voltage), the wall voltage Vwall between the address electrode and the scan electrode in the discharge cell is 0V. do.

However, since the discharge start voltage is different depending on the characteristics of each discharge cell, in the first embodiment of the present invention, the voltage Vy applied to the scan electrode is changed from the address electrode A to the scan electrode Y in all the discharge cells. It can be made large enough to cause a discharge. In this case, all of the discharge cells include discharge cells in an area (effective display area) that may affect when displaying a screen on the plasma display panel.

That is, as shown in Equation 1, the difference VA-Yreset between the voltage 0V applied to the address electrode A and the voltage Vn applied to the scan electrode Y is the discharge start voltage Vfay among the discharge cells. It is made larger than the highest discharge start voltage (Vf, MAX, below maximum discharge start voltage). At this time, if the magnitude of the Vn voltage (Vn) is too large than the maximum discharge start voltage (Vf, MAX), a negative wall voltage is formed. Therefore, the magnitude of the Vn voltage (Vn) is a maximum discharge start voltage (Vf, MAX). Is the same as

In this way, when the ramp voltage falling down to the Vn voltage is applied to the scan electrode Y, wall charges are removed from all the discharge cells. When the magnitude (Vn) of the voltage Vn is set to the maximum discharge start voltage Vf, MAX, the discharge start voltage Vf is less than the maximum discharge start voltage Vf, MAX. Wall voltage can be generated. That is, negative wall charges may be formed on the address electrode A. FIG. At this time, the generated wall voltage becomes a voltage capable of solving the nonuniformity between the discharge cells in the address period.

Subsequently, in the address period, the scan electrode Y and the sustain electrode X are first maintained at the Vsch voltage and the Ve voltage, respectively, and then voltages are applied to the scan electrode Y and the address electrode A to select the discharge cells to be displayed. Is applied. That is, first, a negative voltage Vsc is applied to the scan electrode Y1 in the first row, and a positive voltage Va voltage is applied to the address electrode Ai located in the discharge cell to be displayed in the first row. do. In FIG. 4, the Vsc voltage was set at the same level as the Vn voltage in the reset period.

Then, as shown in Equation 2, the difference VA-Y, address between the address electrode Ai and the scan electrode Y1 in the selected discharge cell in the address period is always larger than the maximum discharge start voltage Vf, Max. You lose.

Therefore, in the discharge cells formed by the address electrode Ai to which the Va voltage is applied and the scan electrode Y1 to which the Vsc voltage is applied, between the address electrode Ai and the scan electrode Y1 and between the sustain electrode X1 and the scan electrode. An address discharge occurs between the electrodes Y1. As a result, positive wall charges are formed on the scan electrode Y1 and negative wall charges are formed on the sustain electrode X1. A negative wall charge is also formed at the address electrode Ai.

Next, while applying the Vsc voltage to the scan electrode Y2 in the second row, the Va voltage is applied to the address electrode Ai located in the discharge cell to be displayed in the second row. Then, as described above, an address discharge occurs in the discharge cell formed by the address electrode Ai to which the Va voltage is applied and the scan electrode Y2 to which the Vsc voltage is applied, thereby forming wall charges in the discharge cell. Similarly, the voltage Vc is applied to the address electrodes located in the discharge cells to be displayed while sequentially applying the Vsc voltage to the scan electrodes Y3-Yn in the remaining rows, thereby forming wall charges.

In the sustain period, the reference voltage (0 V) is applied to the sustain electrode X while applying the Vs voltage to the scan electrode Y first. Then, in the discharge cell selected in the address period, the positive wall charge and the sustain electrode Xj of the scan electrode Yj formed in the address period at the voltage between the scan electrode Yj and the sustain electrode Xj are at the Vs voltage. Since the wall voltage due to the negative wall charge of + is added, the discharge start voltage Vfxy between the scan electrode and the sustain electrode is exceeded. Therefore, sustain discharge occurs between scan electrode Yj and sustain electrode Xj. Negative wall charges and positive wall charges are formed on the scan electrode Yj and the sustain electrode Xj of the discharge cell in which the sustain discharge has occurred.

Next, 0 V is applied to the scan electrode Y, and a Vs voltage is applied to the sustain electrode X. In the discharge cell in which the sustain discharge has occurred previously, the positive wall charge and the scan electrode of the sustain electrode Xj formed by the sustain discharge before the voltage between the sustain electrode Xj and the scan electrode Yj are formed before the Vs voltage. Since the wall voltage due to the negative wall charge of Yj) is added, the discharge start voltage is exceeded. Therefore, sustain discharge occurs between the scan electrode Yj and the sustain electrode Xj, and the positive wall charge and the negative (-) are respectively applied to the scan electrode Yj and the sustain electrode Xj of the discharge cell in which the sustain discharge has occurred. Wall charges are formed.

Thereafter, the Vs voltage and 0V are alternately applied to the scan electrode Y and the sustain electrode X in the same manner, and sustain discharge is continued. In the last sustain pulse of the sustain period, the Vs voltage is applied to the scan electrode Y and the 0 V voltage is applied to the sustain electrode X. Then, in the selected discharge cell, discharge occurs from the scan electrode Yj to the sustain electrode Xj, and negative wall charges and positive wall charges are formed on the scan electrode Yj and the sustain electrode Xj, respectively.

Next, in the reset period of the second subfield, a ramp voltage that gradually falls from the Vg voltage to the Vn voltage is applied to the scan electrode Y after the last sustain pulse applied in the sustain period of the first subfield. At this time, as in the reset period of the first subfield, the reference voltage 0V is applied to the address electrode A, and the sustain electrode X is biased to the Ve voltage. That is, the same voltage as the falling ramp voltage applied in the reset period of the first subfield is applied to the scan electrode (Y). Then, weak discharge occurs in the discharge cell selected in the first subfield, and no discharge occurs in the discharge cell that is not selected. At this time, in the reset period of the second subfield, as in the reset period of the first subfield, the wall charge existing between the scan electrode Y and the address electrode A is completely erased. In other words, weak discharge occurs only in the cell selected in the first subfield by the reset period of the second subfield, and the wall charge existing between the scan electrode and the address electrode is completely erased.

Since the waveforms applied to the address period and the sustain period of the second subfield are the same as the first subfield, the description thereof will be omitted below. Here, the same waveform as the second subfield may be applied to the third subfield to the eighth subfield, and the same waveform as the first subfield is applied to any subfield among the third subfield to the eighth subfield. Can be.

Next, the relationship between the discharge start voltage Vfay between the address electrode and the scan electrode, the discharge start voltage Vfxy between the sustain electrode and the scan electrode, and the Vs voltage described in the first embodiment of the present invention will be described.

Discharge in a plasma display panel is determined by the amount of secondary electrons emitted when a cation strikes the cathode, which is called a process. Therefore, the discharge initiation voltage is higher when an electrode covered with a material having a higher secondary electron emission coefficient (γ) acts as a cathode than when an electrode covered with a material having a lower secondary electron emission coefficient (γ) serves as a cathode. low. However, in the three-electrode plasma display panel, the address electrode formed on the back substrate is covered with phosphor for color expression, and the scan electrode and sustain electrode formed on the front substrate are covered with dielectric layer formed of MgO for sustain discharge. Here, the dielectric layer of the MgO component has a high secondary electron emission coefficient while the phosphor layer has a low secondary electron emission coefficient. In addition, since the scan electrode and the sustain electrode are formed symmetrically, the address electrode and the scan electrode are formed asymmetrically, so that the discharge start voltage between the address electrode and the scan electrode acts as the anode and the cathode. May vary.

That is, the discharge start voltage Vfay when the address electrode covered with the phosphor serves as the anode and the scan electrode covered with the dielectric layer serves as the cathode is discharged when the address electrode serves as the cathode and the scan electrode serves as the anode. It is lower than the starting voltage Vfya. In general, between the discharge start voltage Vfay when the address electrode is the anode, the discharge start voltage Vfya when the address electrode is the cathode, and the discharge start voltage Vfxy between the scan electrode and the sustain electrode, The relationship is established. Of course, this relationship may vary depending on the state of the discharge cell.

In the reset period and the address period, since the scan electrode acts as the cathode, the discharge start voltage Vfay between the address electrode and the scan electrode is represented by the equation (4) from the relationship in the equation (3). Since the sustain discharge should not occur in the discharge cells not addressed in the address period, the Vs voltage is also lower than the discharge start voltage Vfxy between the scan electrode and the sustain electrode as shown in Equation (5).

In the first embodiment of the present invention, since the wall voltage between the address electrode and the scan electrode is close to 0 V in the reset period, in the discharge cells that are not addressed in the address period, between the scan electrode and the address electrode and the sustain electrode in the sustain period. Discharge should not occur continuously even between address electrodes. In other words, when discharge occurs continuously, Vs voltage is applied to the scan electrode to cause discharge between the scan electrode and the address electrode, and when the positive wall charge is formed on the address electrode, the Vs voltage is applied to the sustain electrode. This is a case where discharge occurs between the sustain electrode and the address electrode even when this is applied. However, since the sustain electrode and the scan electrode are symmetric electrodes, the discharge start voltage between the sustain electrode and the address electrode is equal to the Vfay voltage, and the sustain electrode is formed when positive wall charges are accumulated on the sustain electrode by the discharge of the scan electrode and the address electrode. The wall voltage formed on the and address electrodes cannot exceed the Vfay voltage. Therefore, in order that no discharge occurs when a positive wall charge is formed on the sustain electrode by the discharge between the scan electrode and the address electrode, when the Vs voltage is applied to the sustain electrode, the relationship of Equation 6, that is, the Vfay voltage is higher than the Vs / 2 voltage. Need to be big

In summary, the Vfay voltage needs to be set to a voltage higher than Vs / 2, and both Vfay and Vs voltages must be lower than a certain voltage than Vfxy voltage, so that the Vfay voltage is determined near the Vs voltage. Can be. In other words, the relationship as shown in equation (7) holds. As measured experimentally, ΔV has a voltage between 0 and 30V.

In FIG. 4, the Ve voltage applied to the sustain electrodes X1-Xn in the reset period and the address period is expressed as a positive voltage. The Ve voltage may be another voltage if a discharge can occur between the scan electrode Yj and the sustain electrode Xj by the discharge between the scan electrode Yj and the address electrode Ai in the address period. For example, the Ve voltage may be 0V or negative voltage.

As described above, according to the first embodiment of the present invention, by making the difference between the address electrode and the scan electrode of the discharge cell to be displayed in the address period larger than the maximum discharge start voltage, the address discharge occurs even when no wall charge is formed in the reset period. . Therefore, since the address discharge is not affected by the wall charges formed in the reset period, the problem of margin deterioration due to the loss of wall charges is eliminated.

Further, in the selected discharge cell, since the voltage difference between the address electrode A and the scan electrode Y can always be greater than Va above the maximum discharge start voltage, address discharge can occur regardless of the wall charge.

At this time, the Ve voltage is biased to the sustain electrode X while the ramp voltage gradually falling from the Vg voltage to the Vn voltage is applied to the scan electrode Y in the reset period. In general, the Ve voltage is selected to an appropriate value to set the wall voltage between the scan electrode Y and the sustain electrode Y to 0V after the reset period. Therefore, after the falling ramp voltage of the reset period is applied, the wall voltage between the scan electrode Y and the sustain electrode X is set to 0 V, and as in the first embodiment of the present invention, the scan electrode X and the address electrode A are The wall voltage of the yarn is also 0V, and all the wall charges are erased.

Thus, the wall voltage between the scan electrode Y and the sustain electrode X and the wall voltage between the scan electrode Y and the address electrode A are 0V through the waveform of the reset period in the first embodiment of the present invention. Becomes However, when the wall voltage becomes 0 V in this manner, strong discharge may occur in the subfield to which the ramp voltage that rises slowly is applied, such as the reset waveform of the first subfield shown in FIG. 4. Hereinafter, as in the first embodiment of the present invention, when the wall voltage between the scan electrode and the sustain electrode and the wall voltage between the scan electrode and the address electrode are all 0V, the reset period has a period for applying a ramp voltage that rises slowly. Find out why the strong discharge occurs.

In general, the discharge start voltage Vfyx between the scan electrode Y and the sustain electrode X is higher than the discharge start voltage Vfya between the scan electrode Y and the address electrode A. FIG. In addition, weak discharge occurs from the scan electrode Y to the sustain electrode X and the address electrode A when a ramp voltage which rises gently in the reset period of the first subfield shown in FIG. 4 is applied. Therefore, according to the reset waveform in the first embodiment of the present invention, the wall voltage between the scan electrode Y and the sustain electrode X and the wall voltage between the scan electrode Y and the address electrode A are reduced after the reset period. Since the voltage is set to 0 V, i.e., in the same wall voltage state, the discharge between the scan electrode Y and the address electrode A becomes the rising ramp voltage of the reset period of the first subfield so that the scan electrode Y and the sustain electrode ( Occurs before the discharge between X).

On the other hand, as described above, in the plasma display panel, the discharge is determined by the amount of secondary electrons emitted when a positive ion collides with the cathode, so that an electrode covered with a material having a low electron emission coefficient (γ) is negative. In the case of acting as a function, the discharge does not occur smoothly, and the timing at which the discharge occurs is delayed. By the way, in the three-electrode plasma display panel, the address electrode formed on the back substrate is covered with phosphor for color representation, and the scan electrode and sustain electrode formed on the front substrate are covered with dielectric layer formed of MgO for sustain discharge. Here, the dielectric layer of the MgO component has a high secondary electron emission coefficient while the fluorescent layer has a low secondary electron emission coefficient. Therefore, when the rising ramp voltage of the reset period is applied, the discharge start voltage between the scan electrode Y and the address electrode A is low, so that discharge occurs first (this is between the scan electrode and the address electrode and between the scan electrode and the sustain electrode). Since the wall voltage between the electrodes is 0 V) and the address electrode A covered with the phosphor acts as the cathode, the discharge does not occur smoothly, so that the discharge is delayed and the discharge occurs when a certain threshold is abnormal. However, since the time point at which discharge occurs between the scan electrode Y and the address electrode A exceeds the discharge start voltage between the scan electrode Y and the address electrode A, a strong discharge occurs.

That is, in the address period after the reset period as shown in FIG. 4, the ramp voltage that rises gently as in the reset waveform of the first subfield is not present in the unselected cells (the unselected cells maintain the wall charge state in the reset period). When applied, the discharge between the scan electrode Y and the address electrode A occurs earlier than the discharge between the scan electrode Y and the sustain electrode X to generate a strong discharge. In other words, when the wall voltage between the scan electrode and the address electrode and the wall voltage between the scan electrode and the address electrode are set to 0 V as shown in the reset waveform as shown in FIG. 4, in the rising ramp waveform of the reset period of the first subfield. Since discharge occurs first between the scan electrode and the address electrode, there is a problem that strong discharge occurs due to the above reason.

Hereinafter, as a method of solving the strong discharge generated in the first embodiment of the present invention, a method of causing a discharge to occur first between the scan electrode (Y) and the sustain electrode (Y) when the rising ramp waveform is applied in the reset period. Learn specifically.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention. As shown in Fig. 6, the driving waveform according to the second embodiment of the present invention applies a positive bias voltage to the address electrode A during a part of applying the ramp voltage which rises gently in the reset period. The method of driving the plasma display panel according to the second embodiment of the present invention is identical to the first embodiment of the present invention except that a positive bias voltage is applied to the address electrode A. Therefore, a description of overlapping portions is omitted. do.

When the wall voltage between the scan electrode Y and the sustain electrode X and the wall voltage between the scan electrode Y and the address electrode A are set to 0 V as shown in the reset waveform shown in FIG. Because of the voltage state, discharge occurs first between the scan electrode Y and the address electrode A in the rising ramp waveform of the reset period of the first subfield, so that a strong discharge occurs for the reasons described above. Therefore, according to the driving method of the plasma display panel according to the second embodiment of the present invention, in the rising ramp waveform of the reset period, the address electrode A is biased by a predetermined positive voltage, Since the voltage difference is biased at 0V, the voltage difference between the scan electrode Y and the address electrode A is smaller than the voltage difference between the scan electrode Y and the sustain electrode X, thereby suppressing the discharge between the two electrodes, The weak discharge first occurs between Y) and the storage electrode X.

As described above, by biasing the address electrode A to a predetermined positive voltage in the ramp waveform which rises gently in the reset period, the difference in the voltage between the scan electrode Y and the address electrode A becomes the scan electrode Y. The discharge between the scan electrode Y and the sustain electrode X may be earlier than the discharge between the scan electrode Y and the address electrode A in the reset period as the voltage difference between the and sustain electrodes X decreases. . Therefore, if a positive bias voltage is not applied to the address electrode A after the weak discharge between the scan electrode Y and the sustain electrode X, and the same 0V voltage as the sustain electrode X is applied, the scan electrode ( Discharge also occurs between Y) and the address electrode A. FIG. In this case, after priming particles are generated by the discharge between the scan electrode Y and the sustain electrode X, the weak discharge occurs even at the scan electrode Y and the address electrode A using the priming particles.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the wall charges formed in the reset period are not affected, the problem of deterioration of margin due to the loss of wall charges is eliminated.

In addition, the strong discharge that may occur in the reset period can be prevented by biasing the address electrode to a predetermined voltage at the beginning of the reset period having the gently rising section.

Claims (7)

A plurality of first electrodes and second electrodes formed side by side on a first substrate, and a plurality of third electrodes intersecting the first and second electrodes and formed on a second substrate; A driving method of a plasma display panel in which discharge cells are formed by a second electrode and a third electrode, In reset period (a) a first period in which the voltage gradually rises from the second voltage to the third voltage is applied to the first electrode while the second electrode is biased to the first voltage; Biasing the third electrode to a fourth voltage that is higher than the first voltage; And (b) applying a voltage slowly falling from a fifth voltage to a sixth voltage to the first electrode after the rising voltage is applied; And the sixth voltage is substantially less than a negative value of a voltage corresponding to half of a difference between voltages applied to the first electrode and the second electrode for sustain discharge in the sustain period. . The method of claim 1, And the sixth voltage is substantially equal to or less than a negative value of a voltage corresponding to a difference between a voltage applied to the first electrode and the second electrode for the sustain discharge in the sustain period. The method of claim 1, And the sixth voltage is substantially equal to or less than a negative value of a discharge start voltage between the first electrode and the third electrode. The method of claim 1, And in step (a), biasing the third electrode to the first voltage during a second period during which the rising voltage is applied after the first period. First substrate, A plurality of first electrodes and second electrodes formed on the first substrate, respectively; A second substrate facing away from the first substrate, A plurality of third electrodes formed on the second substrate in a direction crossing the first and second electrodes, and A driving circuit for supplying a driving voltage to the first electrode, the second electrode, and the third electrode to discharge the discharge cells formed by the adjacent first, second, and third electrodes; The driving circuit applies a voltage that rises slowly from the second voltage to the third voltage to the first electrode while biasing the second electrode to the first voltage, Biasing the third electrode to a fourth voltage greater than the first voltage during a first period during which the rising voltage is applied; Applying a voltage gently falling from the fifth voltage to the sixth voltage to the first electrode, And the sixth voltage is substantially less than a negative value of a voltage corresponding to half of a difference between voltages applied to the first electrode and the second electrode for sustain discharge in the sustain period. The method of claim 5, The driving circuit discharges a discharge cell to be selected among the discharge cells during an address period, sustain discharges the selected cell during a sustain period, And the sixth voltage is substantially equal to or less than a negative value of a voltage corresponding to a difference between the voltage applied to the first electrode and the second electrode for sustain discharge during the sustain period. The method according to claim 5 or 6, And biasing the third electrode to the first voltage during a second period during which the rising voltage is applied after the first period.

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