KR100521472B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

A method of driving a plasma display panel, wherein the voltage of a first electrode is gradually increased from a first voltage to a second voltage before a reset period, and then the first electrode is biased with a third voltage. The voltage of is gradually decreased from the fourth voltage to the fifth voltage. In the reset period, after the voltage of the first electrode is gradually increased from the sixth voltage to the seventh voltage, the voltage of the first electrode is increased from the ninth voltage with the second electrode biased to the eighth voltage. Incrementally decreases to the tenth voltage. At this time, the difference between the third voltage and the fifth voltage is greater than the difference between the eighth voltage and the tenth voltage. In this way, it is possible to prevent low discharge that may occur when control cannot be performed only by the reset operation in the reset period.

Description

Plasma display panel driving method and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

The present invention relates to a method of driving a plasma display panel (PDP).

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, a structure of a general plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. In the column direction, address electrodes A ₁ -A _m are arranged, and in the row direction, n rows of scan electrodes Y ₁ -Y _n and sustain electrodes X ₁ -X _n are arranged in pairs.

As a method of driving a conventional plasma display panel, there is a method described in US Pat. No. 6,294,875 to Kurata et al. The driving method of '875 is a method of dividing one waveform into eight subfields and then different waveforms applied in the reset period of the first subfield and the second to eighth subfields.

As shown in Fig. 3, each subfield includes a reset period, an address period, and a sustain period. In the reset period of the first subfield, a ramp voltage gradually rising from the V _p voltage smaller than the discharge start voltage to the V _r voltage exceeding the discharge start voltage is first applied to the scan electrodes Y ₁ -Y _n . While this ramp voltage is rising, weak discharge occurs from the scan electrodes Y ₁ -Y _n to the address electrodes A ₁ -A _m and the sustain electrodes X ₁ -X _n , respectively. By this discharge, negative wall charges are accumulated on the scan electrodes Y ₁ -Y _n , and positive wall charges are stored on the address electrodes A ₁ -A _m and the sustain electrodes X ₁ -X _n . Referring to FIG. 1, wall charges are formed on the surface of the protective film 3 of the scan electrode 4 and the sustain electrode 5, but are described below as being formed on the scan electrode 4 and the sustain electrode 5 for convenience of description.

Subsequently, a ramp voltage gently falling to 0 V is applied to the scan electrodes Y ₁ -Y _n at a voltage V _q lower than the discharge start voltage. Then, the ramp voltage is weak from the sustain electrodes X _1- X _n and the address electrodes A ₁ -A _m to the scan electrodes Y ₁ -Y _{n due} to the wall voltage formed in the discharge cells. Discharge occurs. This discharge partially erases wall charges formed in the sustain electrodes X ₁ -X _n , the scan electrodes Y ₁ -Y _n , and the address electrodes A ₁ -A _m , and sets them to a state suitable for addressing. do. Similarly, referring to FIG. 1, wall charges are formed on the surface of the insulator layer 7 of the address electrode 8, but are represented below as being formed on the address electrode 8 for convenience of description.

Next, in the address period, a positive voltage V _w is applied to the address electrodes A ₁ -A _m of the discharge cells to be selected, and 0 V is applied to the scan electrodes Y ₁ -Y _n . Then, between the address electrodes A ₁ -A _m and the scan electrodes Y ₁ -Y _n and the sustain electrodes X ₁ -X _n by the wall voltage and the positive voltage V _w caused by the wall charges formed in the reset period. ) And the address electrodes Y ₁ -Y _n occur. This discharge accumulates positive wall charges in the scan electrodes Y ₁ -Y _n and negative wall charges in the sustain electrodes X ₁ -X _n and the address electrodes A ₁ -A _m . In the discharge cells in which the wall charges are accumulated by the address discharge, sustain discharge occurs by a sustain pulse applied in the sustain period.

Next, the voltage level of the last sustain pulse applied to the scan electrodes Y _1- Y _n in the sustain period of the first subfield is equal to the voltage of V _r in the reset period, and V is applied to the sustain electrodes X ₁ -X _n . _The voltage V _r -V _s corresponding to the difference between the _r voltage and the sustain voltage V _s is applied. Then, in the discharge cells selected in the address period, discharge occurs from the scan electrodes Y ₁ -Y _n to the address electrodes A ₁ -A _m by the wall voltage formed by the address discharge, and the scan electrodes Y ₁ -Y _n. Sustain discharge (X ₁ -X _n ) is generated from? This discharge corresponds to the discharge generated by the rising ramp voltage in the reset period of the first subfield. In the discharge cells that are not selected, there is no address discharge, so no discharge occurs.

In the subsequent reset period of the second subfield, a voltage V _h is applied to the sustain electrodes X _1- X _n , and a ramp voltage gently falling from the voltage V _q to 0 V is applied to the scan electrodes Y ₁ -Y _n . . That is, a voltage equal to the falling ramp voltage applied in the reset period of the first subfield is applied to the scan electrodes Y ₁ -Y _n . Then, a weak discharge occurs in the discharge cell selected in the first subfield, and no discharge occurs in the discharge cell that is not selected.

In the subsequent reset period of the remaining subfields, the same waveform as the reset period of the second subfield is applied. Meanwhile, in the eighth subfield, an erase period is formed after the sustain period. In the erase period, a ramp voltage that rises slowly from 0 V to V _e is applied to the sustain electrodes X _1- X _n . The wall charges formed in the discharge cells are erased by this lamp voltage.

In such a conventional drive waveform, since addressing in the address period using the internal wall voltage is performed sequentially for all the scan electrodes, there is a problem that the internal wall voltage is lost in the scan electrode which is selected later. This loss of wall voltage eventually worsens the margin.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of driving a plasma display panel that can reduce and address an internal wall voltage dependency.

Another object of the present invention is to provide a method of driving a plasma display panel, which reduces the reset period by lowering a voltage at which discharge occurs in a falling reset period of a method of driving a plasma display panel that can be addressed without using an internal wall voltage.

According to an aspect of the present invention, each of the plurality of subfields forming one frame includes a reset period, an address period, and a sustain period, and drives a plasma display panel in which discharge cells are formed by the first electrode and the second electrode. A method is provided. In this driving method, before the reset period, the voltage of the first electrode is gradually increased from the first voltage to the second voltage, and then the second electrode is biased to the third voltage. Is gradually decreased from the fourth voltage to the fifth voltage, and in the reset period, the voltage of the first electrode is gradually increased from the sixth voltage to the seventh voltage, and then the second electrode is moved to the eighth voltage. Gradually decreasing a voltage of the first electrode from a ninth voltage to a tenth voltage in a biased state, wherein a difference between the third voltage and the fifth voltage is equal to that of the eighth voltage and the tenth voltage. Is greater than the difference. In this case, the fifth voltage may be the same voltage as the tenth voltage, and the third voltage may be the same voltage as the eighth voltage. The third voltage may be a voltage equal to a higher voltage among voltages applied to the second electrode for sustain discharge in the sustain period.

And a difference between the tenth voltage and the voltage applied to the third electrode while the voltage of the first electrode decreases to the tenth voltage is equal to the first electrode and the second electrode for the sustain discharge in the sustain period. It may be equal to or less than a negative value of a voltage corresponding to 1/2 of a voltage difference applied to an electrode, and is applied to the third electrode while the voltage of the tenth voltage and the first electrode are reduced to the tenth voltage. The difference in voltage may be equal to or less than a negative value of a voltage corresponding to a voltage difference applied to the first electrode and the second electrode for the sustain discharge in the sustain period.

According to another feature of the invention, a plasma display panel in which discharge cells are formed between a first electrode, a second electrode, and a third electrode, and the first electrode, the second during a reset period, an address period, and a sustain period. A plasma display device including an electrode and a driving circuit for applying a driving voltage to the third electrode is provided. In this case, the driving circuit gradually increases the voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode from the first voltage to the second voltage before the reset period, and then gradually increases from the third voltage to the fourth voltage. In the reset period, the voltage from the voltage of the first electrode minus the voltage of the second electrode is gradually increased from the fifth voltage to the sixth voltage and then gradually decreased from the seventh voltage to the eighth voltage, The fourth voltage is greater than the seventh voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a method of driving a plasma display panel according to a first embodiment of the present invention will be described in detail with reference to FIG. 4. In the following description, reference numerals denoted by the address electrodes A ₁ -A _m , the scan electrodes Y ₁ -Y _n , and the sustain electrodes X ₁ -X _n denote the address electrodes, the scan electrodes, and the sustain electrodes. The same voltage is applied, and the display of the address electrode A _i and the scan electrode Y _j indicates that only a portion of the address electrode and the scan electrode are applied.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

As shown in Fig. 4, the drive waveform according to the first embodiment of the present invention includes a reset period, an address period, and a sustain period. In the plasma display panel, a scan / hold driving circuit (not shown) and an address electrode A ₁ -which apply driving voltages to the scan electrodes Y ₁ -Y _n and the sustain electrodes X ₁ -X _n in each period. An address driving circuit (not shown) for applying a driving voltage to A _m ) is connected. The driving circuit and the plasma display panel are connected to form one plasma display device.

The reset period is a period in which the wall charges formed in the sustain period are removed, and in the reset period of the first subfield, a main reset waveform is applied to remove and accumulate wall charges in all discharge cells and reset the subfield after the second subfield. In the period, an auxiliary reset waveform is applied to remove only wall charges of the discharge cells in which the discharge occurred in the previous subfield by removing the wall charges without accumulating the wall charges in the discharge cells. The address period is a period for selecting a discharge cell to be displayed among the discharge cells, and the sustain period is a period for discharging the discharge cell selected in the address period.

First, in the reset period of the first subfield, a ramp voltage gradually rising from the Vs voltage to the Vset voltage exceeding the discharge start voltage is applied to the scan electrode Y in the period during which the main reset is applied. While this lamp voltage is applied, weak discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. By this discharge, negative wall charges are accumulated on the scan electrode Y, and positive wall charges are accumulated on the address electrode A and the sustain electrode X.

Next, a ramp voltage gradually decreasing from the Vs voltage to the Vnf voltage is applied to the scan electrode Y. At this time, a reference voltage (assuming 0 V in FIG. 4) is applied to the address electrode A, and the sustain electrode X is biased to the Ve voltage. In general, the difference Ve-Vnf between the scan electrode Y and the sustain electrode X is different from the scan electrode Y in order to prevent the cells without address discharge in the address period from being erroneously discharged in the sustain period. It is set near the discharge start voltage Vaxy between the sustain electrodes X. As a result, the wall voltage between the scan electrode Y and the sustain electrode X becomes almost 0 V to prevent such an erroneous discharge.

Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage. When the discharge start voltage between the address electrode and the scan electrode in the discharge cell is called Vfay voltage, the last voltage Vnf of the falling ramp voltage is a voltage corresponding to -Vfay.

In general, when the voltage between the scan electrode and the address electrode or between the scan electrode and the sustain electrode is higher than the discharge start voltage in the discharge cell, discharge occurs between the scan electrode and the address electrode or between the scan electrode and the sustain electrode. In particular, when the ramp voltage is gently applied as in the first embodiment of the present invention and discharge occurs, the wall voltage inside the discharge cell is also reduced at the same rate as the ramp lamp voltage. Since this principle is described in detail in US Patent No. 5,745,086, detailed description thereof will be omitted.

_Hereinafter , with reference to FIG. 5, the discharge characteristics when the ramp voltage falling down to the -V _fay voltage is applied will be described.

5 is a diagram illustrating a relationship between a falling ramp voltage and a wall voltage when a falling ramp voltage is applied to a discharge cell. In FIG. 5, the scan electrode and the address electrode will be described, and a negative charge and a positive charge are accumulated on the scan electrode and the address electrode, respectively, before the falling ramp voltage is applied, so that a certain amount of wall voltage V ₀ is formed. Assume that

As shown in FIG. 5, when the difference between the wall voltage V _wall and the voltage V _y applied to the scan electrode exceeds the discharge start voltage V _fay while the voltage applied to the scan electrode is slowly decreased. Discharge occurs. As described above, when discharge occurs, the wall voltage V _wall inside the discharge cell decreases at the same speed as the falling ramp voltage V _y . In this case, the difference between the falling ramp voltage V _y and the wall voltage V _wall maintains the discharge start voltage V _fay . Therefore, as shown in FIG. 5, when the voltage V _y applied to the scan electrode decreases to the -V _fay voltage, the wall voltage V _wall between the address electrode and the scan electrode in the discharge cell becomes 0V.

However, since the discharge start voltage is different depending on the characteristics of each discharge cell, in the first embodiment of the present invention, the voltage V _y applied to the scan electrodes is determined from the scan electrodes from the address electrodes A ₁ -A _m in all the discharge cells. (Y ₁ -Y _n ) can be made large enough to cause a discharge. In this case, all of the discharge cells include discharge cells in an area (effective display area) that may affect when displaying a screen on the plasma display panel.

That is, as shown in Equation 1, the difference between the voltage 0V applied to the address electrodes A ₁ -A _m and the voltage V _nf applied to the scan electrodes Y ₁ -Y _n (V _{AY, reset} ) Among the discharge cells, the discharge start voltage V _fay is greater than the discharge start voltage (V _{f, MAX} , hereinafter referred to as 'maximum discharge start voltage') of the highest. At this time, if the magnitude of the voltage V _nf (| V _nf |) is too large than the maximum discharge initiation voltage (V _{f, MAX} ) _{, a} negative wall voltage is formed. Therefore, the magnitude of the voltage V _nf (| V _nf |) is the maximum discharge initiation. It is preferable that the voltage V _{f and MAX} be the same.

As such, when a ramp voltage that drops to the Vnf voltage is applied to the scan electrodes Y ₁ -Y _n , the wall voltage is removed from all the discharge cells. If the magnitude of the Vnf voltage (| Vnf |) is set to the maximum discharge start voltage (V _{f, MAX} ), the discharge start voltage (V _f ) is negative in the discharge cell smaller than the maximum discharge start voltage (V _{f, MAX} ). Wall voltage can be generated. That is, negative wall charges may be formed on the address electrodes A ₁ -A _m and negative wall charges may be formed on the scan electrodes Y ₁ -Y _n . At this time, the generated wall voltage becomes a voltage capable of solving the nonuniformity between the discharge cells in the address period.

Subsequently, in the address period, the scan electrodes Y ₁ -Y _n and the sustain electrodes X ₁ -X _n are _first maintained at the reference voltage (0 V) and the V _e voltage, respectively, and then scanned to select the discharge cells to be displayed. Voltages are applied to the electrodes Y ₁ -Y _n and the address electrodes A ₁ -A _m . That is, first, the negative voltage VscL is applied to the scan electrode Y ₁ of the first row, and the positive voltage VscH is applied to the address electrode A _i located in the discharge cell to be displayed in the first row. Is authorized. In Fig. 4, the VscL voltage is set at the same level as the Vnf voltage in the reset period.

Then, as shown in Equation 2, the difference between the voltage V _{AY and address} of the address electrode A _i and the scan electrode Y ₁ in the selected discharge cell in the address period is always the maximum discharge start voltage V _f , _MAX . It becomes bigger.

Therefore, in the discharge cell formed by the address electrode A _{i to} which the VscH voltage is applied and the scan electrode Y _{1 to} which the VscL voltage is applied, between the address electrode A _i and the scan electrode Y ₁ and the sustain electrode ( An address discharge occurs between X ₁ ) and the scan electrode Y ₁ . As a result, positive wall charges are formed on the scan electrode Y ₁ and negative wall charges are formed on the sustain electrode X ₁ . A negative wall charge is also formed on the address electrode A _i .

Next, while applying the VscL voltage to the scan electrode Y _{2 of} the second row, the VscH voltage is applied to the address electrode A _i located in the discharge cell to be displayed in the second row. Then, as described above, the address discharge occurs in the discharge cell formed by the address electrode A _i to which the VscH voltage is applied and the scan electrode Y _{2 to} which the VscL voltage is applied, thereby forming wall charges in the discharge cell. Similarly, the VscH voltage is applied to the address electrodes positioned in the discharge cells to be displayed while sequentially applying the VscL voltage to the scan electrodes Y ₃ -Y _n in the remaining rows, thereby forming wall charges.

In the sustain period, first, the reference voltage (0V) is applied to the sustain electrodes (X ₁ -X _n ) while applying the V _s voltage to the scan electrodes (Y ₁ -Y _n ). Then, in the discharge cell selected in the address period, the positive wall charge and the sustain electrode X of the scan electrode Y _j formed in the address period at the voltage between the scan electrode Y _j and the sustain electrode X _j are at the voltage V _{s. Since} the wall voltage due to the negative wall charge of _j ) is added, the discharge start voltage V _fxy between the scan electrode and the sustain electrode is _exceeded . Therefore, sustain discharge occurs between scan electrode Y _j and sustain electrode X _j . A negative wall charge and a positive wall charge are formed in the scan electrode Y _j and the sustain electrode X _j of the discharge cell in which the sustain discharge has occurred.

The next scanning electrode (Y ₁ -Y _n) 0V is applied is applied with a voltage V _s to the sustain electrodes (X ₁ -X _n). In the discharge cell in which the sustain discharge has occurred previously, the positive wall charge and the scan electrode of the sustain electrode X _j formed at the sustain discharge before the voltage between the sustain electrode X _j and the scan electrode Y _j are equal to the voltage V _s. Since the wall voltage due to the negative wall charge of (Y _j ) is added, the discharge start voltage V _fxy between the scan electrode and the sustain electrode is _exceeded . Therefore, the scan electrode occurs and the sustain discharge between (Y _j) and the sustain electrode (X _j), maintaining the scan electrode of the discharge cell the discharge takes place (Y _j) and the sustain electrode (X _j), the respective amounts of the wall charges and the negative Wall charges are formed.

Thereafter, in the same manner, the voltage V _s and 0 V are alternately applied to the scan electrodes Y ₁ -Y _n and the sustain electrodes X ₁ -X _n to continue sustain discharge. The last sustain discharge occurs in a state where a voltage V _s is applied to the scan electrodes Y ₁ -Y _n and 0 V is applied to the sustain electrodes X ₁ -X _n . After the last sustain discharge, subfields starting from the reset period described above are continued.

Next, in the reset period of the second subfield, a ramp that gently drops from the voltage Vs to the voltage Vnf to the scan electrode Y after the last sustain pulse applied in the sustain period of the first subfield to the period during which the auxiliary reset is applied. Voltage is applied. At this time, as in the reset period of the first subfield, the reference voltage 0V is applied to the address electrode A, and the sustain electrode X is biased to the Ve voltage. That is, the same voltage as the falling ramp voltage applied in the reset period of the first subfield is applied to the scan electrode (Y). Then, weak discharge occurs in the discharge cell selected in the first subfield, and no discharge occurs in the discharge cell that is not selected. At this time, in the reset period of the second subfield as in the reset period of the first subfield, the wall charge existing between the scan electrode Y and the address electrode A is completely erased. In other words, weak discharge occurs only in the cell selected in the first subfield by the reset period of the second subfield, and the wall charge existing between the scan electrode and the address electrode is completely erased.

Since the waveforms applied to the address period and the sustain period of the second subfield are the same as the first subfield, the description thereof will be omitted below. Here, the same waveform as the second subfield may be applied to the third subfield to the eighth subfield, and the same waveform as the first subfield is applied to any subfield among the third subfield to the eighth subfield. Can be.

As described above, according to the first embodiment of the present invention, by making the voltage difference between the address electrode and the scan electrode of the discharge cell to be displayed in the address period larger than the maximum discharge start voltage, the address discharge is not generated even in the reset period. Happens. Therefore, since the address discharge is not affected by the wall charges formed in the reset period, the problem of margin deterioration due to the wall charges disappears.

In the first embodiment of the present invention, the VscL voltage and the Vnf voltage can be supplied from the same power supply, so that the circuit for driving the scan electrode is simplified.

In the first embodiment of the present invention, the reference voltage is assumed to be 0 V. However, the reference voltage may be another voltage. And Va voltage and VscL If the voltage difference can be made larger than the maximum discharge start voltage, the VscL voltage may be different from the Vnf voltage.

Next, the relationship between the discharge start voltage V _fay between the address electrode and the scan electrode, the discharge start voltage V _fxy and the V _s voltage between the sustain electrode and the scan electrode described in the first embodiment of the present invention will be described. do.

Discharge in a plasma display panel is determined by the amount of secondary electrons emitted when a cation strikes the cathode, It is called a process. Therefore, the secondary electron emission coefficient ( Secondary electron emission coefficient ( The discharge initiation voltage is lower when the electrode covered with the lower substance acts as the cathode. By the way, in the three-electrode plasma display panel, the address electrode formed on the rear substrate is covered with phosphor for color expression, and the scan electrode and sustain electrode formed on the front substrate are covered with a protective film of MgO component. The MgO passivation layer has a high secondary electron emission coefficient while the phosphor layer has a low secondary electron emission coefficient. In addition, since the scan electrode and the sustain electrode are formed symmetrically, the address electrode and the scan electrode are formed asymmetrically, so that the discharge start voltage between the address electrode and the scan electrode acts as the anode and the cathode. May vary.

That is, the discharge start voltage V _fay when the address electrode covered with the phosphor acts as the anode and the scan electrode covered with the dielectric layer acts as the cathode is used when the address electrode acts as the cathode and the scan electrode acts as the anode. It is lower than the discharge start voltage V _fya . And generally between the address electrodes, the discharge initiation voltage (V _fay) when the positive electrode, the starting discharge when the address electrode is the cathode voltage (V _fya) and the scan electrodes and the sustain start discharge between the electrode voltage (V _fxy) mathematics Equation 3 holds. Of course, this relationship may vary depending on the state of the discharge cell.

In the reset period and the address period, since the scan electrode acts as the cathode, the discharge start voltage V _fay between the address electrode and the scan electrode is represented by the equation (4) from the relationship in the equation (3). Since the sustain discharge should not occur in the discharge cells not addressed in the address period, the V _s voltage is also lower than the discharge start voltage V _fxy between the scan electrode and the sustain electrode as shown in Equation (5).

In the first embodiment of the present invention, since the wall voltage between the address electrode and the scan electrode is close to 0 V in the reset period, in the discharge cells that are not addressed in the address period, between the scan electrode and the address electrode and the sustain electrode in the sustain period. Discharge should not occur continuously even between address electrodes. In other words, when discharge occurs continuously, V _s voltage is applied to the scan electrode to cause discharge between the scan electrode and the address electrode, and when the positive wall charge is formed on the address electrode, V _{s is} applied to the sustain electrode. The discharge occurs between the sustain electrode and the address electrode even when a voltage is applied. However, since the sustain electrode and the scan electrode are symmetrical electrodes, the discharge start voltage between the sustain electrode and the address electrode is equal to the V _fay voltage, and is maintained when positive wall charges are accumulated on the sustain electrode by the discharge of the scan electrode and the address electrode. The wall voltage formed on the electrode and the address electrode cannot exceed the V _fay voltage. Therefore, in order that no discharge occurs when the voltage V _s is applied to the sustain electrode after the positive wall charge is formed on the sustain electrode by the discharge between the scan electrode and the address electrode, the relationship of Equation 6, that is, the V _fay voltage is V _s / Need to be greater than 2 voltages.

Based on these relations given by the expressions 4 to 6, V _fay voltage V _s / 2, and more needs to be set to a high voltage, and therefore lower than the constant voltage than V _fxy voltage both V _fay voltage and V _s the voltage V _fay voltage Can be determined near the V _s voltage. In other words, the relationship as shown in equation (7) holds. When measured by experiment Has a voltage between 0 and 30V.

In the first embodiment of the present invention, the voltage applied to the address electrode in the reset period is described as 0 V. However, the wall voltage between the address electrode and the scan electrode is determined by the difference between the voltages applied to the address electrode and the scan electrode. Therefore, if the difference between the voltage applied to the address electrode and the scan electrode satisfies the same relationship as in the embodiment of the present invention, the voltage applied to the address electrode and the scan electrode can be set differently.

In the first embodiment of the present invention, a voltage in the form of a lamp is applied to the scan electrode in the reset period. However, in addition to the lamp, another type of voltage capable of controlling wall charge while generating a weak discharge is applied to the scan electrode. May be authorized. This type of voltage is a voltage whose voltage level changes gradually over time.

Thus, according to the present invention, since the address discharge is not affected by the wall charges formed in the reset period, the problem of margin deterioration due to the wall charges disappears. Since the amount of discharge in the reset period is reduced in the discharge cells that do not emit light, the contrast ratio is improved.

On the other hand, in general, since all types of discharge cells must be initialized in the reset period, the difference between the highest voltage and the lowest voltage applied during the reset period is set to (Vfay + Vfya) or more. That is, in the driving waveform of Fig. 4, the difference between the Vset voltage which is the highest voltage and the -Vnf voltage which is the lowest voltage in the reset period is set to (Vfay + Vfya) voltage or more. The voltage between the internal electrodes of a discharge cell that remains stable at a given externally applied voltage is determined by the sum of the externally applied voltage and the wall voltage, -Vfya and Vfay. Has a voltage between the voltages. Therefore, in order to generate a discharge in all the discharge cells, a voltage variation of (Vfay + Vfya) voltage must be applied between the scan electrode and the address electrode. That is, when (Vfay + Vfya) voltage or more external voltage is applied, since the external voltage can make the voltage between the internal electrodes more than the discharge start voltage at any polarity together with the wall voltage, the initializing discharge is Can happen.

However, in the first embodiment of the present invention, the voltage of the address electrode is maintained at 0 V during the reset period, and the maximum Vset voltage and the minimum Vnf voltage are applied to the scan electrode. Therefore, the voltage applied in the reset period must satisfy the following equation.

However, in the first embodiment of the present invention, the voltage Vnf is a negative voltage and the magnitude of the voltage Vnf (| Vnf |) is set to the discharge start voltage Vfay or more. Therefore, the voltage Vset, which is the maximum voltage applied to the scan electrodes in the reset period, can be lowered to a voltage larger than Vfya.

6 is a driving waveform diagram of the plasma display panel according to the second embodiment of the present invention.

Meanwhile, as shown in FIG. 6, when the rising reset final voltage is lowered to the voltage Vset ', the difference between the voltage Vset' and the voltage Vs becomes smaller than the difference between the voltage Vset and the voltage Vs, thereby shortening the wall charge accumulation period in the reset period. In the rising reset period, sufficient wall voltage may not be formed on the scan electrodes.

Therefore, in order to solve this disadvantage, in the third embodiment of the present invention, wall charges of all cells are formed to a level at which sustain discharge can occur without an address discharge before the reset period, thereby lowering the voltage at which wall charges begin to accumulate in the rising reset period. give. Hereinafter, such an embodiment will be described in detail with reference to FIG. 7.

7 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

As shown in FIG. 7, the driving waveform according to the third embodiment of the present invention applies one or more periods of forming the wall charges of all cells (hereinafter, referred to as 'all cell wall charge forming periods') before the reset period. .

The full cell wall charge forming period includes a rising period and a falling period. The rising period maintains the address electrode A and the sustain electrode X at the reference voltage as in the rising reset period of the reset period, and applies a ramp voltage gradually rising from the voltage Vs to the voltage Vset 'to the scan electrode Y. do. While this lamp voltage is applied, weak discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. By this discharge, negative wall charges are accumulated on the scan electrode Y, and positive wall charges are accumulated on the address electrode A and the sustain electrode X.

Next, a ramp voltage gradually decreasing from the Vs voltage to the Vnf voltage is applied to the scan electrode Y. At this time, a reference voltage is applied to the address electrode A, and the sustain electrode X is biased to the voltage Vb. At this time, the voltage Vb is higher than the final voltage Ve in the falling reset period.

As can be seen from Equation 9, in the falling period of the all-cell wall charge formation period, the magnitude of the final applied voltage between the scan electrode Y and the sustain electrode X is the scan electrode Y and the sustain electrode in the falling reset period of the reset period. It is greater than the magnitude of the final applied voltage between (X). And Vb The size of | Vb-Vnf | is such that discharge can occur even if a sustain pulse is applied immediately after the full cell wall charge formation period.

Specifically, | Ve-Vnf | is set near the discharge start voltage V _fxy between scan electrode Y and sustain electrode X as described above. Therefore, | Vb-Vnf | becomes more than discharge start voltage _Vfxy . That is, the discharge start voltage V _fxy is negative and the magnitude of the final applied voltage between the scan electrode Y and the sustain electrode X falls below the discharge start voltage. Accordingly, positive wall charges are formed on the scan electrode Y, and negative wall charges are formed on the address electrode A and the sustain electrode X, thereby increasing the wall voltage. As a result, even if the sustain pulse is applied immediately after the same role as the address discharge in the address period, the discharge occurs.

Therefore, when the rising waveform is applied in the reset period after the full cell wall charge formation period, positive and negative wall charges are formed on the scan electrode Y and the sustain electrode X, respectively, in the full cell wall charge formation period. Vs to scan electrode Y in state Vset 'in voltage Since a ramp voltage that rises slowly to the voltage is applied, discharge can occur quickly.

In FIG. 7, the final voltage Vnf of the scan electrode Y is shown as the same voltage as the final voltage Vnf of the falling reset period in the falling period of the all-cell wall charge formation period, but may be different. However, if the final voltage Vnf of the scan electrode Y is applied in the same manner as the final voltage Vnf of the falling reset period, the number of power sources can be reduced.

If it is assumed that the final voltage Vnf of the scan electrode Y is applied in the same manner as the final voltage Vnf of the falling reset period, the Vb voltage must be greater than the Ve voltage and the Vb voltage is within a range satisfying Equation (9). It can also be set to Vs voltage. This can further reduce the number of power supplies.

In addition, assuming that the voltage Vb is equal to the voltage Ve, the final voltage Vnf of the scan electrode Y may be further lowered in the falling period of the all-cell wall charge formation period.

As such, if the full cell wall charge formation period is provided before the reset period, the wall charges accumulate on the scan electrode in the reset period due to the positive and negative wall charges formed on the scan electrode and the sustain electrode, respectively, during the full cell wall charge formation period. The starting voltage can be lowered. As a result, it is possible to lower the voltage Vset 'which is the final voltage of the rising reset period.

If the full cell wall charge formation period is placed in front of the reset period, the resting period is driven before the reset period of the subfield after the long subfield, and then goes through a long rest period due to lack of priming in the discharge space or loss of wall charge between electrodes. It is possible to prevent the low discharge problem that may occur when the wall charges cannot be controlled only by the reset operation of the reset period. In addition, since the driving waveform in the all-cell wall charge formation period is similar to the driving waveform in the reset period, the driving circuit for generating the driving waveform of the plasma display panel can generate the driving waveform in the all-cell wall charge formation period without changing the circuit. .

Further, the full cell wall charge formation period can be applied to all driving waveforms of the plasma display panel, and the first subfield of the plurality of subfields forming one frame as well as before the reset period of the subfield after the subfield having a long rest period. It can also be placed before the main reset period of.

 Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since it is not affected by the wall charges formed in the reset period, the problem of deterioration of the margin due to the loss of the wall charges is eliminated. The reset period can be shortened by lowering the reset rising final voltage and the reset falling start voltage. In addition, it is possible to prevent low discharge that may occur when it is not possible to control only by the reset operation of the reset period, and the waveform capable of preventing such low discharge can be driven without changing the circuit, so there is no additional cost in terms of cost.

1 is a partial perspective view of a typical plasma display panel.

2 shows an electrode arrangement diagram of a typical plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

5 is a diagram illustrating a relationship between a falling ramp voltage and a wall voltage when a falling ramp voltage is applied to a discharge cell.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

7 is a driving waveform diagram of a plasma display panel according to a third embodiment of the present invention.

Claims (9)

In the method of driving a plasma display panel, each of the plurality of subfields constituting one frame includes a reset period, an address period, and a sustain period, wherein discharge cells are formed by the first electrode, the second electrode, and the third electrode. Before the reset period, after gradually increasing the voltage of the first electrode from the first voltage to the second voltage, the voltage of the first electrode at the fourth voltage with the second electrode biased to the third voltage Progressively reducing to a fifth voltage, and In the reset period, after gradually increasing the voltage of the first electrode from the sixth voltage to the seventh voltage, the voltage of the first electrode is reduced from the ninth voltage with the second electrode biased to the eighth voltage. Gradually decreasing to 10 voltage Including; And a difference between the third voltage and the fifth voltage is greater than a difference between the eighth voltage and the tenth voltage. The method of claim 1, And a fifth voltage equal to the tenth voltage. The method of claim 1, And a third voltage equal to the eighth voltage. The method of claim 1, And the third voltage is equal to a higher voltage among voltages applied to the second electrode for sustain discharge in the sustain period. The method according to any one of claims 1 to 4, The difference between the tenth voltage and the voltage applied to the third electrode while the voltage of the first electrode decreases to the tenth voltage is equal to the first electrode and the second electrode for the sustain discharge in the sustain period. A method of driving a plasma display panel that is equal to or less than a negative value of a voltage corresponding to 1/2 of a voltage difference applied to the voltage. The method according to any one of claims 1 to 4, The difference between the tenth voltage and the voltage applied to the third electrode while the voltage of the first electrode decreases to the tenth voltage is equal to the first electrode and the second electrode for the sustain discharge in the sustain period. A method of driving a plasma display panel that is equal to or less than a negative value of a voltage corresponding to a voltage difference applied to the. A plasma display panel in which discharge cells are formed between the first electrode, the second electrode, and the third electrode; and A driving circuit for applying a driving voltage to the first electrode, the second electrode, and the third electrode during a reset period, an address period, and a sustain period, The drive circuit, Before the reset period, the voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode is gradually increased from the first voltage to the second voltage, and then gradually decreased from the third voltage to the fourth voltage, In the reset period, the voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode is gradually increased from the fifth voltage to the sixth voltage and then gradually decreased from the seventh voltage to the eighth voltage, And the fourth voltage is greater than the seventh voltage. The method of claim 7, wherein While the voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode decreases from the seventh voltage to the eighth voltage, the voltage obtained by subtracting the voltage of the third electrode from the voltage of the first electrode is determined by the ninth voltage. Gradually decreases to 10 voltage, And the tenth voltage is equal to or less than a negative value of a voltage corresponding to 1/2 of a voltage difference applied to the first electrode and the second electrode for the sustain discharge in the sustain period. The method of claim 7, wherein While the voltage obtained by subtracting the voltage of the second electrode from the voltage of the first electrode decreases from the seventh voltage to the eighth voltage, the voltage obtained by subtracting the voltage of the third electrode from the voltage of the first electrode is determined by the ninth voltage. Gradually decreases to 10 voltage, And the tenth voltage is less than or equal to a negative value of a voltage corresponding to a voltage difference applied to the first electrode and the second electrode for the sustain discharge in the sustain period.