KR100599725B1 - Plasma display panel and driving method thereof - Google Patents

Abstract

In the plasma display panel, a large amount of negative and positive charges may be formed in the scan electrode and the sustain electrode, respectively, by an unstable reset operation of the reset period. These charges can cause a discharge between the scan electrode and the sustain electrode in the sustain period even if there is no address discharge in the address period. After the reset period, a sustain voltage is applied to the scan electrodes to cause discharge, thereby forming negative and positive charges on the scan and sustain electrodes, respectively. Next, a wide erase pulse is applied to the scan electrode to erase the negative and positive charges formed on the scan electrode and the sustain electrode. In this way, discharge cells that are not selected in the sustain period can be prevented from being discharged when an unstable reset operation occurs.

PDP, strong discharge, reset, sustain, reset, address, mis-discharge, erase

Description

Plasma display panel and its driving method {PLASMA DISPLAY PANEL AND DRIVING METHOD THEREOF}

1 is a schematic partial perspective view of a plasma display panel.

2 is an arrangement diagram of electrodes of a plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

5A to 5D are wall charge distributions according to the driving waveforms of FIG. 4, respectively.

6A to 6C are wall charge distribution diagrams when an unstable reset operation occurs in the driving waveform of FIG. 4, respectively.

The present invention relates to a plasma display panel (PDP) and a driving method thereof.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. In the column direction, address electrodes A1-Am are arranged, and in the row direction, n rows of scan electrodes Y1-Yn and sustain electrodes X1-Xn are arranged in pairs.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and gray levels are expressed by a combination of subfields. Each subfield is composed of a reset period, an address period, and a sustain period as shown in FIG. The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

Next, a conventional driving method of the plasma display panel will be described with reference to FIG. 3.

3 is a driving waveform diagram of a plasma display panel according to the prior art. As shown in Fig. 3, the reset period consists of a ramp up period and a ramp down period.

In the ramp up period, the address electrode A and the sustain electrode X are held at 0 V, and a ramp waveform that gently rises to the Vset voltage is applied to the scan electrode Y. While this ramp waveform is rising, a weak reset discharge occurs in all the discharge cells between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A. FIG. As a result, negative wall charges are accumulated in the scan electrode Y, and positive wall charges are accumulated in the address electrode A and the sustain electrode X at the same time. Here, the wall charge refers to a charge that is formed on the wall of the discharge cell (for example, the dielectric layer) to be close to each electrode and accumulates on the electrode. And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

Subsequently, in the ramp down period, while the sustain electrode X is maintained at the Ve voltage, a ramp waveform that gently falls toward 0V at the Vs voltage is applied to the scan electrode Y. While this ramp waveform is falling, again weak discharge discharge occurs in all the discharge cells. As a result, the negative wall charge of the scan electrode Y decreases and the positive wall charge of the sustain electrode X decreases.

When the reset period is normally operated, the wall charges of the scan electrode Y and the sustain electrode X are erased, but an unstable discharge may occur due to an unstable reset operation. In such unstable discharges, when a discharge occurs due to self-erasing during the drop of the Vset voltage of the scan electrode Y after the strong discharge occurs during the ramp up period, the strong discharge occurs during the ramp up period and the ramp down period. In some cases, strong discharges occur during the ramp down period. In this case, in the first case, the reset function is performed according to the magnetic erase.

However, in the second and third cases, positive wall charges are formed on the scan electrode Y and negative wall charges are formed on the sustain electrode X due to the strong discharge in the ramp falling period. At this time, if the wall voltage V _wxy1 formed by the wall charges formed on the scan electrode Y and the sustain electrode X satisfies Equation 1, sustain discharge may occur in the sustain period even though there is no address discharge in the address period. Can be.

Here, V _wxy1 is a wall voltage formed between the scan electrode Y and the sustain electrode X due to the strong discharge in the ramp falling period, and Vs is the scan voltage of the scan electrode Y due to the sustain pulse applied in the sustain period. It is a voltage difference formed between sustain electrode X, and Vf is a discharge start voltage between scan electrode Y and sustain electrode X. As shown in FIG.

As described above, according to the conventional driving method, sustain discharge may occur in a discharge cell that should not be turned on due to the strong discharge in the ramp down period of the reset period.

The technical problem to be achieved by the present invention is to eliminate the erroneous discharge that may occur due to the strong discharge in the reset period.

In order to solve this problem, the present invention erases the charges formed by the unstable reset operation.

According to one aspect of the invention, it comprises a plurality of first and second electrodes formed side by side on the first substrate, and a plurality of third electrodes formed on the second substrate and intersect the first and second electrodes, The present invention provides a method of driving a plasma display panel in which discharge cells are formed by adjacent first, second and third electrodes. The driving method includes a reset step of setting the discharge cells to be addressable, an auxiliary reset step of assisting the reset step, an address step of selecting a discharge cell to be selected from among the discharge cells, and a sustain step of sustaining discharge of the selected discharge cell. Include. The auxiliary reset may include applying a first voltage to the first electrode, and applying a first voltage having a polarity opposite to the first voltage and having an absolute value smaller than the first voltage based on the voltage applied to the second electrode. Applying to the electrode.

According to one embodiment of the invention, under certain conditions, the first voltage may have a discharge function and the second voltage may have an erase function.

According to another embodiment of the present invention, the predetermined condition is when abnormal charge is formed in the reset step, and the abnormal charge formed in the reset step by the first voltage and the second voltage may be discharged and erased.

According to another embodiment of the present invention, the abnormal charge includes first and second charges formed on the first electrode and the second electrode, respectively, in the reset step, and the voltage formed by the first and second charges is determined in the address step. It may be a voltage that allows the unselected discharge cells to be sustained discharged in the sustain phase.

According to another embodiment of the present invention, the first voltage may be within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge.

According to another embodiment of the present invention, the period during which the first voltage is applied is within a range in which charge can be formed on the first electrode and the second electrode by the discharge between the first electrode and the second electrode, and the second The voltage may be a voltage capable of erasing the charge formed in the first period.

According to another embodiment of the present invention, the first voltage may be a voltage at the same level as the voltage periodically applied to the first electrode in the sustain step.

According to another embodiment of the present invention, the second voltage may be a voltage at the same level as the minimum voltage applied to the first electrode in the reset step.

According to another embodiment of the present invention, while the first voltage and the second voltage are applied to the first electrode, a constant voltage may be applied to the second electrode, respectively.

According to another feature of the invention, the first substrate, a plurality of first and second electrodes formed in parallel on each of the first substrate, the second substrate facing the first substrate and the first substrate and the second electrode and cross A plasma display panel is provided that includes a plurality of third electrodes formed on a second substrate and a driving circuit for supplying driving signals to discharge cells formed by adjacent first electrodes, second electrodes, and third electrodes. The driving circuit applies a first voltage to the first electrode that can cause a discharge between the first electrode and the second electrode under a constant condition between the reset period and the address period, and discharges the first electrode and the second electrode. A second voltage capable of erasing the charges formed in the circuit is applied to the first electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

4 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention. 5A through 5D are wall charge distribution diagrams according to the driving waveform of FIG. 4. 6A to 6C are wall charge distribution diagrams when strong discharge occurs during a ramp falling period in the driving waveform of FIG. 4.

As shown in FIG. 4, the driving waveform according to the embodiment of the present invention includes a reset period 100, a misfiring erase period 200, an address period 300, and a sustain period 400. . The reset period 100 includes a ramp up period 120 and a ramp down period 130.

The ramp up period 120 of the reset period 100 is a period of forming wall charges in the scan electrode Y, the sustain electrode X, and the address electrode A, and the ramp down period 130 is a ramp up period ( The wall charges formed at 120 are partially erased to facilitate address discharge.

The mis-discharge erasing period 200 is a period for forming a charge state so as to normally emit light by assisting the reset period 100, and the scan electrode Y and the sustain electrode formed due to unstable strong discharge in the ramp falling period 130. It is the period of removing the wall charge of (X).

The address period 300 is a period for selecting a discharge cell to cause sustain discharge in the sustain period from among the plurality of discharge cells. The sustain period 400 is a period for sustain discharge of the discharge cells selected in the address period 300 by applying a sustain pulse to the scan electrode Y and the sustain electrode X in order.

In addition, the plasma display panel applies a driving voltage to the scan / hold driving circuit for applying the driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods 100, 200, 300, and 400 and the address electrode A. And an address driving circuit to be applied.

First, a case in which the reset operation normally occurs by the driving waveform according to the embodiment of the present invention will be described in detail with reference to FIGS. 5A to 5D.

In the ramp rising period 120, a ramp waveform gradually rising from the voltage Vs to the voltage Vset is applied to the scan electrode Y while the sustain electrode X is maintained at the reference voltage. At this time, the voltage Vs is lower than the discharge start voltage Vf between the scan electrode Y and the sustain electrode X, and the voltage Vset is higher than the discharge start voltage Vf. Then, a weak discharge occurs between the scan electrode Y and the sustain electrode X while the ramp waveform rises, and then a weak discharge occurs between the scan electrode Y and the address electrode A. FIG. As a result, as shown in Fig. 5A, negative wall charges are accumulated on the scan electrode Y, and positive wall charges are accumulated on the address electrode A and the sustain electrode X at the same time.

In the ramp falling period 130, a ramp waveform that gently drops from the Vs voltage to the Vn voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the Ve voltage. Where the Vn voltage is a negative voltage. While this ramp waveform is falling, again weak discharge occurs in all the discharge cells. As a result, as shown in Fig. 5B, the negative wall charge of the scan electrode Y decreases and the positive wall charge of the sustain electrode X decreases. At this time, some negative wall charges may be accumulated on the sustain electrode X. In addition, the positive wall charge of the address electrode A is adjusted to a value suitable for the address operation.

In the false discharge erase period 200, a square pulse having a voltage Vs is applied to the scan electrode Y while the sustain electrode X is maintained at the reference voltage. At this time, when the charge is normally erased in the ramp falling period 130, the wall voltage formed between the scan electrode Y and the sustain electrode X is negative when the scan electrode Y is referenced to the negative voltage (-V _wxy2). ) Then, the voltage between scan electrode Y and sustain electrode X becomes (Vs-V _wxy2 ), which does not exceed the discharge start voltage Vf, and no discharge occurs. Thus, as shown in FIG. 5C, the wall charge distribution in the discharge cell remains the same as in FIG. 5B.

Next, in the false discharge erase period 200, a rectangular pulse having a Vn voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the reference voltage. Since the charge distribution in the scan electrode Y and the sustain electrode X is the same as in the previous period, no discharge occurs even by this rectangular pulse, so that the wall charge is maintained in the same manner as in FIG. 5B.

In the address period 300, a scan pulse having a Vn voltage is sequentially applied to the scan electrode Y in order to select a discharge cell, and to select among the address electrodes A intersecting the scan electrode Y to which the scan pulse is applied. The address pulse is applied to the address electrode A. Then, the discharge occurs between the scan electrode Y and the address electrode A due to the potential difference formed by the scan pulse and the address pulse. The discharge is generated between the scan electrode Y and the sustain electrode X based on the discharge between the scan electrode Y and the address electrode A to form wall charges in the scan electrode Y and the sustain electrode X. do.

In the sustain period 400, a sustain pulse is sequentially applied to the scan electrode Y and the sustain electrode X. The sustain pulse is a pulse that causes the voltage difference between the scan electrode Y and the sustain electrode X to alternate between the Vs voltage and the -Vs voltage. The voltage Vs is lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. When the wall voltage V _wxy3 is formed between the scan electrode Y and the sustain electrode X by the address discharge in the address period 300, the scan electrode Y is formed by the wall voltage V _wxy3 and the Vs voltage. And discharge occurs at the sustain electrode (X).

Next, the case where the strong discharge occurs in the ramp falling period 130 of the driving waveform according to an embodiment of the present invention with reference to Figures 6a to 6c in detail.

When strong discharge occurs in the ramp down period 130 due to an unstable reset operation, as shown in FIG. 6A, positive wall charges are accumulated on the scan electrode Y and negative wall charges are accumulated on the sustain electrode. At this time, the wall voltage V _wxy1 formed by the wall charges formed on the scan electrode Y and the sustain electrode X satisfies Equation 1.

When the voltage Vs is applied to the scan electrode Y and the reference voltage is applied to the sustain electrode X in the mis-discharge erase period 200, the wall voltage V _wxy1 between the scan electrode Y and the sustain electrode X is _applied . The voltage V _wxy1 + Vs between the scan electrode Y and the sustain electrode X _exceeds the discharge start voltage Vf due to the Vs voltage. Therefore, discharge occurs between scan electrode Y and sustain electrode X. As shown in FIG. 6B, a large amount of negative wall charges are accumulated on scan electrode Y, and a large amount of ( +) Wall charges accumulate

Next, in the second half of the false discharge erase period 200, a rectangular pulse having a Vn voltage is applied to the scan electrode Y to perform an erase operation. That is, the wall charges formed on the scan electrode Y and the sustain electrode X are erased by the Vn voltage pulse, so that the wall voltage between the scan electrode Y and the sustain electrode X is reduced. Lowers. As a result, the sum of the wall voltage between the scan electrode Y and the sustain electrode X and the Vs voltage applied in the sustain period 300 becomes lower than the discharge start voltage. Therefore, if there is no address discharge in the address period 300, no discharge occurs in the sustain period 400.

Generally, waveforms for erasing wall charges include waveforms that ramp up or fall slowly (lamp pulses), waveforms with short widths (narrow pulses), waveforms with wide widths and low voltage levels (wide pulses). In FIG. 4, in order to simplify the driving circuit, a wide pulse that applies the same voltage as the Vn voltage applied in the reset period 100 in a wide width is used. According to the waveform of FIG. 4, since the Vs voltage is applied to the voltage used in the sustain period 400 and the Vn voltage is applied to the voltage used in the reset period 100 in the false discharge erase period 200, the false discharge erase period There is no need to add a new voltage source or switching element for the 200.

In FIG. 4, the Vn voltage is used for the wide pulse. Alternatively, another voltage that satisfies the condition for erasing the wall charges may be widely applied. In this case, however, it is necessary to add a voltage source for supplying the corresponding voltage and a switching element for controlling the same.

In the embodiment of the present invention, the reference voltage is assumed to be 0 V, but the reference voltage may be another voltage.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, when a strong discharge occurs in the reset period due to an unstable reset operation, a large amount of charges are formed in the scan electrode and the sustain electrode, these charges can be erased. Therefore, sustain discharge can be prevented from occurring in the discharge cells that are not selected.

Claims (15)

A plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first and second electrodes, wherein the adjacent first, second, and third electrodes A method for driving a plasma display panel in which discharge cells are formed by A reset step of setting the discharge cells to be addressable; An auxiliary reset step of assisting the reset step; An address step of selecting a discharge cell to be selected among the discharge cells, and A sustain step of sustaining and discharging the selected discharge cells Including; The auxiliary reset step, Applying a first voltage to the first electrode, and Applying a second voltage having a polarity opposite to the first voltage and having an absolute value smaller than the first voltage to the first electrode based on the voltage applied to the second electrode. . delete The method of claim 1, When abnormal charge is formed in the reset step, And the abnormal charges formed in the reset step are discharged and erased by the first voltage and the second voltage. The method of claim 3, The abnormal charge includes first and second charges respectively formed on the first electrode and the second electrode in the reset step, And the voltage formed by the first and second charges is a voltage that allows discharge cells not selected in the address step to be sustained discharged in the sustain step. The method of claim 4, wherein And the first voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge. The method of claim 4, wherein The period during which the first voltage is applied is within a range in which charge can be formed in the first electrode and the second electrode by the discharge between the first electrode and the second electrode, And the second voltage is a voltage capable of erasing charges formed in the first period. The method according to any one of claims 1 and 3 to 6, And the first voltage is a voltage having the same level as a voltage periodically applied to the first electrode in the sustain step. The method according to any one of claims 1 and 3 to 6, And the second voltage is a voltage at the same level as the minimum voltage applied to the first electrode in the reset step. The method according to any one of claims 1 and 3 to 6, And a constant voltage is applied to the second electrode while the first voltage and the second voltage are applied to the first electrode. A plurality of first electrodes, A plurality of second electrodes, A plurality of third electrodes formed in a direction crossing the first and second electrodes, and A driving circuit for supplying driving signals to discharge cells formed by the adjacent first, second and third electrodes, The drive circuit, between the reset period and the address period, A first voltage capable of causing a discharge between the first electrode and the second electrode to the first electrode and erasing the charges formed in the first electrode and the second electrode by the discharge; 2. A plasma display panel applying a voltage to the first electrode. The method of claim 10, When abnormal charge is formed in the reset period, the discharge occurs by the first voltage and the erase occurs by the second voltage, The abnormal charge includes first and second charges respectively formed on the first electrode and the second electrode in the reset period, And the voltage formed by the first and second charges is a voltage that allows discharge cells not selected in the address period to be sustained discharged in the sustain period. The method according to claim 10 or 11, wherein And wherein the second voltage is opposite in polarity to the first voltage based on the voltage applied to the second electrode and has an absolute value smaller than the first voltage. The method of claim 12, And the first voltage is the same level of voltage as is periodically applied to the first electrode in the sustain period. The method of claim 12, And the second voltage is a voltage at the same level as a minimum voltage applied to the first electrode in the reset period. The method according to claim 10 or 11, wherein And wherein the second voltage is opposite in polarity to the first voltage based on the voltage applied to the second electrode and has an absolute value smaller than the first voltage.

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