JP2953342B2 - Driving method of plasma display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel, and more particularly to a method for driving a memory type plasma display panel.

[0002]

2. Description of the Related Art Plasma display panels (PDPs)
Is a thin structure, has no flicker, has a large display contrast ratio, is capable of producing a relatively large screen, has a fast response speed, is a self-luminous type, and uses a phosphor. It has many features, such as the ability to emit multicolor light. For this reason, in recent years, it has been widely used in fields such as computer-related display devices and color image display.

[0003] Depending on the operation method, the PDP has an AC discharge (AC) type in which electrodes are covered with a dielectric and indirectly operates in an AC discharge state, or a direct current discharge (DC) discharge in which the electrodes are exposed to a discharge space. There is a direct current (DC) type that operates in a state. Further, the AC type includes a memory operation type using a memory function of a discharge cell and a refresh operation type not using the same as a driving method. The luminance is proportional to the number of discharges, that is, the number of repetitions of the pulse voltage. In the refresh type, the brightness decreases as the display capacity increases,
Mainly used for panels with small display capacity.

FIG. 9 is a block diagram illustrating a conventional AC memory type PDP. PD for dot matrix display
The P panel 22 includes a plurality of scan electrodes Sc ₁ , S _c2 ,..., S _cj and sustain electrodes S _u1 , S _u2 , arranged in parallel with each other.
, S _uj, and data electrodes D _a1 , D _a2 ,..., D _ak arranged orthogonally (intersecting) with these scanning electrodes and sustaining electrodes. Each display cell 23 is arranged at the intersection of each electrode. In the figure, attention is paid to the structure of the electrode arrangement of the PDP panel 22, and the display cells 23 are displayed as j × k matrices.

FIG. 8 shows a sectional structure of one display cell 23 of the memory type PDP of FIG. The PDP includes first and second glass members disposed on the front side and the rear side on the display side, respectively.
Of insulating substrates 11 and 19. Scan electrode 17 and sustain electrode 18 are arranged on second insulating substrate 19 in parallel with each other, and data electrode 1 is placed on first insulating substrate 11.
2 are arranged, and the data electrodes 12 are orthogonal to the scan electrodes 17 and the sustain electrodes 18. The discharge gas space 21 between the first and second insulating substrates 11 and 19 is filled with a discharge gas made of helium, neon, xenon, or the like, or a mixed gas thereof. The partition walls 20 are arranged to secure a discharge gas space and to separate the display cells from each other. On the inner surface of the second insulating substrate 19, a dielectric 16 made of a dielectric material covering the scan electrode 17 and the sustain electrode 18 is formed.
Then, a protective film 15 made of magnesium oxide or the like for protecting the dielectric from discharge is formed. First insulating substrate 1
A dielectric 13 is formed on the inner surface of the data electrode 12 so as to cover the data electrode 12, and a phosphor 14 is applied on the dielectric 13. The phosphor 14 converts ultraviolet light generated by the discharge of the discharge gas into visible light. Here, the phosphor 14 is RG
By separately applying the three colors B, a PDP capable of color display can be obtained.

Next, the discharging operation of the selected display cell 23 will be described. When a pulse voltage exceeding a discharge threshold is applied between the scan electrode 17 and the data electrode 12 to start discharge, positive and negative charges corresponding to the polarity of the pulse voltage are generated on the dielectrics 13 and 16 on both sides of the discharge gas space 21. Is attracted to the surface of the substrate, and charge accumulates as the discharge grows. Since the equivalent internal voltage, that is, the wall voltage, due to the deposited charge has the opposite polarity to the applied pulse voltage, the effective voltage inside the cell decreases as the discharge grows. For this reason, even if the applied pulse voltage holds a constant value,
The discharge is stopped as soon as it cannot be maintained.

Thereafter, when a sustain pulse having the same polarity as the wall voltage is applied between the scan electrode 17 and the sustain electrode 18 adjacent to each other, the sustain pulse is superimposed on the wall voltage, and the sustain pulse is applied. Even if the voltage amplitude is low, the discharge threshold can be exceeded. That is, the discharge in the display cell can be maintained by continuously applying the sustain pulse between the scan electrode 17 and the sustain electrode 18. This function is the memory function described above. In addition, the discharge can be stopped by applying a low-voltage erase pulse having a magnitude and width that neutralizes the wall voltage to the scan electrode 17 or the sustain electrode 18.

FIG. 7 is a schematic diagram showing the driving timing of a PDP when one field is divided into a plurality of subfields and driven in order to perform gradation display in the PDPs of FIGS. FIG. 7 shows an example in which four subfields are divided into SF1, SF2, SF3, and SF4. First, there is a pre-discharge period A in which all display cells are pre-discharged simultaneously, followed by a pre-discharge erase period B in which all display cells are pre-discharged simultaneously. In the subsequent address discharge period C, scan pulses are applied line-sequentially to scan electrodes S _c1 to S _cj . The hatched portions in the drawing are the writing timings of the respective scanning electrodes. After the writing of the last scan electrode S _cj is completed, all the display cells are sustain-discharged during a predetermined period selected from the sustain discharge periods D1, D2, D3, and D4, respectively. The sustain discharge periods D1, D2, D3, D4 are T, T / 2, T / 4,
T / 8 is selected, and gradation display (16 gradations = 2 ⁴ ) is performed by weighting the light emission time of each light emitting cell by 2 ⁿ .

FIG. 10 is a timing chart exemplifying a driving voltage waveform in one subfield period in driving the above-described PDP. The common sustain electrode drive waveform COM applied to the sustain electrodes S _u1 , S _u2 ,..., S _uj and the scan electrode drive waveform S applied to the scan electrodes S _c1 , S _{c2 ,.
1} , S ₂ ,..., S _j and the data electrode drive waveform DATA applied to the data electrodes D _i (1 ≦ i ≦ k) are shown. One cycle of driving includes a preliminary discharge period A, a preliminary discharge erase period B, a write discharge period C, and a sustain discharge period D.

Predischarge period A and predischarge erase period B
Is a period for generating active particles and wall charges in the discharge gas space in order to obtain stable address discharge characteristics in the address discharge period C. The application pulse in this period is composed of a preliminary discharge pulse 24 for simultaneously discharging all display cells of the PDP panel 22 and a preliminary discharge erasing pulse 25 for erasing the discharge.

In the address discharge period C, each of the scan electrodes S _c1 , S _c
The scanning pulse 26 is applied to each of _c2 ,..., _Scj at a timing independently and sequentially, and the writing discharge is performed line-sequentially. For example, the scanning electrode S shown in FIG.
Display cell 2 formed at the intersection of _c1 and data electrode _Da3
To write emission data 3, to match the timing of the scanning pulse 26 of the drive waveform S _1, the data pulse 29 is applied to the data electrodes D _a3, scanning electrodes S _c1 and the data electrodes D
_A discharge is generated in the display cell 23 between a and _a3 . When light emission data is not written in the display cell 23, the data pulse 29 is not applied.

The sustain discharge period D is a period in which the display cells which have undergone the address discharge in the address discharge period C are sustain-discharged according to the memory function, and the discharge is repeated between the scan electrodes and the sustain electrodes by the sustain pulses 27 and 28. Continue lighting.

[0013]

In driving a plasma display panel, the number of display cells has increased remarkably with the recent increase in screen size and definition. For this reason, the number of light emitting cells selected to emit light by the scan pulse and the data pulse also increases, the peak current value of the address discharge flowing on one scan electrode at the time of the address discharge increases, and the voltage drop due to the impedance of the electrode and the drive circuit. Also increases. Therefore, in order to perform stable address discharge, it is necessary to apply a scan pulse voltage and a data pulse voltage having higher voltage values. However, there is a problem that the adoption of a high voltage value contradicts the demand for further lowering the voltage accompanying the portable use of personal computers and the like. .

An object of the present invention is to solve the above-mentioned problem by reducing the increase in the peak current of the address discharge due to the increase in the number of display cells, thereby requiring a high scan voltage or data pulse voltage. It is an object of the present invention to provide a method of driving a plasma display panel capable of performing a stable address discharge without any problem.

[0015]

According to a method of driving a plasma display panel of the present invention, display cells are arranged in a matrix at each intersection of a plurality of scanning electrodes and a plurality of data electrodes.
In a method of driving a plasma display panel of a type in which a screen is displayed by controlling light emission of the display cell by a data pulse applied from the data electrode, the data electrode is divided into a plurality of data electrode groups, and the divided data electrode is It is characterized in that data pulses which are mutually shifted in time are applied to each of the groups.

Here, the plasma display panel to which the driving method of the present invention is applied is not limited to the AC surface discharge type plasma display panel having a three-electrode structure exemplified in the prior art, but is, for example, a facing discharge type plasma display panel having a two-electrode structure. Alternatively, the present invention can be applied to other types of plasma display panels.

In a preferred example of the method for driving a plasma display panel according to the present invention, the length of the shifting time is 1
When the address discharge duration of one display cell is Ti and the pulse width of the scan pulse applied to the scan electrode is Tw, Ti / 1
The range is 0 to Tw−2Ti. More preferably, the shifting time is in the range of Ti / 5 to Ti. Thus, a pulse width adapted to the scanning pulse width can be obtained, and the peak value of the discharge current can be sufficiently reduced.

[0018]

In the method of driving a plasma display panel according to the present invention, the data electrodes are divided into a plurality of electrode groups, and the timing of applying a data pulse to each of these electrode groups is shifted from each other, so that the data flowing through one scan electrode is reduced. The peak value of the discharge current required for writing can be reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. FIG. 1 shows a driving voltage waveform in a driving method of a plasma display panel (PDP) according to one embodiment of the present invention. FIG. 2 is a block diagram similar to FIG. 9 and shows a divided configuration of the data electrodes divided into two groups of the PDP to which the driving method of this embodiment is applied. The configuration of this PDP is the same as the configuration of the PDP described in the related art, except that the entire data electrode is divided into two groups of data blocks G1 and G2 as shown in FIG.

In FIG. 1, a driving voltage pulse in the driving method of this embodiment includes a common sustain electrode driving pulse COM applied to sustain electrodes Su _{1 to} Su _j and scanning electrodes S _{c1 to} S _c.
Scan electrode driving pulses S ₁₁ , S ₁₂ ,..., S _1j applied to _cj
And a first data electrode drive pulse DATA1 applied to the data block G1, and a second data electrode drive pulse DATA2 applied to the data block G2. I _w1 and I _{wj
Represents} the waveform of the write discharge current flowing through the scan electrodes S _c1 and S _cj , respectively. Here, an example in which the discharge gas of the PDP is a mixed gas of He, Ne, and Xe will be described.

[0021] For example, when performing the address discharge is line scan electrodes S _c1 is used to apply a scan pulse 3 to the scanning electrodes S _c1, applies data pulses 4 and 5 each data block G1, G2 within that period I do. At this time, the rising of the data pulse 4 applied to the data electrodes D _{a1 to} D _ak of the data block G1 and the data electrode Da of the data block G2 are performed.
Each rising _edge of the data pulse 5 applied to _{k + 1 to Da2k} is 4
It is shifted by 00 ns, and both pulse widths are the same. Here, the pulse width of the scan pulse 3 applied to the scan electrode S _c1 is 5 .mu.s, the pulse width of the data pulses 4 and 5 is applied to each data block is a respective 4.6Myuesu.

As described above, by delaying the data pulse 5 from the data pulse 4 by a predetermined time, the timing of the address discharge by each data pulse is shifted, so that the address discharge currents I _{W1 to} I _Wj flowing through one scan electrode _become : Within one scan pulse 3, it has two peak values.
In other words, the data blocks G1 and G
2, the address discharge period is dispersed.

FIG. 1 shows an example in which the data pulse 5 is delayed from the data pulse 4 by 400 ns. A good result can be obtained by setting the delay time to about 40 to 3400 ns, preferably about 80 to 800 ns, especially when focusing on the rising timing, that is, the pulse application start time.

FIGS. 3A to 3C illustrate the waveforms of the write discharge current depending on the timing differences of the data pulses. Here, reference numeral 3 indicates a scanning pulse, reference numerals 4 and 5 indicate respective data pulses, and reference numeral 8 indicates a write discharge current. FIG. 11A shows an example in which no delay time is provided between the data pulses 4 and 5, and FIG.
FIG. 2C shows an example of the delay time Ti. Here, Ti indicates the duration of the address discharge current flowing by one address discharge pulse, as shown in FIG. The discharge duration Ti is determined by the size of the panel, the electrode structure,
Although it depends on the composition of the discharge gas, it is generally several hundred to
He, Ne and X shown above are several thousands ns.
When the mixed gas of e is used, the time is about 800 ns.
As shown in FIG. 7A, when no delay time is provided, a write discharge current having a large peak value Ip flows.

FIG. 4 is a diagram showing the relationship between the delay time from data pulse 4 to data pulse 5 and the peak value of the discharge current. As shown in the figure, the peak value of the address discharge current 8 decreases as the delay time increases. FIG.
Assuming that the delay time is Ti / 2 as shown in (b), the peak current of the address discharge current 8 is the maximum value Ip without delay.
Is approximately の. Even if the delay time is set longer, the decrease in the peak current is small. Here, the delay time is T
As shown in FIG. 3C, the write discharge timing of the scan pulse 3 and the data pulse 4 and the write discharge timing of the scan pulse 3 and the data pulse 5 become independent as shown in FIG. 8 can be completely divided.

As shown in FIG. 4, even if the delay time from data pulse 4 to data pulse 5 is short, the peak value of the write discharge current can be reduced. In general, if Tw is the scanning pulse width, the delay time is Ti / 10
~ Tw-2Ti (ns), more preferably Ti / 5 ~ Ti (ns). here,
2Ti (ns) is the time required as the sum of the duration of the address discharge current and the stabilization time of the wall charge after the address discharge. Therefore, the upper limit of the delay time is Tw-2Ti (ns). If the delay time is set to Ti / 2 or more, the peak value of the write discharge current becomes substantially the lowest possible value, and particularly good results are obtained.

As described above, by dispersing the address discharge time among the data blocks, the peak value of the address discharge current can be reduced, and the voltage drop due to the parasitic impedance of the electrodes and the drive circuit can be reduced accordingly. .
Therefore, even if the number of display cells increases, stable address discharge can be performed without increasing the scan pulse voltage and the data pulse voltage.

FIGS. 5 and 6 are timing charts showing another example of giving a delay to a data pulse. In the example of FIG. 5, the data pulse 4 is replaced with the data pulse 5
Is delayed by 400 ns, and the fall of the data pulse 5 is set at the same timing as the fall of the data pulse 4. In general, the duration of the discharge current is substantially determined by the rise of the data pulse. Therefore, even if this example is adopted, the same effect as that of the above example can be obtained.

In the example of FIG. 6, the pulse widths of the data pulses 4 and 5 are the same, and the falling of the data pulse 5 is later than the falling of the corresponding scanning pulse 3.
Even if the falling of the data pulse 5 temporally overlaps with the scanning pulse 3 for the next scanning electrode as described above, if the overlapping timing is short, an erroneous write discharge does not occur. There is no.

Although FIG. 2 shows an example in which the data block is divided into two in the horizontal direction on the drawing, the method of dividing the data block is not limited to this. For example, the data block may be divided into odd lines and even lines. Can be divided into
The same effect as above can be obtained.

The data block can be divided into three or more. In this case, by shifting the rising time of the data pulse of each data block by a predetermined time,
When the peak value of the discharge current is further suppressed and the scan pulse voltage and the data pulse voltage having the same voltage values as in the previous embodiment are employed, the address discharge is performed more stably.

As described above, the method for driving the plasma display panel according to the present invention is an AC surface discharge type PD having a three-electrode structure.
Although P has been described as an example, the driving method of the plasma display panel according to the present invention is not limited to such an example, and can be applied to, for example, a two-electrode opposed discharge PDP or another type of PDP. .

Although the present invention has been described based on the preferred embodiments, the method of driving the plasma display panel of the present invention can be variously modified and changed from the configuration of the above-described embodiment. A method for driving a plasma display panel modified and changed from the configuration described above is also included in the scope of the present invention.

[0034]

As described above, the driving method of the plasma display panel of the present invention employs a configuration in which the data electrodes are divided into a plurality of data blocks and the data pulse application timing is shifted for each data block. The peak current of the address discharge flowing on the same scan electrode can be suppressed to be small, so that the voltage drop due to the impedance of the scan electrode and the drive circuit can be reduced.
Therefore, even if the number of display cells increases due to an increase in the screen size and definition of the plasma display panel, a plasma display capable of performing stable address discharge without increasing the scan pulse voltage and the data pulse voltage is required. We can provide panels.

[Brief description of the drawings]

FIG. 1 is a timing chart in a method of driving a PDP according to one embodiment of the present invention.

FIG. 2 is a block diagram showing an electrode configuration in the PDP of FIG.

FIGS. 3A to 3C are timing charts each illustrating a relationship between a timing difference between data pulses and a waveform of a write discharge current.

FIG. 4 is a graph showing a relationship between a delay time of a data pulse and a peak value of a write discharge current.

FIG. 5 is a timing chart showing another example of a data pulse delay.

FIG. 6 is a timing chart showing still another example of the delay of the data pulse.

FIG. 7 is a schematic diagram showing timing in a conventional PDP driving method.

FIG. 8 is a cross-sectional view illustrating one display cell of a conventional PDP.

FIG. 9 is a block diagram showing an electrode configuration of a conventional PDP.

FIG. 10 is a timing chart illustrating a drive voltage waveform in one subfield period in driving a conventional PDP.

[Explanation of symbols]

A preliminary discharge period B preliminary discharge erase period C write discharge period D, D1, D2, D3, D4 sustain discharge period G1 first data block G2 second data block Sc1 to Scj scan electrode Su1 to Suj sustain electrode Da1 to Dak to Da2k Data electrodes S1, S2, S3, Sj, S11, S12, S1j Scan electrode drive waveform COM Sustain electrode drive waveform DATA, DATA1, DATA2 Data electrode drive waveform SF1, SF2, SF3, SF4 Subfield 24 Predischarge pulse 25 Predischarge erase Pulse 26 Scanning pulse 6, 7, 27, 28 Sustain pulse 4, 5, 29 Data pulse 8 Write discharge current 9, 22 PDP panel 11, 19 Insulating substrate 13, 16 Dielectric 14 Phosphor 15 Protective film 12 Data electrode 17 Scan Electrode 18 Sustain electrode 20 Partition wall 21 Discharge gas space 23 Display cell

Claims (2)

(57) [Claims] A display cell is arranged in a matrix at each intersection of a plurality of scanning electrodes and a plurality of data electrodes, and light emission of the display cells is controlled by a data pulse applied from the data electrode to display a screen. In the method of driving a plasma display panel of the type described above, the data electrodes are divided into a plurality of data electrode groups, and each of the divided data electrode groups has a writing discharge duration of one display cell, Ti, and a scan.
Assuming that the pulse width of the scanning pulse applied to the electrode is Tw,
A method for driving a plasma display panel, characterized by applying data pulses whose application start times are sequentially shifted within a range of Ti / 10 to Tw-2Ti . 2. Display screens are arranged in rows and columns at each intersection of a plurality of scanning electrodes and a plurality of data electrodes, and light emission of the display cells is controlled by data pulses applied from the data electrodes. In the method of driving a plasma display panel of the type described above, the data electrode is divided into a plurality of data electrode groups, and each of the divided data electrode groups has a writing discharge duration of one display cell as Ti.
And applying a data pulse whose application start time is sequentially shifted in a range of Ti / 5 to Ti .