JP4977960B2 - Plasma display device - Google Patents

Description

  The present invention relates to a plasma display device known as a thin, lightweight display device having a large screen.

  A plasma display device is capable of high-speed display compared to a liquid crystal panel, has a wide viewing angle, is easy to increase in size, and is self-luminous, so that the display quality is high. Recently, it has attracted particular attention in technology.

  In general, in this plasma display device, an ultraviolet ray is generated by gas discharge, and a phosphor is excited by the ultraviolet ray to emit light to perform color display. And the display cell divided by the partition on the board | substrate is provided, and it has the structure by which the fluorescent substance layer is formed in this.

  This plasma display device is roughly classified into an AC type and a DC type in terms of driving, and there are two types of discharge types: a surface discharge type and a counter discharge type, but high definition, large screen, and simple manufacturing are possible. Therefore, at present, the mainstream of plasma display devices is a surface discharge type of a three-electrode structure, and the structure has a pair of display electrodes adjacent in parallel on one substrate, and on the other substrate. It has an address electrode arranged in a direction intersecting with the display electrode, a partition wall, and a phosphor layer. The phosphor layer can be made relatively thick and is suitable for color display using a phosphor.

  However, as the screen size of plasma display devices has increased, the following issues have become clear. As the number of pixels in the horizontal direction increases as the screen size increases, the peak current that simultaneously flows into the scan electrodes during address discharge increases. Although the peak current increased by this enlargement of the screen flows through the same scan electrode, the scan electrode has a resistance component of several tens of ohms to several hundreds of ohms, so that a voltage drop occurs. When the voltage drop occurs, the voltage for the address discharge applied to the discharge cell is lowered. For this reason, if the peak current increases too much, the address discharge itself stops, and a cell in which the subsequent sustain discharge does not emit light normally occurs, resulting in a phenomenon such as dot dropping.

For this reason, various methods for reducing the current peak of the address discharge have been considered. For example, as in Patent Document 1, the address electrode is divided into a plurality of blocks, and the timing of the address pulse voltage applied to the address electrode is shifted for each block, that is, the current peak flowing on the same scan electrode is shifted. By dispersing, the current peak is kept low, the voltage drop due to the impedance of the scan electrode and the drive circuit is reduced, and the rising phase of the voltage applied to the address electrode is simplified for circuit simplification. A method has been devised in which a recovery coil is used to shift each unit block and power is recovered using a common recovery coil without causing a phase difference at the fall.
JP-A-8-305319

  However, in this method, since the rising phase of the write voltage of the address driver circuit is shifted and the falling timing is made the same, the high level period of the pulse that rises with a delay in the phase difference is short, and a reliable display operation is achieved. There is a problem that the margin of the panel characteristics necessary to achieve a wide range cannot be obtained, and if the phase difference is reduced to ensure a high level period, the current is concentrated without the address current becoming two peaks. Therefore, the problem that stable discharge cannot be obtained has occurred.

  An object of the present invention is to solve such a problem, and it is an object of the present invention to stably perform address discharge and ensure a sufficient panel margin in a plasma display device.

In order to achieve the above object, a plasma display device according to the present invention has a plurality of rows of display electrodes and a plurality of rows of electrodes arranged so as to cross the display electrodes on a pair of substrates that form a discharge space and face each other. A plasma display panel having a plurality of discharge cells configured by providing an address electrode, and an address driver circuit for supplying an address pulse voltage for writing display data to the address electrode of the plasma display panel, The address driver circuit is configured to be able to supply first and second address pulse voltages having different phases, and includes a power recovery circuit that recovers charges at the time of writing display data to the address electrodes, the power recovery circuit is provided in common to all of the address electrodes, the plasma The address electrode of the display panel is divided into a plurality of blocks of the first and second blocks to which the first and second address pulse voltages are respectively supplied, and the first address pulse voltage having an early phase is supplied. The area ratio of the first block is made smaller than that of the second block, and the falling timings of the first and second address pulse voltages are made the same.

  Furthermore, the present invention is characterized in that the area ratio of the first block to which the first address pulse voltage having an early phase is supplied is 40% or less of the entire effective display area of the plasma display panel.

  According to the plasma display apparatus of the present invention, the address driver circuit is configured to be able to supply first and second address pulse voltages having different phases, and the address electrode of the plasma display panel includes the first and second address electrodes. The area ratio of the first block to which the first address pulse voltage having an early phase is supplied is divided into a plurality of blocks of the first and second blocks to which the second address pulse voltage is supplied. By making it smaller than this block, even when the configuration of the power recovery circuit in the address driver circuit is simplified, address discharge can be performed stably and a sufficient panel margin can be secured.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7, but the embodiment of the present invention is not limited to this.

  First, the structure of the plasma display panel in the plasma display device will be described with reference to FIG. As shown in FIG. 1, on a transparent front substrate 1 such as a glass substrate, a plurality of stripe-shaped display electrodes 2 paired with a scan electrode and a sustain electrode are formed, and covers the electrode group. Thus, the dielectric layer 3 is formed, and the protective film 4 is formed on the dielectric layer 3.

  Further, a plurality of rows of stripes covered with an overcoat layer 6 are formed on the rear substrate 5 opposite to the front substrate 1 so as to intersect the display electrodes 2 of the scan electrodes and the sustain electrodes. Address electrodes 7 are formed. On the overcoat layer 6 between the address electrodes 7, a plurality of barrier ribs 8 are arranged in parallel with the address electrodes 7, and a phosphor layer 9 is provided on the side surface between the barrier ribs 8 and on the surface of the overcoat layer 6. Yes.

  The substrate 1 and the substrate 5 are opposed to each other with a minute discharge space so that the display electrode 2 and the address electrode 7 of the scan electrode and the sustain electrode are almost orthogonal to each other, and the periphery is sealed, In the discharge space, one or a mixed gas of helium, neon, argon, and xenon is sealed as a discharge gas. Further, the discharge space is divided into a plurality of sections by partition walls 8 to provide a plurality of discharge cells where the intersections of the display electrodes 2 and the address electrodes 7 are located, and each of the discharge cells has red, green and blue colors. The phosphor layers 9 are sequentially arranged one by one so that

  FIG. 2 shows an electrode arrangement of the plasma display panel. As shown in FIG. 2, the scan electrode, the sustain electrode, and the address electrode have a matrix configuration of M rows × N columns, and M rows are arranged in the row direction. Scan electrodes SCN1 to SCNm and sustain electrodes SUS1 to SUSm are arranged, and N columns of address electrodes D1 to Dn are arranged in the column direction.

  In the plasma display panel having such an electrode configuration, an address pulse is applied between the address electrode and the scan electrode by applying a write pulse between the address electrode and the scan electrode, and after selecting the discharge cell, the scan electrode By applying a periodic sustain pulse that is alternately inverted between the sustain electrode and the sustain electrode, a sustain discharge is performed between the scan electrode and the sustain electrode, and a predetermined display is performed.

  In general, an address / display period separation method is used as a gradation display driving method of a plasma display device. In this method, one field is temporally divided into a plurality of subfields. For example, when 256 gradation display is performed with 8 bits, one field is divided into eight subfields. Each subfield is divided into a scan period in which an address discharge for selecting a lighted cell is performed and a sustain period (a display discharge period) in which a sustain discharge for display is performed.

  In this method, scanning by address discharge is performed on the entire surface of the PDP from the first line to the m-th line in each subfield, and sustain discharge is performed at the end of the entire address discharge.

  FIG. 3 shows the configuration of the display drive circuit of the plasma display device in this embodiment. As shown in FIG. 3, the plasma display panel (PDP) 10 having the configuration shown in FIG. 1, the address driver circuit 11, the scan driver circuit 12, the sustain driver circuit 13, the discharge control timing generation circuit 14, the power supply circuits 15, 16, and A A / D converter (analog / digital converter) 17, a scanning number conversion unit 18, and a subfield conversion unit 19 are provided.

  In the circuit of FIG. 3, first, the video signal VD is input to the A / D converter 17. Further, the horizontal synchronizing signal H and the vertical synchronizing signal V are given to the discharge control timing generation circuit 14, the A / D converter 17, the scanning number conversion unit 18, and the subfield conversion unit 19. The A / D converter 17 converts the video signal VD into a digital signal and supplies the image data to the scanning number conversion unit 18.

  The scanning number conversion unit 18 converts the image data into image data having the number of lines corresponding to the number of pixels of the PDP 10, and gives the image data of each line to the subfield conversion unit 19. The subfield conversion unit 19 divides each pixel data of the image data of each line into a plurality of bits corresponding to a plurality of subfields, and serially outputs each bit of each pixel data to each address field 11 in each subfield. To do.

  The address driver circuit 11 is connected to the power supply circuit 15, converts the data serially given to each subfield from the subfield conversion unit 19 into parallel data, and applies address pulses to a plurality of address electrodes based on the parallel data. Supply voltage.

  The discharge control timing generation circuit 14 generates discharge control timing signals SC and SU with reference to the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the scan driver circuit 12 and the sustain driver circuit 13, respectively. The scan driver circuit 12 includes an output circuit 121 and a shift register 122. The sustain driver circuit 13 includes an output circuit 131 and a shift register 132. The scan driver circuit 12 and the sustain driver circuit 13 are connected to a common power supply circuit 16.

  The shift register 122 of the scan driver circuit 12 applies the discharge control timing signal SC supplied from the discharge control timing generation circuit 14 to the output circuit 121 while shifting in the vertical scanning direction. The output circuit 121 sequentially supplies a scan pulse voltage to the plurality of scan electrodes in response to the discharge control timing signal SC supplied from the shift register 122.

  The shift register 132 of the sustain driver circuit 13 supplies the discharge control timing signal SU supplied from the discharge control timing generation circuit 14 to the output circuit 131 while shifting in the vertical scanning direction. The output circuit 131 supplies a sustain pulse voltage to the plurality of sustain electrodes in response to the discharge control timing signal SU given from the shift register 132.

  Next, a driving voltage waveform for driving the panel and its operation will be described. FIG. 4 is a diagram showing a driving voltage waveform applied to each electrode of the panel in the embodiment of the present invention.

  In the initializing period of the first subfield, the address electrodes D1 to Dn and the sustain electrodes SUS1 to SUSm are held at 0 (V), and from the voltage Vi1 (V) that is lower than the discharge start voltage with respect to the scan electrodes SCN1 to SCNm. A ramp voltage that gradually increases toward the voltage Vi2 (V) exceeding the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are stored on the scan electrodes SCN1 to SCNm, and positive walls are formed on the sustain electrodes SUS1 to SUSm and the address electrodes D1 to Dn. The voltage is stored. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on a dielectric layer or a phosphor layer covering the electrode. Thereafter, the sustain electrodes SUS1 to SUSm are maintained at the positive voltage Vh (V), and a ramp voltage that gradually decreases from the voltage Vi3 (V) to the voltage Vi4 (V) is applied to the scan electrodes SCN1 to SCNm. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage on the scan electrodes SCN1 to SCNm and the wall voltage on the sustain electrodes SUS1 to SUSm are weakened, and the wall voltage on the address electrodes D1 to Dn is reduced. Is also adjusted to a value suitable for the write operation.

  In the subsequent address period, scan electrodes SCN1 to SCNm are temporarily held at Vr (V). Next, a positive address pulse voltage Vd (V) is applied to the address electrodes Dk (k = 1 to n) of the discharge cells to be displayed in the first row among the address electrodes D1 to Dn, and the scan in the first row. A scan pulse voltage Va (V) is applied to the electrode SCN1. At this time, the voltage at the intersection of the address electrode Dk and the scan electrode SCN1 is obtained by adding the wall voltage on the address electrode Dk and the wall voltage on the scan electrode SCN1 to the externally applied voltage (Vd−Va) (V). Exceeding the discharge start voltage. An address discharge is generated between the address electrode Dk and the scan electrode SCN1 and between the sustain electrode SUS1 and the scan electrode SCN1, and a positive wall voltage is accumulated on the scan electrode SCN1 of the discharge cell. And a negative wall voltage is also accumulated on the address electrode Dk.

  In this way, an address operation is performed in which an address discharge is caused in the discharge cell to be displayed in the first row and a wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the address electrodes D1 to Dn and the scan electrode SCN1 to which the positive address pulse voltage Vd (V) is not applied does not exceed the discharge start voltage, so that no address discharge occurs. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, a sustain pulse is applied between the scan electrodes SCN1 to SCNm and the sustain electrodes SUS1 to SUSm, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light. The details of the sustain pulse waveform and the accompanying discharge will be described later, and an outline of the operation in the sustain period will be described here.

  First, the sustain electrodes SUS1 to SUSm are returned to 0 (V), and a positive sustain pulse voltage Vs (V) is applied to the scan electrodes SCN1 to SCNm. In the discharge cell in which the address discharge has occurred at this time, the voltage between the scan electrodes SCN1 to SCNm and the sustain electrodes SUS1 to SUSm is set to the sustain pulse voltage Vs (V), the scan electrodes SUN1 to SUNm, and the sustain electrodes SUS1 to SUS1. The magnitude of the wall voltage on SUSm is added and exceeds the discharge start voltage. A sustain discharge occurs between the scan electrodes SUN1 to SUNm and the sustain electrodes SUS1 to SUSm, a negative wall voltage is accumulated on the scan electrodes SUS1 to SUSm, and a positive wall voltage is accumulated on the sustain electrodes SUS1 to SUSm. Is done.

  At this time, a positive wall voltage is also accumulated on the address electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage state at the end of the initialization period is maintained. Subsequently, the scan electrodes SCN1 to SCNm are returned to 0 (V), and a positive sustain pulse voltage Vs (V) is applied to the sustain electrodes SUS1 to SUSm. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage between the sustain electrodes SUS1 to SUSm and the scan electrodes SUN1 to SUNm exceeds the discharge start voltage, the sustain electrodes SUS1 to SUSm and the scan electrodes SUN1 to SUNm again During this time, a sustain discharge occurs, negative wall voltages are accumulated on the sustain electrodes SUS1 to SUSm, and positive wall voltages are accumulated on the scan electrodes SUN1 to SUNm.

  Similarly, the sustain discharge continues in the discharge cells in which the address discharge is generated in the address period by alternately applying the number of sustain pulses corresponding to the luminance weight to the scan electrodes SCN1 to SCNm and the sustain electrodes SUS1 to SUSm. Done. Thus, the maintenance operation in the maintenance period is completed.

  The operations in the initialization period, address period, and sustain period in the subsequent subfield are substantially the same as those in the first subfield, and thus description thereof is omitted.

  Through the above operation, one screen is displayed on the plasma display device.

  Next, the address driver circuit in this embodiment will be described in more detail.

  FIG. 5 is a diagram showing the configuration of the address driver circuit 11 and the connection state with the PDP 10 in the present embodiment, and FIG. 6 is a diagram showing timing waveforms of the address electrodes and the scan electrodes. The address driver circuit 11 that supplies an address pulse voltage for writing display data to the address electrode of the PDP 10 includes a power recovery circuit that recovers charges when writing display data to the address electrode, and the address driver circuit 11 is configured to be able to supply first and second address pulse voltages having different phases, and the address electrodes of the PDP 10 are supplied with the first and second address pulse voltages, respectively. The area ratio of the first block that is divided into a plurality of blocks of the second block and that is supplied with the first address pulse voltage having an early phase is made smaller than that of the second block. That is, the area ratio of the first block to which the first address pulse voltage having an early phase is supplied is set to 40% or less of the entire effective display area of the plasma display panel.

  In FIG. 5, Q1 to Q5 are FETs as switching elements, Di1 to Di4 are diodes, C1 is a power recovery capacitor, L1 and L2 are resonance coils for power recovery, and IC1 and IC2 control the on / off of FETs Q2 and Q3. Control IC. Reference numerals 111 and 112 denote output circuits of the address driver circuit 11, which can supply first and second address pulse voltages having different phases, and each of the output circuits 111 and 112 has a plurality of output ICs. . The address electrode of the PDP 10 connected to each of the output circuits 111 and 112 is divided into a plurality of blocks of the first and second blocks. A recovery potential adjustment circuit 113 is a circuit that automatically adjusts the recovery potential of the capacitor C1 in accordance with an address in order to increase the power recovery efficiency of the output IC group.

  In FIG. 5, the FET Q2 is first turned on, and the charge stored in the capacitor C1 is supplied to the output circuit 112 and the power source of the output circuit 112 via the diode Di4, the resonance coil L1, another diode Di2, and the resonance coil L2. The power supply voltage is raised to near the address voltage Vda. At this time, the resonance coils L1 and L2 are set so that the inductance satisfies L1> L2. Since L1> L2 when the FET Q2 is turned on, the power supply voltage rises of the output circuit 111 and the output circuit 112 are different. That is, the power supply voltage rise of the output circuit 111 connected to the resonance coil L1 is slower than the power supply voltage rise of the output circuit 112 connected to the resonance coil L2. A time difference is provided in the address discharges of the output circuits 111 and 112 using the time difference of the voltage rise.

  When the FET Q2 is turned on, it is the power supply of the output circuit 112 to which the resonance coil L2 having a small inductance is connected that increases the voltage. Therefore, the FET Q4 is then turned on to raise the power supply of the output circuit 112 to the address voltage Vda. The output circuits 111 and 112 are connected via the diode Di1, but when the FET Q4 is turned on, the anode of the diode Di1 is connected to the output circuit 111, so that the power supply of the output circuit 112 rises. The power supply voltage of the output circuit 111 does not rise up to the address voltage Vda. At this time, the scan driver circuit connected to the scan electrode on the n-th line is turned on, the scan electrode voltage is lowered as shown in FIG. 6, address discharge is started between the address electrode and the scan electrode, and the address is applied to the scan electrode. Current flows.

  Next, the FET Q1 is turned on with a delay of time ta from the turning on of the FET Q4, and the output circuit 111 similarly rises to the address voltage Vda. Similarly to the output circuit 112, an address discharge occurs between the scan electrodes, and an address current flows through the scan electrodes with a delay of approximately time ta. Therefore, as shown in FIG. 6, the peak of the address current flowing during one scan period is divided into two peaks, and is reduced to about half.

  By reducing the peak current of the address current in this manner, the voltage drop due to the resistance component of the scan electrode and the voltage drop due to the impedance of the address driver circuit and the scan driver circuit are reduced, and the address discharge can be made stable.

  Next, the FET Q1, the FET Q4, and the FET Q2 are turned off, and the FET Q3 is turned on. The charge charged in the address electrode is collected via the diode Di1, the resonance coil L2, and the diode Di3, and accumulated in the capacitor C1. By connecting the diode Di1, charges can be recovered from both the output circuits 111 and 112.

  Finally, the FET Q5 is turned on to lower the power supply voltages of the output circuits 111 and 112 to the GND potential. After that, this cycle is repeated.

  In the prior art, since the rising phase of the write voltage of the address driver circuit is shifted and the falling timing is made the same, the voltage high level period of the output circuit 111 of the address driver circuit whose phase is delayed is short. However, there is a problem that the panel margin cannot be widened, and if the phase difference is reduced in order to ensure a high level period, the address current does not become two peaks and the current is concentrated, and stable discharge cannot be obtained. It was.

  In the plasma display device of the present invention, the address driver circuit 11 is configured to be able to supply first and second address pulse voltages having different phases, and the first and second address pulse voltages having different phases. The address electrodes of the PDP 10 to which the first address pulse voltage is supplied are divided into two blocks so that the ratio is 4: 8, and the area ratio of the first block to which the first address pulse voltage having an early phase is supplied is determined by the plasma display panel. It is 40% or less of the entire effective display area. Even if the phase difference is reduced by reducing the panel area borne by the output circuit 112 that outputs the address pulse voltage having an early phase, the address current flows in two peaks with the phase difference, and the peak current Is suppressed.

  FIG. 7 shows the relationship between the panel margin when the panel area to which the address pulse voltage having an early phase is supplied is 50% and 40%. As shown in FIG. 7, when the panel area to which the address pulse voltage having an early phase is supplied is set to 40%, the panel margin is widened, and the panel area to which the address pulse voltage having an early phase is supplied is 40%. In the case of%, even if the phase difference is reduced, it can be made wider than the panel margin in the case of 50%.

  As described above, according to the plasma display apparatus according to the present invention, the address driver circuit is configured to be able to supply the first and second address pulse voltages having different phases, and the address electrode of the plasma display panel includes: The area of the first block which is divided into a plurality of blocks of the first and second blocks to which the first and second address pulse voltages are respectively supplied and to which the first address pulse voltage having an early phase is supplied By setting the ratio to 40% or less, even when the configuration of the power recovery circuit in the address driver circuit is simplified, address discharge can be performed stably and a sufficient panel margin can be secured.

  As is apparent from the above description, according to the present invention, a sufficient panel margin can be secured even in a state where the configuration of the power recovery circuit in the address driver circuit is simplified, which is useful for the plasma display device.

The perspective view which shows schematic structure of the panel of the plasma display apparatus by one embodiment of this invention. Explanatory drawing which shows the electrode arrangement of the panel of the plasma display apparatus Block circuit diagram showing an example of a display drive circuit of the plasma display device Signal waveform diagram showing an example of a driving method of the plasma display device Circuit diagram of address driver circuit of the plasma display device Signal waveform diagram explaining the operation waveform of each part of the power recovery circuit of the address driver circuit Characteristic diagram showing the relationship between the phase difference of the address pulse voltage and the panel margin

Explanation of symbols

1, 5 Substrate 2 Display electrode 7 Address electrode 10 Plasma display panel 11 Address driver circuit 12 Scan driver circuit 13 Sustain driver circuit 111, 112 Output circuit

Claims (2)

A plurality of discharge cells configured by providing a plurality of rows of display electrodes and a plurality of rows of address electrodes arranged so as to intersect the display electrodes on a pair of substrates opposed to each other by forming a discharge space. A plasma display panel, and an address driver circuit for supplying an address pulse voltage for writing display data to the address electrodes of the plasma display panel. The address driver circuit includes first and second phase drivers having different phases. The power recovery circuit is configured to be able to supply an address pulse voltage and recovers charges when writing display data to the address electrodes. The power recovery circuit is common to all the address electrodes. provided, the address electrodes of the plasma display panel, the first and second add Dividing into a plurality of blocks of the first and second blocks to which the pulse voltage is respectively supplied, and comparing the area ratio of the first block to which the first address pulse voltage having an early phase is supplied with the second block The plasma display apparatus is characterized in that the timing of the fall of the first and second address pulse voltages is made the same. 2. The plasma display device according to claim 1, wherein the area ratio of the first block to which the first address pulse voltage having an early phase is supplied is 40% or less of the entire effective display area of the plasma display panel. .