JP5011615B2 - Plasma display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display device known as a thin, lightweight display device having a large screen.
[0002]
[Prior art]
A plasma display device is capable of high-speed display compared to a liquid crystal panel, has a wide viewing angle, is easy to increase in size, and is self-luminous, so that the display quality is high. Recently, it has attracted particular attention in technology.
[0003]
In general, in this plasma display device, an ultraviolet ray is generated by gas discharge, and a phosphor is excited by the ultraviolet ray to emit light to perform color display. And the display cell divided by the partition on the board | substrate is provided, and it has the structure by which the fluorescent substance layer is formed in this.
[0004]
This plasma display device is roughly classified into an AC type and a DC type in terms of driving, and there are two types of discharge types: a surface discharge type and a counter discharge type, but high definition, large screen, and simple manufacturing are possible. Therefore, at present, the mainstream of plasma display devices is a surface discharge type of a three-electrode structure, and the structure has a pair of display electrodes adjacent in parallel on one substrate, and on the other substrate. It has an address electrode arranged in a direction intersecting with the display electrode, a partition wall, and a phosphor layer. The phosphor layer can be made relatively thick and is suitable for color display using a phosphor.
[0005]
[Problems to be solved by the invention]
According to the present invention, in such a plasma display device, the self-heating amount of the scan electrode driving IC for supplying a panel driving voltage waveform for performing address discharge and sustain discharge to the scan electrode is reduced, and stable operation is achieved. It is the purpose.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a plasma display device of the present invention includes a plurality of scan electrodes arranged in a row direction of a panel on a pair of substrates that form a discharge space and face each other, and are arranged in parallel with the scan electrodes. A plasma display panel having a plurality of discharge cells is provided by providing a plurality of sustain electrodes and a plurality of address electrodes arranged in the column direction of the panel so as to intersect the scan electrodes and the sustain electrodes. The scan electrode of the plasma display panel is divided into a plurality of blocks with a predetermined number as one unit, and a panel drive voltage waveform for performing address discharge and sustain discharge is supplied to each block of the scan electrode Connects multiple scan electrode driving ICs and is located on the upper side of the panel The can electrode driving IC reduces the driving load of the scan electrode driving IC by reducing the number of output terminals connected to the scan electrode compared to the number of output terminals held by the scan electrode driving IC. It suppresses the amount of self-heating.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
That is, according to the first aspect of the present invention, a plurality of scan electrodes arranged in the row direction of the panel are arranged in parallel with the scan electrodes on a pair of substrates opposed to each other by forming a discharge space. A plasma display panel having a plurality of discharge cells is formed by providing a plurality of sustain electrodes and a plurality of address electrodes arranged in the column direction of the panel so as to intersect the scan electrodes and the sustain electrodes. A plurality of scan electrodes of the plasma display panel are divided into a plurality of blocks with a predetermined number as one unit, and a plurality of panel drive voltage waveforms for supplying address discharge and sustain discharge to each block of the scan electrodes are provided. Scan electrode driving I connected to the upper side of the panel , Compared to the number of output terminals to which the scan electrode driving IC's are those with a reduced number of output terminals connected to the scan electrode.
[0008]
According to the second aspect of the present invention, the plurality of scan electrode driving ICs scan all the output terminals of the scan electrode driving ICs in order from the scan electrode driving IC located on the lower side of the panel. By connecting to the electrodes, the number connected to the scan electrodes of the scan electrode driving IC located on the upper side of the panel is reduced.
[0009]
Further, according to a third aspect of the present invention, a plurality of scan electrodes arranged in the row direction of the panel are arranged in parallel with the scan electrodes on a pair of substrates opposed to each other by forming a discharge space. A plurality of sustain electrodes, and a plurality of address electrodes arranged in the column direction of the panel so as to intersect the scan electrodes and the sustain electrodes, thereby forming a plasma display panel having a plurality of discharge cells, A plurality of scan electrodes of the plasma display panel are divided into a plurality of blocks with a predetermined number as one unit, and a plurality of panel drive voltage waveforms for performing address discharge and sustain discharge are supplied to each block of the scan electrodes. Scan electrode driving I connected to a plurality of scan electrode driving ICs and located at the top of the panel The output timing control pulses to be input to, which is constituted to apply before the address discharge in the first scan electrode of the panel begins.
[0010]
According to a fourth aspect of the present invention, a plurality of scan electrodes arranged in the row direction of the panel are arranged in parallel with the scan electrodes on a pair of substrates opposed to each other by forming a discharge space. A plurality of sustain electrodes, and a plurality of address electrodes arranged in the column direction of the panel so as to intersect the scan electrodes and the sustain electrodes, thereby forming a plasma display panel having a plurality of discharge cells, A plurality of scan electrodes of the plasma display panel are divided into a plurality of blocks with a predetermined number as one unit, and a plurality of panel drive voltage waveforms for performing address discharge and sustain discharge are supplied to each block of the scan electrodes. IC for driving scan electrodes connected to the IC for driving scan electrodes and located on the upper side of the panel One of the outputs to the panel drive voltage waveform by amplitude conversion by a resistor, which is constituted so as to control signals of the next scan electrode driving processing IC. Further, the resistor may be configured to perform amplitude and polarity conversion.
[0011]
Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8, but the embodiment of the present invention is not limited thereto.
[0012]
First, the structure of the plasma display panel in the plasma display device will be described with reference to FIG. As shown in FIG. 1, on a transparent front substrate 1 such as a glass substrate, a plurality of stripe-shaped display electrodes 2 paired with a scan electrode and a sustain electrode are formed, and covers the electrode group. Thus, the dielectric layer 3 is formed, and the protective film 4 is formed on the dielectric layer 3.
[0013]
Further, a plurality of rows of stripes covered with an overcoat layer 6 are formed on the rear substrate 5 opposite to the front substrate 1 so as to intersect the display electrodes 2 of the scan electrodes and the sustain electrodes. Address electrodes 7 are formed. On the overcoat layer 6 between the address electrodes 7, a plurality of barrier ribs 8 are arranged in parallel with the address electrodes 7, and a phosphor layer 9 is provided on the side surface between the barrier ribs 8 and on the surface of the overcoat layer 6. Yes.
[0014]
The substrate 1 and the substrate 5 are opposed to each other with a minute discharge space so that the display electrode 2 and the address electrode 7 of the scan electrode and the sustain electrode are almost orthogonal to each other, and the periphery is sealed, In the discharge space, one or a mixed gas of helium, neon, argon, and xenon is sealed as a discharge gas. Further, the discharge space is divided into a plurality of sections by partition walls 8 to provide a plurality of discharge cells where the intersections of the display electrodes 2 and the address electrodes 7 are located, and each of the discharge cells has red, green and blue colors. The phosphor layers 9 are sequentially arranged one by one so that
[0015]
FIG. 2 shows an electrode arrangement of this plasma display panel. As shown in FIG. 2, the scan electrode, the sustain electrode, and the address electrode have a matrix configuration of M rows × N columns, and a plurality of M in the row direction. The scan electrodes SCN1 to SCNM of the rows and the sustain electrodes SUS1 to SUSM arranged in parallel thereto are arranged, and the addresses of a plurality of N columns are arranged so as to intersect the scan electrodes SCN1 to SCNM and the sustain electrodes SUS1 to SUSM in the column direction. Electrodes D1 to DN are arranged.
[0016]
In the plasma display panel having such an electrode configuration, an address pulse is applied between the address electrode and the scan electrode by applying a write pulse between the address electrode and the scan electrode, and after selecting the discharge cell, the scan electrode By applying a periodic sustain pulse that is alternately inverted between the sustain electrode and the sustain electrode, a sustain discharge is performed between the scan electrode and the sustain electrode, and a predetermined display is performed.
[0017]
In general, an address / display period separation method is used as a gradation display driving method of a plasma display device. In this method, one field is temporally divided into a plurality of subfields. For example, when 256 gradation display is performed with 8 bits, one field is divided into eight subfields. Each subfield is divided into an address period in which an address discharge for selecting a lighted cell is performed and a sustain period (a display discharge period) in which a sustain discharge for display is performed.
[0018]
In this method, scanning by address discharge is performed on the entire surface of the PDP from the first line to the m-th line in each subfield, and sustain discharge is performed at the end of the entire address discharge.
[0019]
FIG. 3 shows the configuration of the display drive circuit of the plasma display device in this embodiment. As shown in FIG. 3, the plasma display panel (PDP) 10 having the configuration shown in FIG. 1, the address driver circuit 11, the scan driver circuit 12, the sustain driver circuit 13, the discharge control timing generation circuit 14, the power supply circuits 15 and 16, A / D converter (analog / digital converter) 17, a scanning number conversion unit 18, and a subfield conversion unit 19 are provided.
[0020]
In the circuit of FIG. 3, first, the video signal VD is input to the A / D converter 17. Further, the horizontal synchronizing signal H and the vertical synchronizing signal V are given to the discharge control timing generation circuit 14, the A / D converter 17, the scanning number conversion unit 18 and the subfield conversion unit 19. The A / D converter 17 converts the video signal VD into a digital signal and supplies the image data to the scanning number conversion unit 18.
[0021]
The scanning number conversion unit 18 converts the image data into image data having the number of lines corresponding to the number of pixels of the PDP 10, and supplies the image data for each line to the subfield conversion unit 19. The subfield conversion unit 19 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and serializes each bit of each pixel data to the address driver circuit 11 for each subfield. Output to. The address driver circuit 11 is connected to the power supply circuit 15, converts serially supplied data from the subfield conversion unit 19 for each subfield into parallel data, and applies voltages to a plurality of address electrodes based on the parallel data. Supply.
[0022]
The discharge control timing generation circuit 14 generates discharge control timing signals SC and SU with reference to the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the scan driver circuit 12 and the sustain driver circuit 13, respectively. The scan driver circuit 12 includes an output circuit 121 and a shift register 122. The sustain driver circuit 13 includes an output circuit 131 and a shift register 132. The scan driver circuit 12 and the sustain driver circuit 13 are connected to a common power supply circuit 16.
[0023]
The shift register 122 of the scan driver circuit 12 applies the discharge control timing signal SC supplied from the discharge control timing generation circuit 14 to the output circuit 121 while shifting in the vertical scanning direction. The output circuit 121 sequentially supplies drive signal voltages to the plurality of scan electrodes in response to the discharge control timing signal SC supplied from the shift register 122.
[0024]
The shift register 132 of the sustain driver circuit 13 supplies the discharge control timing signal SU supplied from the discharge control timing generation circuit 14 to the output circuit 131 while shifting in the vertical scanning direction. The output circuit 131 sequentially supplies drive signal voltages to the plurality of sustain electrodes in response to the discharge control timing signal SU supplied from the shift register 132.
[0025]
FIG. 4 shows an example of a timing chart of the display driving circuit of the plasma display device. As shown in FIG. 4, after all the sustain electrodes SUS1 to SUSM are held at 0 (V) in the writing period, A positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to discharge cells to be displayed in the first row, and a negative scan pulse voltage -Vs (V) is applied to scan electrode SCN1 in the first row. When applied to each, an address discharge occurs at the intersection of predetermined address electrodes D1 to DN and the first row scan electrode SCN1.
[0026]
Next, a positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to discharge cells to be displayed in the second row, and a negative scan pulse voltage -Vs is applied to the scan electrode SCN2 in the second row. When (V) is applied to each, an address discharge occurs at the intersection of the predetermined address electrodes D1 to DN and the scan electrode SCN2 in the second row.
[0027]
The same operation as described above is sequentially performed. Finally, a positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to discharge cells to be displayed in the Mth row, and the Mth row is scanned. When a negative scan pulse voltage −Vs (V) is applied to each electrode SCNM, an address discharge occurs at the intersection of predetermined address electrodes D1 to DN and the Mth row scan electrode SCNM.
[0028]
In the next sustain period, all the scan electrodes SCN1 to SCNM are once held at 0 (V), and when a negative sustain pulse voltage −Vm (V) is applied to all the sustain electrodes SUS1 to SUSM, an address discharge is caused. Further, a sustain discharge occurs between the scan electrodes SCN1 to SCNM and the sustain electrodes SUS1 to SUSM at the intersection. Next, by applying negative sustain pulse voltage -Vm (V) alternately to all the scan electrodes SCN1 to SCNM and all the sustain electrodes SUS1 to SUSM, the sustain discharge is continuously generated in the display discharge cells. Panel display is performed by the light emission of the sustain discharge.
[0029]
In the next erasing period, all the scan electrodes SCN1 to SCNM are temporarily held at 0 (V), and when the erasing pulse voltage -Ve (V) is applied to all the sustain electrodes SUS1 to SUSM, an erasing discharge is caused and discharged. Stops.
[0030]
Through the above operation, one screen is displayed on the plasma display device.
[0031]
By the way, in such a plasma display device, the heat generated in the device flows to the upper part of the panel. Therefore, among the scan electrode driving ICs constituting the scan driver circuit, the driving for driving the scan electrode located on the upper side of the panel. As the IC increases, the ambient temperature rises and the temperature operating conditions become severe. Therefore, the heat dissipation structure for using the scan electrode driving IC, the operating voltage, and the number of pulse applications are all limited by the ambient temperature of the scan electrode driving IC located on the upper side of the panel and the amount of self-heating. There was a problem.
[0032]
The present invention solves such problems, and specific embodiments thereof will be described below.
[0033]
As described above, the shift register 122 of the scan driver circuit 12 applies the discharge control timing signal SC supplied from the discharge control timing generation circuit 14 to the output circuit 121 while shifting it in the vertical scanning direction. In response to the discharge control timing signal SC supplied from the shift register 122, the drive signal voltage is supplied to the plurality of scan electrodes in order.
[0034]
In a current plasma display device, it is common to use a plurality of scan electrode driving ICs that perform these series of operations, and the number of output pins of the scan electrode driving ICs used is mainly 64. .
[0035]
That is, the scan electrode of the plasma display panel is divided into a plurality of blocks with a predetermined number as one unit, and a panel driving voltage waveform for performing address discharge and sustain discharge is supplied to each block of the scan electrode A plurality of scan electrode driving ICs are connected. For example, in an apparatus having 480 scanning lines, eight scan electrode driving ICs are used when the upper and lower divided driving is performed. Here, the upper and lower divided driving means a driving method in which data electrodes are respectively provided on the upper and lower sides of the panel, and the operations during the writing period are performed independently and simultaneously.
[0036]
Therefore, there are four scan electrode driving ICs responsible for the upper half of the panel, and the lowest scan electrode driving IC among them is (480/2 divisions) − (3 ICs × 64) = Forty-eight are connected to the scan electrodes. That is, the scan electrode driving IC located at the bottom is in a state where there is no load for 16 lines compared to the other scan electrode driving ICs. The same applies to the scan electrode driving IC group responsible for the lower half of the panel.
[0037]
In the present invention, the heat generated in the apparatus flows upward, and the ambient temperature becomes higher as the position is higher. Therefore, the scan electrode driving IC located on the upper side of the panel is provided with 16 loads without load. Allocating and suppressing self-heating. That is, the scan electrode driving IC located on the upper side of the panel has a smaller number of output terminals connected to the scan electrodes than the number of output terminals held by the scan electrode driving IC.
[0038]
FIG. 5 is a diagram showing a configuration of a main circuit of a scan driver circuit portion in the display drive circuit shown in FIG. 3 in one embodiment of the present invention, which will be described below with reference to FIG.
[0039]
In FIG. 5, 20 is a panel, 21-24 are scan electrode driving ICs, 25-27 are control signal generating circuits, and the scan electrodes located on the upper side of the panel 20 in the scan electrode driving ICs 21, 22, 23 The drive IC has a smaller number of output terminals connected to the scan electrodes than the number of output terminals held by the scan electrode drive ICs 21, 22, and 23. Further, the scan electrode driving ICs 21, 22, 23, and 24 output drive pulses while shifting the discharge control timing signal SC in the vertical scanning direction as in the prior art.
[0040]
That is, the discharge control timing signal SC is shifted by 64 in the scan electrode driving IC 21 and then transferred to the next scan electrode driving IC 22. Conventionally, the scan electrode drive IC 21 is transferred from the SC output terminal to the next scan electrode drive IC 22 input terminal. In the present invention, the scan electrode drive ICs 21, 22, 23 are connected to the scan electrodes. The control signal generation circuits 25, 26 and 27, which receive the output of the output terminal in the order obtained by adding 1 to the number, convert the amplitude and input it as the next discharge control timing signal SC.
[0041]
In this way, by connecting the control signal generating circuits 25, 26, and 27 between the scan electrode driving ICs 21, 22, 23, and 24, respectively, the load on each IC can be reduced arbitrarily, and the scan located at the top. The ambient temperature of the electrode driving IC and the temperature due to self-heating can be made closer to the ambient temperature of the scan electrode driving IC located below and the temperature due to self-heating.
[0042]
FIG. 6 shows an example according to another embodiment of the present invention. In the example of FIG. 6, the upper half IC group in the case of the upper and lower divided driving is shown.
[0043]
Similarly to the above example, the scan electrode driving IC 21 receives the discharge control timing signal SC from the discharge control timing generation circuit 14, and all the scan electrode driving ICs 21, 22, 23, 24 receive from the output terminal pins. A clock signal CLK that determines the output timing and a signal CL that determines the low period of the output are input.
[0044]
In the example shown in FIG. 6, output terminals are connected to the scan electrodes in order from the scan electrode driving IC 24 located on the lower side of the panel 20. As a result, when the panel 20 has 480 scanning lines, the scan electrode driving IC 21 located at the uppermost portion of the panel 20 has {64- (480/2 divided)-(3 ICs × 64 ICs). )} = 16 lines are not connected to the scan electrodes and no load is applied.
[0045]
According to the example of FIG. 6, the effect of reducing self-heating by 15 ° C. or more can be obtained in the uppermost scan electrode driving IC 21 by adding only one control signal generation circuit 28.
[0046]
FIG. 7 is an explanatory diagram showing an example of the control signal generation circuit. In FIG. 7, if the discharge control timing signal SC from the discharge control timing generation circuit 14 and the output of the scan electrode driving IC 21 have the same pulse polarity, FIG. The amplitude of the control signal is set to be small by resistance division by the two resistors 29 and 30 and is input as the discharge control timing pulse SC of the scan electrode driving IC 22.
[0047]
On the other hand, when the pulse polarities are different, the polarity is inverted by a simple switching circuit using the transistor 31 and the resistors 32, 33, and 34 and is input as the discharge control timing pulse SC of the next scan electrode driving IC 22. The number of output terminals connected to the scan electrodes of the scan electrode driving IC located on the upper side of the panel can be reduced with a circuit having a simple configuration.
[0048]
Next, a plasma display apparatus according to another embodiment of the present invention will be described with reference to FIG.
[0049]
First, a discharge control timing signal SC is inputted from the discharge control timing generation circuit 14 to the scan electrode driving IC located at the upper part of the panel, and the timing outputted from each output pin is inputted to all the scan electrode driving ICs. CLK to be determined and CL to determine the low period of the output are input. Then, after the discharge control timing signal SC is shifted by 64 lines in the vertical scanning direction within the first scan electrode driving IC at the top of the panel, the discharge control timing signal SC is input to the next scan electrode driving IC. . Thereafter, similarly, the scan electrode driving IC is connected so that the discharge control timing signal SC is input to the next scan electrode driving IC.
[0050]
In the present embodiment, as shown in FIG. 8, the discharge control timing signal SC and the CLK signal input to the scan electrode driving IC located at the uppermost part of the panel are scanned with the first scan electrode driving waveform of the panel. It is applied before the pulse application time. If it is desired to reduce the load on the scan electrode driving IC by 16 lines, the CLK signal is configured to be input earlier by the scan pulse application time × 16 times as shown in FIG.
[0051]
As a result, 16 pieces of output data are shifted in the scan electrode driving IC, and the 17th output data is output from the 17th output terminal. From this point, the first scan electrode of the panel is driven. The output up to the 16th of the scan electrode driving IC at the top of the panel is set to a no-load state, and the output of the scan electrode driving IC at the top of the panel is changed without changing the wiring and configuration of the subsequent scan electrode group. Is set to a no-load state, and the load can be reduced.
[0052]
As described above, the output timing control pulse of the discharge control timing signal SC and the CLK signal input to the scan electrode driving IC located at the top of the panel is applied before the address discharge of the first scan electrode of the panel starts. Thus, if a part of the output terminal of the scan electrode driving IC at the top of the panel (16 in the example of FIG. 8) is wired so as not to be connected to the scan electrode of the panel, without adding a circuit, The load on the scan electrode driving IC located at the top of the panel can be reduced.
[0053]
【Effect of the invention】
As is apparent from the above description, according to the plasma display device according to the present invention, the load on the scan electrode driving IC at the top of the panel where the ambient temperature is likely to rise due to the structure of the device is reduced, and the amount of self-heating is reduced. As a result, the scan electrode driving IC can be operated stably.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a schematic configuration of a panel of a plasma display device according to an embodiment of the present invention. FIG. 2 is an explanatory view showing an electrode arrangement of the panel of the plasma display device. FIG. 4 is a block diagram showing an example of a display driving circuit. FIG. 4 is a signal waveform diagram showing an example of a driving method of the plasma display apparatus. FIG. 5 is a schematic diagram showing a main circuit configuration of a display driving circuit of the plasma display apparatus. FIG. 6 is a schematic diagram showing a main circuit configuration of a display drive circuit according to another embodiment of the plasma display device. FIG. 7 shows a main circuit configuration of a display drive circuit according to another embodiment of the plasma display device. FIG. 8 is a waveform diagram for explaining the operation of the main circuit of the display drive circuit according to another embodiment of the plasma display device. Description]
1, 5 Substrate 2 Display electrode 7 Address electrode 20 Panel 21, 22, 23, 24 Scan electrode driving IC
25, 26, 27, 28 Control signal generation circuit 29, 30, 32, 33, 34 Resistance

Claims (1)

A plurality of scan electrodes arranged in the row direction of the panel on a pair of substrates facing each other to form a discharge space, a plurality of sustain electrodes arranged in parallel to the scan electrodes, and the scan electrodes and the sustain electrodes A plasma display panel having a plurality of discharge cells by providing a plurality of address electrodes arranged in the column direction of the panel so as to intersect the electrodes;
A plurality of scan electrode drive ICs for sequentially supplying a panel drive voltage for performing a write operation to the scan electrodes by a discharge control timing signal applied by shifting to a plurality of output terminals connected to the scan electrodes;
A control signal generation circuit for outputting the discharge control timing signal to the scan electrode driving IC,
Among the plurality of scan electrode driving ICs, the scan electrode driving ICs arranged at the upper part in the vertical direction of the plasma display panel are connected to the scan electrodes in comparison with the number of output terminals held by the scan electrode driving ICs. The number of output terminals to be connected is small, and the number of output terminals of the scan electrode driving ICs arranged other than the upper part in the vertical direction is less than the number connected to the scan electrodes,
The output of the output terminal in the order obtained by adding 1 to the number of output terminals connected to the scan electrode is input to the control signal generating circuit, and the control signal generating circuit outputs a discharge control timing signal to the next scan electrode driving IC. A plasma display device.

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