JP2003029701A - Plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the generation of heat in the IC(integrated circuit) for driving scan electrodes in a plasma display device. SOLUTION: This display device has a plurality of ICs for driving scan electrodes which are provided in order to supply a panel driving voltage waveform for performing addressing discharge and sustaining discharge to scan electrode of the plasma display panel 20 and, in an IC for driving scan electrodes 21 which is positioned at the upper-part side of the panel 20, the number of output terminals which are connected to scan electrodes of the panel 20 is made smaller than that of output terminals possessed by the IC 21. By this structure, the load of the IC 21 for driving the scan electrodes 21 whose ambient temperature is most apt to rise from the structural viewpoint of the plasma display device of the upper part of the panel 20 becomes light and the self-generation of heat of the IC 21 can be reduced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a large screen, thin type,
The present invention relates to a plasma display device known as a lightweight display device.

[0002]

2. Description of the Related Art Plasma display devices are capable of high-speed display and have a wide viewing angle compared to liquid crystal panels.
Recently, the flat panel display technology has been attracting a lot of attention because it can be easily upsized and its display quality is high because it is a self-luminous type.

Generally, in this plasma display device, ultraviolet rays are generated by gas discharge, and the ultraviolet rays excite phosphors to emit light, thereby performing color display. The display cell partitioned by the partition is provided on the substrate, and the phosphor layer is formed on the display cell.

This plasma display device is roughly classified into an AC type and a DC type in terms of driving, and there are two types of discharge types: a surface discharge type and a counter discharge type. However, high definition, large screen and Due to the ease of manufacturing, at present, the mainstream plasma display device is a surface discharge type of three-electrode structure, which has a pair of display electrodes adjacent in parallel on one substrate and the other. It has address electrodes arranged in a direction intersecting with the display electrodes on the substrate, partition walls, and a phosphor layer. Since the phosphor layer can be relatively thick, it is suitable for color display by the phosphor.

[0005]

SUMMARY OF THE INVENTION In the plasma display device as described above, the self-heating amount of the scan electrode driving IC for supplying the panel driving voltage waveform for performing the address discharge and the sustain discharge to the scan electrode. The purpose is to reduce the noise and to make the operation stable.

[0006]

In order to achieve the above object, a plasma display device of the present invention comprises a plurality of scan electrodes arranged in a row direction of a panel on a pair of substrates forming a discharge space and facing each other. And a plurality of sustain electrodes arranged in parallel with the scan electrodes, and a plurality of address electrodes arranged in the column direction of the panel so as to intersect with the scan electrodes and the sustain electrodes. A plasma display panel having cells is formed, the scan electrodes of the plasma display panel are divided into a plurality of blocks with a predetermined number of units as one unit, and each block of the scan electrodes is subjected to address discharge and sustain discharge. Connect a plurality of scan electrode driving ICs for supplying a panel driving voltage waveform, The scan electrode driving IC located on the upper side of the panel is driven by reducing the number of output terminals connected to the scan electrode as compared with the number of output terminals of the scan electrode driving IC. The driving load of the IC for use is reduced and the amount of self-heating is suppressed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS That is, the invention according to claim 1 of the present invention comprises a plurality of scan electrodes arranged in the row direction of the panel on a pair of substrates facing each other forming a discharge space, and the scan electrodes. A plasma having a plurality of discharge cells by providing a plurality of sustain electrodes arranged in parallel with the electrodes and a plurality of address electrodes arranged in the column direction of the panel so as to intersect these scan electrodes and sustain electrodes. A panel drive voltage waveform for configuring a display panel, dividing the scan electrodes of the plasma display panel into a plurality of blocks with a predetermined number of units as one unit, and performing address discharge and sustain discharge in each block of the scan electrodes. Are connected to a plurality of scan electrode driving ICs for supplying the liquid crystal and are located on the upper side of the panel. Scanning electrode driving IC, as compared to the number of output terminals to which the scan electrode driving IC's are those with a reduced number of output terminals connected to the scan electrode.

The invention according to claim 2 of the present invention is
The plurality of scan electrode driving ICs are located on the upper side of the panel by connecting all the output terminals of the scan electrode driving ICs to the scan electrodes in order from the scan electrode driving ICs located on the lower side of the panel. The number of scan electrodes connected to the scan electrodes of the scan electrode driving IC is reduced.

Further, according to a third aspect of the present invention, a plurality of scan electrodes arranged in the row direction of the panel are arranged on a pair of substrates which form a discharge space and face each other, and the scan electrodes are parallel to the scan electrodes. A plasma display panel having a plurality of discharge cells is provided by providing a plurality of sustain electrodes and a plurality of address electrodes arranged in the column direction of the panel so as to intersect these scan electrodes and sustain electrodes. The scan electrodes of the plasma display panel are divided into a plurality of blocks with a predetermined number of units as one unit, and a panel drive voltage waveform for performing address discharge and sustain discharge is supplied to each block of the scan electrodes. For connecting a plurality of scan electrode driving ICs for scanning and located at the top of the panel The output timing control pulses to be input pole to the driving IC, it is obtained by configured to apply before the address discharge in the first scan electrode of the panel begins.

The invention according to claim 4 of the present invention is
On a pair of substrates facing each other to form a discharge space, a plurality of scan electrodes arranged in the row direction of the panel, and a plurality of sustain electrodes arranged in parallel with the scan electrodes,
A plasma display panel having a plurality of discharge cells is formed by providing a plurality of address electrodes arranged in the column direction of the panel so as to intersect these scan electrodes and sustain electrodes, and the scan electrodes of the plasma display panel are formed. Is divided into a plurality of blocks with a predetermined number as one unit, and a plurality of scan electrode driving ICs for supplying a panel drive voltage waveform for performing address discharge and sustain discharge to each block of the scan electrode. One of the panel drive voltage waveforms that are connected and output from the scan electrode drive IC located on the upper side of the panel is amplitude-converted by a resistor and used as a control signal for the next scan electrode drive IC. It is configured in. Further, the resistor may be configured to perform amplitude and polarity conversion.

A plasma display device according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 8, but the embodiment of the present invention is not limited to this.

First, the structure of the plasma display panel in the plasma display device will be described with reference to FIG. As shown in FIG. 1, a plurality of stripe-shaped display electrodes 2 forming pairs of scan electrodes and sustain electrodes are formed on a transparent front substrate 1 such as a glass substrate and cover the electrode group. Thus, the dielectric layer 3 is formed, and the protective film 4 is formed on the dielectric layer 3.

A plurality of columns covered with an overcoat layer 6 are formed on the rear substrate 5 facing the front substrate 1 so as to intersect the display electrodes 2 of scan electrodes and sustain electrodes. Stripe-shaped address electrodes 7 are formed. A plurality of partition walls 8 are arranged on the overcoat layer 6 between the address electrodes 7 in parallel with the address electrodes 7, and a phosphor layer 9 is provided on a side surface between the partition walls 8 and a surface of the overcoat layer 6. There is.

The substrate 1 and the substrate 5 are a display electrode 2 and an address electrode 7 of scan electrodes and sustain electrodes.
Are arranged so as to be substantially orthogonal to each other, and are opposed to each other with a minute discharge space interposed therebetween, and the periphery is sealed, and one kind of helium, neon, argon, and xenon or a mixed gas is discharged into the discharge space. It is enclosed as a gas. Further, the discharge space is partitioned into a plurality of partitions by partition walls 8 to provide a plurality of discharge cells at which the intersections of the display electrodes 2 and the address electrodes 7 are located, and each of the discharge cells has red, green, and blue. The phosphor layers 9 are sequentially arranged for each color so that

FIG. 2 shows an electrode array of this plasma display panel. As shown in FIG. 2, the scan electrodes, the sustain electrodes and the address electrodes have a matrix structure of M rows × N columns, and in the row direction. A plurality of M rows of scan electrodes SCN1 to SCNM and sustain electrodes SUS1 to SUSM arranged in parallel therewith are arranged, and a plurality of N electrodes are arranged in the column direction so as to intersect the scan electrodes SCN1 to SCNM and the sustain electrodes SUS1 to SUSM. Column address electrodes D1 to DN are arranged.

In the plasma display panel having such an electrode structure, by applying a write pulse between the address electrode and the scan electrode, an address discharge is performed between the address electrode and the scan electrode, and after selecting a discharge cell. , Between the scan electrode and the sustain electrode,
By applying a periodic sustain pulse that is alternately inverted, a sustain discharge is generated between the scan electrode and the sustain electrode, and a predetermined display is performed.

As a gradation display driving method for a plasma display device, an address / display period separation method is generally used. In this method, one field is temporally divided into a plurality of subfields. For example, when displaying 256 gradations with 8 bits, 1 field is 8
Split into two subfields. In addition, each subfield is divided into an address period in which an address discharge for selecting a lighted cell is performed and a sustain period (display discharge period) in which a sustain discharge for display is performed.

In this method, the entire surface of the PDP is scanned by the address discharge from the first line to the m-th line in each subfield, and the sustain discharge is performed at the end of the whole surface address discharge.

FIG. 3 shows the configuration of the display drive circuit of the plasma display device according to the present embodiment. As shown in FIG. 3, the plasma display panel (PDP) 10 having the configuration shown in FIG.
Scan driver circuit 12 and sustain driver circuit 1
3, discharge control timing generation circuit 14, power supply circuit 15,
16, A / D converter (analog / digital converter)
17, scan number converter 18, and subfield converter 1
9 is equipped.

In the circuit of FIG. 3, first, the video signal VD
Is input to the A / D converter 17. The horizontal synchronization signal H and the vertical synchronization signal V are supplied to the discharge control timing generation circuit 14, the A / D converter 17, the scanning number conversion unit 18,
It is given to the subfield converter 19. The A / D converter 17 converts the video signal VD into a digital signal and supplies the image data to the scanning number conversion unit 18.

The scanning number converter 18 converts the image data into PDP.
Converted to image data of the number of lines according to the number of pixels of 10,
The image data for each line is converted into the subfield conversion unit 19
Give to. The subfield conversion unit 19 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and the bit of each pixel data for each subfield is addressed by the address driver circuit 11.
Output serially to. The address driver circuit 11 is
It is connected to the power supply circuit 15 and converts the data serially given from the subfield converter 19 for each subfield into parallel data, and supplies a voltage to a plurality of address electrodes based on the parallel data.

The discharge control timing generation circuit 14 generates discharge control timing signals SC and SU with reference to the horizontal synchronizing signal H and the vertical synchronizing signal V, and supplies them to the scan driver circuit 12 and the sustain driver circuit 13, respectively. The scan driver circuit 12 includes an output circuit 121 and a shift register 122. The sustain driver circuit 13 also has an output circuit 131 and a shift register 132. The scan driver circuit 12 and the sustain driver circuit 13 are connected to a common power supply circuit 16.

The shift register 122 of the scan driver circuit 12 shifts the discharge control timing signal SC given from the discharge control timing generation circuit 14 in the vertical scanning direction and gives it to the output circuit 121. Output circuit 121
Supplies the drive signal voltage to the plurality of scan electrodes in order in response to the discharge control timing signal SC provided from the shift register 122.

The shift register 132 of the sustain driver circuit 13 shifts the discharge control timing signal SU supplied from the discharge control timing generation circuit 14 to the output circuit 131 while shifting it in the vertical scanning direction. Output circuit 131
Supplies the drive signal voltage to the plurality of sustain electrodes in order in response to the discharge control timing signal SU provided from the shift register 132.

FIG. 4 shows an example of a timing chart of the display drive circuit of this plasma display device.
As shown in FIG. 4, in the writing period, after all the sustain electrodes SUS1 to SUSM are held at 0 (V), positive voltages are applied to the predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed in the first row. Write pulse voltage + Vw (V)
When a negative scan pulse voltage −Vs (V) is applied to the scan electrodes SCN1 of the first row, the address discharge is generated at the intersections of the predetermined address electrodes D1 to DN and the scan electrodes SCN1 of the first row. Occur.

Next, a positive write pulse voltage + Vw (V) is applied to the predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed in the second row, and the scan electrode SCN2 in the second row.
When a negative scan pulse voltage -Vs (V) is applied to each of them, an address discharge occurs at the intersection of the predetermined address electrodes D1 to DN and the scan electrode SCN2 of the second row.

The same operation as described above is sequentially performed, and finally a positive write pulse voltage + Vw (V) is applied to predetermined address electrodes D1 to DN corresponding to the discharge cells to be displayed in the Mth row.
When a negative scan pulse voltage −Vs (V) is applied to the scan electrode SCNM of the M-th row, predetermined address electrodes D1 to DN and the scan electrode SCN of the M-th row.
Address discharge occurs at the intersection with M.

In the next sustain period, all scan electrodes S are
When CN1 to SCNM are once held at 0 (V) and a negative sustain pulse voltage -Vm (V) is applied to all sustain electrodes SUS1 to SUSM, scan electrodes SCN1 to SCNM at the intersections where the address discharge occurs. A sustain discharge occurs between the sustain electrodes SUS1 to SUSM and the sustain electrodes SUS1 to SUSM. Next, a negative sustain pulse voltage -Vm (V) is alternately applied to all scan electrodes SCN1 to SCNM and all sustain electrodes SUS1 to SUSM, so that sustain discharge continues in the discharge cells to be displayed. Panel display is performed by the emission of this sustain discharge.

In the next erase period, all the scan electrodes SCN1 to SCNM are once held at 0 (V), and
When the erase pulse voltage -Ve (V) is applied to all the sustain electrodes SUS1 to SUSM, erase discharge occurs and the discharge is stopped.

By the above operation, one screen is displayed on the plasma display device.

By the way, in such a plasma display device, the heat generated in the device flows to the upper part of the panel. Therefore, of the scan electrode driving ICs constituting the scan driver circuit, the scan located on the upper part side of the panel. As the electrode driving IC increases in ambient temperature, temperature operating conditions become more severe. Therefore, the heat dissipation structure for using the scan electrode driving IC, the used voltage, and the number of pulse applications are all limited by the ambient temperature and the amount of self-heating of the scan electrode driving IC located on the upper side of the panel. There were challenges.

The present invention solves such a problem, and a specific embodiment thereof will be described below.

As described above, the shift register 122 of the scan driver circuit 12 controls the discharge control timing signal SC supplied from the discharge control timing generation circuit 14.
Is given to the output circuit 121 while being shifted in the vertical scanning direction,
The output circuit 121 sequentially supplies a drive signal voltage to the plurality of scan electrodes in response to the discharge control timing signal SC provided from the shift register 122.

In the current plasma display device, it is general to use a plurality of scan electrode driving ICs for performing these series of operations, and the number of output pins of the scan electrode driving ICs used is 64. Mainstream.

That is, the scan electrodes of this plasma display panel are divided into a plurality of blocks with a predetermined number of units as one unit, and a panel drive voltage waveform for performing address discharge and sustain discharge is supplied to each block of the scan electrodes. For this purpose, a plurality of scan electrode driving ICs are connected. For example, in a device having 480 scanning lines, eight scan electrode driving ICs are used when the upper and lower split driving is performed. Up and down 2 here
Divided driving is a driving method in which data electrodes are provided on the upper and lower sides of the panel and the operations during the writing period are performed independently at the same time.

Therefore, there are four scan electrode driving ICs which are in charge of the upper half of the panel, and the scan electrode driving IC located at the bottom of the panel is (480 lines / 2 divisions)-(3 ICs × 64). Books) = 48 are connected to the scan electrodes. In other words, the scan electrode driving IC located at the bottom is 16 times larger than the other scan electrode driving ICs.
There is no load for the time being. The same applies to the scan electrode driving IC group which is in charge of the lower half of the panel.

In the present invention, the heat generated in the device flows to the upper part, and the ambient temperature becomes higher as it is located higher.
In the scan electrode driving IC located on the upper side of the panel,
16 lines without this load are allocated to suppress self-heating. That is, the scan electrode driving IC located on the upper side of the panel has a smaller number of output terminals connected to the scan electrodes than the number of output terminals held by the scan electrode driving IC.

FIG. 5 shows an embodiment of the present invention.
FIG. 4 is a diagram showing a configuration of a main circuit of a scan driver circuit portion in the display drive circuit shown in FIG. 3, which will be described below with reference to FIG. 5.

In FIG. 5, reference numeral 20 designates panels 21 to 24.
Is a scan electrode driving IC, 25-27 are control signal generating circuits, and scan electrode driving ICs 21, 22, 23
In, the scan electrode driving ICs located on the upper side of the panel 20 are the scan electrode driving ICs 21, 22, 2
The number of output terminals connected to the scan electrodes is smaller than the number of output terminals that 3 has. Further, the scan electrode driving ICs 21, 22, 23, 24 output drive pulses while shifting the discharge control timing signal SC in the vertical scanning direction as in the conventional case.

That is, the discharge control timing signal SC is shifted by 64 lines inside the scan electrode driving IC 21 and then transferred to the next scan electrode driving IC 22. In the past, the output from the SC output terminal of the scan electrode driving IC 21 was passed to the input terminal of the next scan electrode driving IC 22, but in the present invention, the scan electrode driving I
In C21, 22, 23, the control signal generating circuits 25, 26, 27, which receive the output of the output terminals in the order of adding 1 to the number of the electrodes connected to the scan electrodes, perform amplitude conversion to perform the next discharge control timing. It is input as the signal SC.

In this way, the scan electrode driving IC 21,
Control signal generating circuit 25, 22, 23 and 24 respectively
By connecting 26 and 27, the load on each IC can be arbitrarily reduced, and the ambient temperature of the scan electrode driving IC located above and the temperature due to self-heating and the scan electrode driving IC located below The ambient temperature and the temperature due to self-heating can be brought close to each other.

FIG. 6 shows an example according to another embodiment of the present invention. In the example of FIG. 6, the upper half IC group in the case of the upper and lower two-division driving is shown.

Similar to the above example, a scan electrode driving IC
21, a discharge control timing signal SC is input from the discharge control timing generation circuit 14, and a clock signal CLK that determines the timing of output from each output terminal pin to all scan electrode driving ICs 21, 22, 23, 24.
And a signal CL that determines the low period of the output.

In the example shown in FIG. 6, the output terminals are sequentially connected to the scan electrodes from the scan electrode driving IC 24 located on the lower side of the panel 20. As a result, when the panel 20 has 480 scanning lines, the scan electrode driving IC 21 located at the top of the panel 20 is {64
Book- (480 lines / 2 divisions)-(3 ICs x 64)} =
16 lines are not connected to the scan electrodes and become unloaded.

According to the example of FIG. 6, the effect of reducing self-heating by 15 ° C. or more in the uppermost scan electrode driving IC 21 can be obtained by only adding one control signal generating circuit 28.

FIG. 7 is an explanatory diagram showing an example of the control signal generation circuit. In FIG. 7, the discharge control timing generation circuit 1 is shown.
If the pulse polarities of the discharge control timing signal SC from 4 and the output of the scan electrode driving IC 21 are the same, the amplitude of the control signal is set small by resistance division by the two resistors 29 and 30 to drive the scan electrode. It is configured to be input as the discharge control timing pulse SC of the IC 22 for use.

On the other hand, when the pulse polarities are different, the polarity is inverted by a simple switching circuit using the transistor 31 and the resistors 32, 33 and 34, and is input as the discharge control timing pulse SC for the next scan electrode driving IC 22. The scan electrode driving IC located on the upper side of the panel with a simple circuit configuration.
The number of output terminals connected to the scan electrodes can be reduced.

Next, a plasma display device according to another embodiment of the present invention will be described with reference to FIG.

First, the discharge control timing signal SC is input from the discharge control timing generation circuit 14 to the scan electrode driving ICs located on the upper part of the panel, and the output pins are output to all the scan electrode driving ICs. CLK that determines the timing to be set, and C that determines the Low period of the output
Enter L. Then, after shifting the discharge control timing signal SC by 64 lines in the vertical scanning direction inside the first scan electrode driving IC in the upper part of the panel, the discharge control timing signal SC is input to the next scan electrode driving IC. . After that, similarly, the scan electrode driving IC is connected so that the discharge control timing signal SC is input to the next scan electrode driving IC.

In this embodiment, as shown in FIG. 8, the scan electrode driving I located at the top of the panel is driven.
Discharge control timing signals SC and CLK input to C
The signal is applied before the scan pulse application time of the first scan electrode drive waveform of the panel. If you want to reduce the load on the scan electrode driving IC by 16 lines,
As shown in FIG. 8, the CLK signal is input earlier than the scan pulse application time × 16 times.

As a result, the output data for 16 lines is shifted inside the scan electrode driving IC, and the 17th output data is output from the 17th output terminal. From this point, the first scan electrode of the panel is output. To drive
Since the 16th output of the scan electrode driving IC on the panel upper part is set to the no-load state, the output of the scan electrode driving IC on the panel upper part is changed without changing the wiring and the configuration of the scan electrode group which follows. Since it is set to the no-load state, the load can be reduced.

As described above, the output timing control pulse of the discharge control timing signal SC and the CLK signal input to the scan electrode driving IC located at the top of the panel is supplied before the address discharge of the first scan electrode of the panel is started. By applying the voltage, a part of the output terminals of the scan electrode driving IC on the upper part of the panel (16 in the example of FIG. 8)
Is wired so as not to be connected to the scan electrodes of the panel, it is possible to reduce the load of the scan electrode driving IC located on the upper portion of the panel without adding a circuit.

[0053]

As is apparent from the above description, according to the plasma display device of the present invention, the load on the scan electrode driving IC on the panel upper portion where the ambient temperature is likely to rise due to the structure of the device is reduced. However, it is possible to suppress the amount of self-heating, which allows the scan electrode driving I
The effect that C can perform a stable operation is obtained.

[Brief description of drawings]

FIG. 1 is a perspective view showing a schematic configuration of a panel of a plasma display device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an electrode array of a panel of the plasma display device.

FIG. 3 is a block circuit diagram showing an example of a display drive circuit of the plasma display device.

FIG. 4 is a signal waveform diagram showing an example of a driving method of the plasma display device.

FIG. 5 is a schematic diagram showing a circuit configuration of a main part of a display drive circuit of the plasma display device.

FIG. 6 is a schematic diagram showing a circuit configuration of a main part of a display drive circuit according to another embodiment of the plasma display device.

FIG. 7 is an explanatory diagram showing a circuit configuration of a main part of a display drive circuit according to another embodiment of the plasma display device.

FIG. 8 is a waveform diagram for explaining an operation of a main circuit of a display driving circuit according to another embodiment of the plasma display device.

[Explanation of symbols]

1,5 substrate 2 Display electrode 7 Address electrode 20 panels 21,22,23,24 Scan electrode driving IC 25, 26, 27, 28 Control signal generation circuit 29, 30, 32, 33, 34 Resistance

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/66 101 G09G 3/28 EF term (reference) 5C058 AA11 BA03 BA35 5C080 AA05 BB05 DD26 FF12 HH04 HH06 JJ02 JJ03 JJ04 JJ06

Claims (5)

[Claims] 1. A plurality of scan electrodes arranged in a row direction of a panel on a pair of substrates forming a discharge space and facing each other, and a plurality of sustain electrodes arranged in parallel with the scan electrodes, A plasma display panel having a plurality of discharge cells is provided by providing a plurality of address electrodes arranged in the column direction of the panel so as to intersect the scan electrodes and the sustain electrodes, and the scan electrodes of the plasma display panel are The block is divided into a plurality of blocks with a predetermined number as one unit, and a plurality of scan electrode driving ICs for supplying a panel drive voltage waveform for performing address discharge and sustain discharge are connected to each block of the scan electrode. The scan electrode driving IC located on the upper side of the panel is for driving the scan electrode. A plasma display device characterized in that the number of output terminals connected to scan electrodes is smaller than the number of output terminals possessed by an IC. 2. A plurality of scan electrode driving ICs are connected to the scan electrodes by sequentially connecting all output terminals of the scan electrode driving ICs in order from the scan electrode driving ICs located on the lower side of the panel. The plasma display device according to claim 1, wherein the number of scan electrodes connected to the scan electrode driving IC located on the upper side is smaller. 3. A plurality of scan electrodes arranged in the row direction of the panel, and a plurality of sustain electrodes arranged in parallel with the scan electrodes on a pair of substrates facing each other forming a discharge space. A plasma display panel having a plurality of discharge cells is provided by providing a plurality of address electrodes arranged in the column direction of the panel so as to intersect the scan electrodes and the sustain electrodes, and the scan electrodes of the plasma display panel are The block is divided into a plurality of blocks with a predetermined number as one unit, and a plurality of scan electrode driving ICs for supplying a panel drive voltage waveform for performing address discharge and sustain discharge are connected to each block of the scan electrode. Output timing control for inputting to the scan electrode driving IC located at the top of the panel. A plasma display device configured to apply a control pulse before the address discharge of the first scan electrode of the panel starts. 4. A plurality of scan electrodes arranged in the row direction of the panel, and a plurality of sustain electrodes arranged in parallel with the scan electrodes, on a pair of substrates facing each other forming a discharge space. A plasma display panel having a plurality of discharge cells is provided by providing a plurality of address electrodes arranged in the column direction of the panel so as to intersect the scan electrodes and the sustain electrodes, and the scan electrodes of the plasma display panel are The block is divided into a plurality of blocks with a predetermined number as one unit, and a plurality of scan electrode driving ICs for supplying a panel drive voltage waveform for performing address discharge and sustain discharge are connected to each block of the scan electrode. And the panel drive voltage wave output from the scan electrode drive IC located on the upper side of the panel A plasma display device in which one of the shapes is amplitude-converted by a resistance and used as a control signal for the next scan electrode driving IC. 5. The plasma display device according to claim 4, wherein one of the panel driving voltage waveforms output by the scan electrode driving IC located on the upper side of the panel is amplitude and polarity converted by a resistor. .