KR100492952B1 - Scanning Electrode Control for Driving High Resolution AC PD - Google Patents

Abstract

The present invention provides a scan for driving a high-resolution AC PDP capable of changing the structure of the controller for efficiently controlling the number of scan electrodes of the panel as the resolution of the panel increases and the scanning scheme for improving the image quality. It relates to an electrode controller.

In the present invention, the scan electrode driver address ROM for generating information for selecting a control block in a temporal order according to the address generated by the ROM address counter and the information generated from the scan electrode driver address ROM correspondingly are scanned accordingly. and a shift register to sequentially output a control bit (Log ₂ n) for controlling the electrode, decodes the control bits (Log ₂ n) output sequentially from the shift register decoder for generating a control block selection signal (block Enable) And a control block for controlling group scan electrodes grouped by a predetermined number of scan electrodes of the PDP panel in units of blocks according to a control block selection signal generated by the decoder, a control clock and an initialization signal for driving the control block. .

Description

Scanning Electrode Control for Driving High Resolution AC PD

The present invention relates to a structure of a driving circuit of a plasma display panel (PDP), which is one of flat panel displays. In particular, the number of scan electrodes of a panel increases efficiently as the resolution of the panel is improved. The present invention relates to a scan electrode controller for driving a high resolution AC PDP capable of changing the structure of a controller for controlling and a scanning method for improving image quality.

In general, a plasma display device (hereinafter, abbreviated as PDP) causes discharge through voltage regulation applied between vertical and horizontal electrodes of a cell constituting a pixel, and the amount of discharged light is discharged in the cell. Adjust by varying the length of time.

The entire screen includes a write pulse for inputting a digital image signal to the vertical and horizontal electrodes of each cell, a scan pulse for scanning, a sustain pulse for maintaining a discharge, and a discharge pulse. It is obtained by driving a matrix type by applying an erase pulse for stopping the discharge of the cell.

On the other hand, the gray level required for displaying an image is different from the length of time each cell is discharged within a given time (1/30 second for an NTSC TV signal) required to display an entire image. Implement

At this time, the brightness of the screen is determined by the brightness when each cell is driven to the maximum, and in order to increase the brightness, the discharge time of the cell can be maintained as long as possible within a given time for constructing one screen The drive circuit must be designed.

The contrast, which is a difference in contrast, is determined by the gradation and luminance of the background of the lamp, and in order to increase the gradation, the background needs to be darkened as well as the luminance is increased.

In the case of a flat panel display for high-definition television (HDTV), 256 gray levels are required, the resolution must be 1280 x 1024 or more, and the gray level is required to be 100: 1 or more under 200 lux illumination.

Therefore, an image digital signal necessary for displaying 256 gray levels requires 8-bit signals each of RGB, and the discharge time of the cell must be kept as long as possible in order to obtain required luminance and gradation.

Gray level implementations include line scanning and subfield scanning. Currently, the most compatible method in the AC plasma display panel (PDP) is the sub-screen scanning method.

The sub-screen scanning method collects 8-bit digital video signals from the MSB to the LSB in the same weight bits, and then, during the time T _A , the MSB is the lower bits in order of T _A / 2, T _A / 4, ..., T _A / 128 is scanned to configure the sub picture, and 256 gray levels are realized by using the integral effect of the eye on the light emitted from each sub picture.

However, the PDP has to be driven in a matrix manner, and therefore, there is a limitation in that a write pulse cannot be applied to one or more horizontal electrodes at a time for a given vertical electrode, which causes the horizontal electrodes to be driven at different times. Should be

Therefore, in order to compose each sub-screen, it is necessary to scan all the horizontal electrodes, and each cell can maintain the discharge only for a time reduced by the scanning time from the time allocated to the average sub-screen.

On the other hand, the time required for scanning increases as the number of horizontal electrodes increases, and during this time, discharge cannot be maintained, which causes a decrease in luminance and contrast of the PDP. You need to reduce it.

 In addition, since the difference in discharge time between the upper bits and the lower bits is large and the secondary screen is sequentially configured in the sub-screen configuration, flicker occurs due to the difference in the discharge time.

In order to reduce the flicker, it is necessary to configure an upper bit screen with a long discharge time and a lower bit screen with a short discharge time in an appropriate order.

1 is a top structure and a bottom structure of a typical three-electrode discharge AC PDP substrate, the upper structure of the upper substrate 1, the sustain electrode (3) formed on the upper substrate 1, and the electrode discharge The dielectric layer 5 and the protective layer 6 for maintaining the surface charge generated in the lower structure, the lower structure is the lower substrate 2, and the address electrode 4 formed on the lower substrate 2 is It is formed in a direction perpendicular to the sustain electrode (3), the partition wall 7 is formed in parallel with the address electrode 4 between the lower substrate 2, the phosphor 8 is coated on the surface of the partition wall 7 To configure.

In the case of an AC PDP having such an electrode structure, an AC voltage whose polarity is continuously reversed must be applied between electrodes in order to maintain discharge.

The protective layer 6 is covered by the dielectric 5, which not only protects the dielectric 5 and extends its life, but also increases the emission efficiency of secondary electrons and is caused by oxide contamination of the refractory metal. MgO thin film is mainly used to reduce the change of discharge characteristics.

Since the phosphor 8 is coated on the dielectric 5, it is excited by the ultraviolet rays generated by the discharge to generate red, green, and blue (RGB) visible light.

The discharge region (not shown) is a space of a cell in which discharge proceeds, and is mainly filled with a mixture of Ar and Xe gas in order to increase ultraviolet emission efficiency.

FIG. 2 illustrates the electrode arrangement diagram of FIG. 1. As shown therein, each cell 9 is configured at a point where the row electrodes and the column electrodes cross at right angles to each other, and the row electrodes are mainly used for scanning the screen. It consists of the S1 to Sm scan electrode group used and the (C1 to Cm) common electrode group mainly used to maintain the discharge. The column electrodes are mainly used for data input, and the sealing part 12 maintains the vacuum of the entire PDP. Used for

3 illustrates driving waveforms and sub-screen scanning schemes of the electrodes in FIGS. 3 and 4.

First, a sustain pulse is applied to the C1 to Cm common electrodes to maintain the discharge of the cell, and a sustain pulse having the same shape but different positions as the pulses of the C1 to Cm common electrodes is applied to the S1 to Sm scan electrodes. Apply.

In addition, scan pulses used for scanning the screen and erase pulses for stopping the discharge of the discharged cells are additionally input to each of the S1 to Sm scan electrodes to control the blinking of the cells. .

Meanwhile, write pulses are obtained by inputting data pulses synchronized with scan pulses input to the scan electrodes to the column electrodes D1 to Dn.

If the cells S1 and D1 are to be discharged, when a positive data pulse is input to D1 and a scan pulse is input to S1 in synchronization with the data pulse, the voltage between the S1 and D1 electrodes causes a discharge. The discharge is generated by exceeding the required threshold voltage.

This state is maintained until the next erase pulse is applied by the electric field generated by the charged particles charged to the insulating film by the discharge and the electric field generated by the sustain pulses of S1 and C1, the erase pulse having a lower amplitude than the scan pulse. When is applied, a small discharge occurs that is insufficient for the sum of the electric field by the charged particles and the electric field by the erasing pulse to sustain the discharge, and the discharge disappears when the next sustain pulse is applied.

To summarize the roles of the electrodes described above, the scan electrodes serve as sustain and screen scan, while the common electrodes perform only the sustain function, and the data electrodes serve as data input for the screen configuration.

FIG. 4 illustrates a conventional sub-screen scanning method for implementing 256 gray levels based on the driving waveform of FIG. 3.

One screen consists of eight sub-screens, and the scan electrodes of the panel are arranged in order from the first scan electrode to the last scan electrode (mth scan electrode) in order of the horizontal axis, and also from MSB to LSB. Data is inputted from the data electrode for each selected scan electrode while being selected as (the logical value of the selected scan electrode is “0” and has a value of “1” when not selected).

A writing pulse is applied to the selected scan electrode on the left diagonal line of each sub-screen, and an erasing pulse is applied on the right diagonal line.

Here, since two or more writing pulses cannot be applied to one pixel at the same time, the time of each sub screen is constant as T.

On the other hand, a sustain pulse is regularly applied to the common electrode separately from the waveform applied to the scan electrode as shown in FIGS. 2 and 3.

However, in order to control the S1 to Sm scan electrodes, [log ₂ m] control bits are required, and the number of controller output pins is given by m.

Therefore, as the resolution increases, the complexity of the control circuitry and the number of output pins increase linearly. In the case of high resolution PDPs, the bus width is a problem.

This difficulty has a problem that becomes larger as the shape of the signal for the control of the scan active is diversified.

5 is a structure of a general scan electrode controller for driving the conventional sub-screen scanning method of FIG.

When a writing pulse is applied, a decoder (or multiplexer) structure having a size of [log ₂ m] -to-m is selected to select only one scan electrode among m scan electrodes. The logic value of the decoder output terminal is "0" and the remaining unselected output terminals have a logic value of "1".)

However, if the scan electrodes are sequentially controlled from the first to m th as shown in the sub-screen scanning shown in FIG. 4, the initial signal “0” is obtained by using a general shift register structure as shown in FIG. 6. After scanning, the scan electrodes may be sequentially selected by controlling with a shifting clock.

Here, the BLK (Blank) signal terminal asserts all outputs to "1" when the logic value is asserted to "1" so that no scan electrode is selected.

Accordingly, the present invention provides a method for driving a high-resolution AC PDP capable of changing the structure of the controller for efficiently controlling the number of scan electrodes of the panel as the resolution of the panel increases and the scanning method for improving the image quality. Its purpose is to provide a scan electrode control device.

In order to achieve the above object, the present invention provides a scan electrode driver address ROM for generating information for selecting a control block in a temporal order according to an address generated by a ROM address counter, and a scan electrode driver address ROM generated from the scan electrode driver address ROM. A shift block for sequentially outputting control bits (Log ₂ n) for controlling the scan electrode corresponding to the information, and a control block selection signal (Decoding the control bits (Log ₂ n) sequentially output from the shift register) A block for generating a block enable, a group scan electrode grouping a predetermined number of scan electrodes of a PDP panel according to a control block selection signal generated by the decoder, a control clock and an initialization signal for driving the control block. It consists of a control block controlled by.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

 First, in the present invention, as shown in FIG. 5, the scan active is individually controlled in the center, or as shown in FIG. 6, in the form of locally controlling all the scan electrodes using a shift register. The purpose of the present invention is to propose a structure of a high speed controller capable of efficiently controlling a scan electrode of a high resolution AC PDP.

FIG. 7 is a block diagram of a circuit for controlling scan electrodes in groups by improving the general scan electrode controller of FIG. 5 into a two-stage structure.

As shown therein, a scan electrode driver address ROM 102 generating information for selecting a control block in a temporal order according to an address generated by the ROM address counter 101 and the scan electrode driver address ROM 102. The shift register 103 sequentially outputs a control bit (Log ₂ n) for controlling the scan electrode corresponding to the information generated from the subfield, and the control bits (Log) sequentially output from the shift register 103. ₂ n) for decoding the control convex selection signal (Block Enable), the generated _{[Log 2 n-to-n} ] decoder 104, the _{[Log 2 n-to-n} ] the control occurs in the decoder 104 And a control block 105 for controlling group scan electrodes grouped by a predetermined number of scan electrodes of the PDP panel in block units according to a block selection signal and a control clock and an initialization signal for driving the control block. The.

In the above, the control block 105 is composed of a plurality of control blocks (105-1 to 105-n) for dividing the scan electrodes of the PDP panel into n equal parts, and for controlling the respective grouped scan electrodes. .

The operation and effects of the present invention configured as described above will be described with reference to FIGS. 7 to 14 as follows.

First, the proposed structure divides the S ₁ to S _M scan electrodes into n equal parts to make each of the divided m / n positive poles into a group, and then the plurality of control blocks 105-1 to 105-in the control block 105. n) have each take charge.

This requires [Log ₂ n] to control only the plurality of control blocks 105-1 to 105-n to control the number of bits needed to control the scan electrodes, so that the number of control bits to control the total m scan electrodes [Log ₂ m]-[Log ₂ n] is reduced.

In addition, since the number of output terminals driven by the [Log ₂ n-to-n] decoder 104 (number of scan electrodes) is reduced from m to n, the internal structure of the corresponding decoder circuit is simplified, and the resolution is increased. Even if the number of scan electrodes is increased, the number of driving output terminals of the [Log ₂ n-to-n] decoder 104 does not increase, so that high speed control is possible.

On the other hand, since the plurality of control blocks 105-1 to 105-n in the control block 105 all operate in common, the operation outline of the initial control block is shown in FIG.

First, when an initial signal for selecting a scan electrode is input (logical value: " 0 "), the plurality of control blocks 105-1 to 105-n synchronize with an externally applied clock. To shift the input value one by one to the next output terminal.

The scan electrode connected to the output terminal having the shifted “0” value receives data from the column electrodes D ₁ to D _n (writing of the data pulse of FIG. 3 and the left diagonal line of FIG. 4). See pulse section)

As an example, when the disable (logical value: "0") signal is input to the enable terminal of an arbitrary control block, the output of all output ports in the control block is "high", which is the corresponding control block. It means that no scan electrode has been selected among the m / n scan electrodes in the circuit.

In other words, since a common initial signal and an external clock are applied to each of the plurality of control blocks 105-1 to 105-n, n scan electrodes are simultaneously selected during one period of the clock. [Log ₂ n] According to the result of log ₂ n control bit input at the decoder 104, one control block at a time is enabled (logical value: "1") signal only at the enable input terminal and the rest (n- 1) control blocks are disabled (logical value: " 0 ") so that only one scan electrode is selected from the n scan electrodes.

In addition, by implementing the information for selecting the control block in a chronological order in accordance with the scanning method in a ROM, it is possible to change the scanning order without changing the circuit by only changing the program of the ROM RM.

FIG. 9 illustrates an example of the sub-screen scanning method of FIG. 4 using the scan electrode block control structure of FIG. 7.

A plurality of control blocks 105-1 to 105-n are sequentially enabled and disabled to select scan electrodes one by one from S ₁ to S _M.

Here, an initial signal is newly input every m / n cycles of the clock.

FIG. 10 illustrates the [Log ₂ n-to-n] decoder 104 in the control block 204 of the plurality of control blocks 204-1 to 204 to simplify external bus line connection in the scan electrode block control structure of FIG. -n) is a structural diagram embedded in the figure, which shows a control device having an improved structure of the scan electrode controller, wherein the scan electrodes generate information for selecting control blocks in a temporal order according to the address generated by the ROM address counter 201. A shift register 203 for sequentially outputting a driver address ROM 202 and a control signal Log ₂ n for controlling the scan electrode according to the information generated from the scan electrode driver address ROM 203; And a control clock and initialization for driving the block, the control signal Log ₂ n sequentially output from the shift register 203, a block selection signal input externally, and the control. It consists of a control block 204 for grouping the scan electrodes of the PDP panel in a predetermined number according to the signal and controlling the scan electrodes in block units.

In the above, the control block 204 is composed of a plurality of control blocks 204-1 to 204-n which divide the scan electrodes of the PDP panel into n equal parts and control the respective grouped scan electrodes.

In addition, the plurality of control blocks 204-1 to 204-n in the control block 204 are commonly enabled according to the control block enable signal output from the shift register 203 to the previously stored block selection control signal. A programmable selection block 204a for generating a shifting control enable signal according to a control signal Log ₂ n sequentially output from the shift register 203 and a block selection signal input from the outside; and the programmable selection block And an m / n output shifting control block 204b for sequentially selecting scan electrodes in accordance with the shifting control block enable signal generated at 204a.

In this configuration, since only [Log ₂ n] control signals can be applied to all the control blocks 204-1 to 204-n externally, the output n signal lines of the decoder 104 of FIG. 7 can be eliminated. have.

Here, the control block is largely divided into a conventional shifting block (control block portion of FIG. 6) and a block for programming each block selection control.

After the control block enable signal is asserted among the plurality of control blocks 204-1 to 204-n, the Log ₂ n control bits and the block selection signal are matched. Only if that block is selected.

The block select signal is preprogrammed for each control block 204-1 to 204-n with values of logic "0" or "1" in the circuit.

11 shows a scanning scheme for high resolution AC PDP. Here, the vertical axis represents the S ₁ to S _M scan electrodes, and the horizontal axis represents the scanning method with time.

Unlike the conventional sub-screen scanning method of FIG. 4, since the scan electrodes are not sequentially selected from the first to the last, the drive waveforms have the control bit number [see FIG. 5]. The control circuit structure is also complicated because it requires log ₂ m] and control all m output terminals.

If the structure of the scan electrode block controller shown in FIG. 7 is applied to this, first, eight control blocks are in charge of each of the eight sub blocks in the scanning blocks 1 and 2, and then, in accordance with the temporal order by the scanning method. -8-Eight control blocks can be enabled and disabled at the output of the decoder.

Therefore, the number of control bits required for this is 4 bits (3 decoder control bits, 1 bit for enabling the decoder), and the next scan electrode is selected according to an externally applied clock within each control.

FIG. 12 briefly illustrates a data map of a ROM having control block selection information according to a temporal order required when driving FIG. 11 using the scan electrode block controller structure.

FIG. 13 is a slightly modified scanning method for the high resolution AC PDP of FIG.

Here, Scanning block 1 and Scanning block 2 have the same scan electrode selection order.

In this case, the above-described scanning controller structure of FIG. 11 may be applied as it is, but using the controller structure of FIG. 14 may reduce the output bus width of the decoder.

In FIG. 14, a plurality of control blocks 306a to 306d and 306e to 306h are disposed in place of four sub blocks of Scanning block 1 and Scanning block 2 in FIG.

Similarly to the scanning controller structure of FIG. 11, two Scanning Blocks 1 and a plurality of control blocks 306a to 306h are selected one by one using a 2-to-4 decoder 304 and then connected together.

This is because four sub blocks of Scanning Block 1 have the same selection order.

However, since two control blocks cannot be selected at the same time, one control block is selected by alternately asserting a control signal 1 and a control signal 2 for control thereof.

If the number of blocks having the same selection order in the scanning method is large, as in the case of FIG. 13, depending on the scanning method, the control bus width required for selecting each control block externally can be reduced by using the controller structure of FIG. 14.

As described above, the present invention is a structure in which a block unit multiple body is controlled by grouping finite number of scan electrodes into one block, as compared to the conventional method of simply driving and controlling all scan electrodes individually, thereby driving all scan electrodes of the panel. As a result, the number of control bits required is reduced, so that the structure of the controller is simplified, and therefore, there is an effect of controlling the scan electrode at high speed.

In addition, by storing information on the temporal order of selecting the scan electrodes in a ROM or implementing programmable logic arrays (PLAs) according to the scanning method, one identical driving is performed without changing the structure of the driving circuit according to each scanning method. The circuit alone has the effect of implementing various scanning methods.

1 is a top structure and a bottom structure diagram of a typical three-electrode surface discharge AC PDP substrate.

2 is a layout view of the electrode of FIG. 1.

3 is a drive waveform diagram using an electrode arrangement of a typical three-electrode surface discharge AC PDP.

4 is a scanning method of a conventional sub-screen driving method for implementing 256 gray level.

5 is a schematic structural scan electrode controller.

6 is a structural diagram of a scan electrode controller using a shift register of a general type;

7 is a block diagram of a scan electrode control apparatus for driving a high resolution AC PDP according to the present invention;

8 is a schematic operation diagram of the control block of FIG. 6;

FIG. 9 is a structural diagram of scanning electrode block control of the sub screen scanning method of FIG. 4; FIG.

FIG. 10 is a controller structure diagram of an improved control structure of the scan electrode block of FIG. 6.

        (A) is a block diagram of another embodiment of a scan electrode control apparatus for driving a high resolution AC PDP according to the present invention.

        (B) is a detailed block diagram of the control block applied to (a).

11 is a scanning scheme for high resolution AC PDP.

FIG. 12 is a data map of a ROM required when FIG. 11 is scanned in the scan electrode block. FIG.

13 is a slightly modified scanning method for the high resolution AC PDP of FIG.

14 is a controller structure diagram suitable for the scanning method of FIG.

*** Explanation of symbols for the main parts of the drawing ***

101: ROM address counter 102: Scan electrode driver address ROM

103: shift register 104: [Log ₂ n-to-n] decoder

105: control block

Claims (10)

A scan electrode driver address ROM 102 for generating information for selecting a control block in a temporal order according to the address generated by the ROM address counter 101 and information generated from the scan electrode driver address ROM 102; Decode the shift register 103 for sequentially outputting the control bit (Log ₂ n) for controlling the scan electrode and the control bit (Log ₂ n) sequentially output from the shift register 103 The decoder 104 generates a control block selection signal (Block Enable), scan electrodes of the PDP panel according to the control block selection signal generated by the decoder 104 and a control clock and an initialization signal for driving the control block. For driving a high resolution AC PDP, comprising a control convex 105 for controlling group scan electrodes grouped by a predetermined number in blocks. Scanning electrode control. The method of claim 1, The control block 105 comprises a plurality of control blocks 105-1 to 105-n for dividing the scan electrodes of the PDP panel into n equal parts, and for controlling the respective grouped scan electrodes. Scanning electrode controller for driving resolution AC PDP. Information generated from the scan electrode driver address ROM 202 for generating information for selecting a control block in a temporal order according to the address generated by the ROM address counter 201, and information generated from the scan electrode driver address ROM 203; a corresponding to a scan electrode control signal (Log ₂ n) for controlling the shift register 203, a control signal (Log ₂ n) output from the shift register 203 in order to sequentially output it as externally A control block 204 for controlling group scan electrodes grouped by a predetermined number of scan electrodes of a PDP panel in block units according to an input block selection signal and a control clock and an initialization signal for driving the control convex. Scan electrode control device for driving a high resolution AC PDP, characterized in that consisting of. The method of claim 3, wherein The control block 204 is composed of a plurality of control blocks (204-1 to 204-n) for dividing the scan electrodes of the PDP panel into n equal parts, and for controlling the respective grouped scan electrodes. Scanning electrode controller for driving resolution AC PDP. The method of claim 3, wherein The plurality of control blocks 204-1 to 204-n in the control block 204 are commonly enabled according to a control block enable signal output from the shift register 203 and are stored by a pre-stored block selection control signal. A programmable selection block 204a for generating a shifting control enable signal according to a control signal Log ₂ n sequentially output from the shift register 203 and a block selection signal input from the outside; And a m / n output shifting control block (204b) that sequentially selects the scan electrodes according to the shifting control block enable signal generated at 204a). A scan electrode driver address ROM 102 for generating information for selecting a control block in a temporal order according to the address generated by the ROM address counter 101 and information generated from the scan electrode driver address ROM 102; Decode the shift register 103 for sequentially outputting the control bit (Log ₂ n) for controlling the scan electrode and the control bit (Log ₂ n) sequentially output from the shift register 103 A decoder 104 outputting a block selection signal and a block selection signal generated by the decoder 104 are logically operated with a control signal (Control Signal 1,2) input from an external source. A logic operation unit 305 for generating a block selection signal, a control clock for driving a control block and a control block selection signal output logically operated by the logic operation unit 305, and A scan for driving a high resolution AC PDP, comprising a control block 306 for controlling a group scan electrode grouped by a predetermined number of scan electrodes of the PDP panel 307 in block units according to vaporization value (Initial). Electrode controller. The method of claim 6, And the decoder (304) outputs control bits sequentially output from the shift register (303) as 4 bits for block selection. The method of claim 6, The control block 306 is composed of a plurality of control blocks (306-1 to 204-8) for dividing the scan electrodes of the PDP panel into n equal parts, and for controlling the respective grouped scan electrodes. Scanning electrode controller for driving resolution AC PDP. The method of claim 6, The logic operation unit 305 may be configured to generate a control block selection signal by combining the block selection signal generated by the decoder 304 with the first control signal Control Signal 1 input to the other side. 4th AND gate 305a to 305d and a block selection signal generated by the decoder 104 to block-select the second control signal (Control Signal 2) input to the other side to generate a control block selection signal; A scan electrode control apparatus for driving a high resolution AC PDP, comprising: 5 to 8th end gates (305e to 305h). The method according to claim 1 or 3, According to the scanning method, a signal required to select a scan electrode group in a temporal order is selected among a ROM, a PLA, and a random logic, and implemented in the form of a FSM. Scanning electrode controller for driving high resolution AC PDP clamps.

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