JPH1165517A - Drive method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve gradation linearity by counting all numbers of times of discharging emission as the discharge for multilevel display, except the resetting discharge of performing a whole surface simultaneously. SOLUTION: A waveform 10 is a part of driving waveforms applied on an X-electrode in a first to third subfields, waveforms 11, 12 are parts of driving waveforms applied on, e.g., a first and second Y1, Y2 of Y electrode and a waveform 13 is a part of driving waveforms applied on one of address electrodes. A waveform 14 shows the timing of discharge. In this case, a selecting reset pulse is set to be a higher voltage than a discharge start voltage. By counting the number of times of discharges except a write discharge 60 and an erasure discharge 61 in all cells in the first subfield as the multilevel display of a selected cell in each subfield and making them multiples of a factorial of two, a linear luminance change from a zeroth level, i.e., a black level to 255th level is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to display devices such as personal computers and workstations,
The present invention relates to a driving method of a plasma display panel used for a flat-type wall-mounted television, a display device for advertising, information, and the like.

[0002]

2. Description of the Related Art In a plasma display device, one field (one screen) is divided into a plurality of subfields on a time axis for each luminance, and ultraviolet light is generated by discharge for each pixel (cell) to generate a phosphor. It is excited and emits light.
This discharge is called a sustain discharge.
As disclosed in Japanese Patent No. 5188, halftone display is performed by changing the number of discharges for each subfield. In addition, at the beginning of each subfield, if a sustain discharge is performed in the immediately preceding subfield, writing and erasing discharges are performed over the entire surface to erase charged particles accumulated in the discharge region (cell). Is performed. The light emission due to this discharge occurs in all cells regardless of the presence or absence of a light emission signal, so that the brightness of the black level increases and the contrast deteriorates.

On the other hand, for example, Japanese Patent Application Laid-Open No. 8-278
As disclosed in Japanese Patent Application Publication No. 766, since the operation of eliminating charged particles (wall charges) is performed only in the cell in which the sustain discharge has been performed in the immediately preceding subfield, only the cell in which the sustain discharge has been performed is selectively written. Discharge and self-erasing discharge,
The contrast is prevented from deteriorating. In these cases, light emission by an address discharge for defining a cell to emit light or light emission by a write discharge and a self-erase discharge selectively performed only in a cell in which a sustain discharge has been performed can be used for low gradation display. No particular consideration was given to the fact that the luminance of the subfield was too bright relative to the black level.

[0004]

As described above, in the prior art, light emission due to writing and erasing discharges or address discharges has not been sufficiently considered for gradation display. In particular, no consideration has been given to the non-linearity of the luminance of the first gradation from the black level.

An object of the present invention is to provide a driving method of a plasma display panel which solves such a problem and improves the linearity of gradation.

[0006]

In order to achieve the above object, the present invention does not care whether writing, erasing, addressing, or sustaining discharge is performed for one gradation, and the number of discharges is two or more. It is prescribed. Furthermore, in the case where one gradation is discharged twice,
In the subfield displaying the lowest gradation, there is no sustain discharge after the address discharge, and a discharge for erasing the charge in the cell is performed by one discharge. In the subsequent subfield, writing and erasing are performed. This is to connect to address discharge without performing discharge.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is an exploded perspective view showing a part of the structure of a plasma display panel to which the driving method according to the present invention is applied.

In FIG. 1, a transparent X electrode 22 and a transparent Y electrode 23 are provided on the lower surface of a front glass substrate 21. Further, an X bus electrode 24 and a Y bus electrode 25 are stacked on the respective electrodes 22 and 23. Further, a dielectric layer 26 and a protective layer 27 such as MgO are provided on the lower surface.

On the other hand, an address A electrode 29 is provided on the upper surface of the rear glass substrate 28 in a direction perpendicular to the X electrodes 22 and the Y electrodes 23 of the front glass substrate 21. The address A electrode 29 is covered with a dielectric 30, and a partition 31 is provided thereon in parallel with the address A electrode 29.
Furthermore, the dielectric 30 on the partition 31 and the address A electrode 29
Is coated with a phosphor 32.

FIG. 3 is a sectional view showing one cell portion of the plasma display panel viewed from the direction of arrow A in FIG.

In FIG. 1, the address A electrode 29 is located at the middle of the partition wall 31. The space 33 between the front glass substrate 21 and the back glass substrate 28 has N
e, Xe or the like is filled with a discharge gas.

FIG. 4 is a sectional view showing three cell portions of the plasma display panel viewed from the direction of arrow B in FIG.

In FIG. 1, the boundary of one cell is a position indicated by a substantially dotted line, and X electrodes 22 and Y electrodes 23 are alternately arranged. In the AC type plasma display panel, positive and negative charges are separately collected on the dielectric near the X electrode 22 and the Y electrode 23, and an electric field for discharging by using the charges is formed. .

FIG. 5 is a schematic diagram showing the wiring and circuit configuration of the X electrode 22, Y electrode 23 and address A electrode 29 described above.

In FIG. 1, an X drive circuit 34 generates a drive pulse applied to the X electrode 22. Y drive circuit 35
Is connected to each of the Y electrodes 23 and generates a drive pulse applied to the Y electrodes 23. The A drive circuit 36 is connected to each of the address A electrodes 29,
9 is generated.

Next, a first embodiment of a method for driving a plasma display panel according to the present invention will be described.

FIG. 6 is a diagram showing a field configuration in the first embodiment. Note that in this embodiment, one gradation is a luminance due to two discharges. In the figure, 40
Represents one field period, the horizontal axis represents time t (one field period), and the vertical axis represents cell row y.

In FIG. 6, here, one field is divided into eight subfields 41 to 48, that is, a first subfield 41, and a first subfield 41 is assigned as a subfield having the least number of discharges. The subfields are arranged in ascending order of the number of discharges.

In the first sub-field 41, first, a first reset period 41a is provided in which writing is performed in all cells and discharge for erasing or reducing charged particles is performed. Is provided in the address period 41b. Further, following this, a selective erasing period 41c is provided for erasing the charge in the cell by one discharge only in the cell in which the charge is formed by the address discharge.

In the second subfield 42 following the first subfield 41, there is no discharge for writing and erasing or reducing charged particles, and an address period 42b for defining a cell to be displayed first is provided. . Subsequently to this, a sustain discharge period 42c is provided, but since the second sub-field 42 is the second sub-field from the one with the smaller number of discharges, one discharge is performed in the sustain discharge period 42c. .

Each of the other subfields 43 to 48
At first, second reset periods 43a to 48a are provided for selectively performing writing and discharging for reducing charged particles only in cells in which sustaining discharge has been performed in the immediately preceding subfield. Periods 43b to 48b and sustain discharge periods 43c to 48c are provided. In the sustain discharge periods 43c to 48c, the number of discharges is assigned to each of them.
Display halftone.

The number of discharges and the order of the subfields are arbitrary.

FIG. 1 shows the first to third embodiments according to the first embodiment.
5 is a time chart showing a part of the drive waveforms of the subfields 41 to 43 of the first embodiment. A waveform 10 is a part of the drive waveform applied to the X electrode 22 in the first to third subfields 41 to 43. , Waveforms 11 and 12 are part of the drive waveforms applied to the first and second rows (Y1, Y2) of the Y electrode 23, for example.
It is a part of the drive waveform applied to the book. The waveform 14
Indicates the discharge timing.

In FIG. 1, for example, a waveform 1 applied to the X electrode 22 in the first to third subfields 41 to 43 is shown.
0 is composed of a full reset pulse 50 in the first reset period 41a, an X scan pulse 51 in the address periods 41b and 42b, and a selective reset pulse 52 in the second reset period 43a of the third subfield. . At this time, the selection reset pulse 52 is set to a voltage higher than the discharge start voltage.

Next, for example, the adjacent one of the Y electrodes 23
Waveforms 11 applied to the second and the second rows (Y1, Y2),
12 includes a scan pulse 53a, 53b,... For the address periods 41b, 42b, a selective erase pulse 54 for the selective erase period 41c, and a first sustain discharge pulse 55 for the sustain discharge period 42c. The voltage of the selective erasing pulse 54 is substantially equal to that of the first sustain discharge pulse 55, and is set to the sustain voltage. Scan pulse 53a, 53
The voltages b,... are set so that the potential difference from the X scan pulse 51 falls within the sustain voltage range.

Next, the waveform 13 applied to one of the address A electrodes 29 includes the address pulse 56 of the address period 42b, 43b corresponding to the cell to emit light and the full-length pulse 57 corresponding to the first sustain discharge pulse 55. It consists of If there is no cell to emit light, there is no address pulse 56. Further, the entire surface pulse 57 and the address pulse 56 are set to substantially the same voltage.

The discharge by each pulse occurs at the timing shown by the waveform 14. That is, first, in the entire reset pulse 50 of the first subfield, the write discharge 60 is applied to all the cells at the rising and falling timings.
And an erasing discharge 61 is generated. In the subsequent address period 41b, the address discharge 62 is generated only in the cells to which the address pulse 56 has been applied to the scan pulses 53a, 53b,. Subsequent selective erase period 41c
In this case, the address discharge 62 causes the erasing discharge 63 by the selective erasing pulse 54 only in the cell where the charged particles are formed. Thereby, in the first subfield 41,
Two discharges occur in all cells and two more discharges occur in selected cells. The discharge in all these cells has a brightness of the black level, and the discharge in the selected cell has the brightness of the first gradation from the black level.

Subsequently, the second sub-field 42
In this case, the address discharge 64 occurs only in the cell selected in the address period 42b. Subsequently, the first discharge is performed only in the cell in which the charged particles are formed by the address discharge 62.
, A writing discharge 66 and an erasing discharge 67 are generated only in the selected cells even in the selection reset pulse 52 of the third subfield 43. As a result, the discharge in the cell selected in the second sub-field 42 is performed four times, and the second gradation is obtained.

FIG. 7 shows the third subfield 43 to the fourth subfield 43.
7 is a time chart showing a driving waveform at the beginning of the subfield 44, where a waveform 70 is a part of the driving waveform applied to the X electrode 22, and waveforms 71 and 72 are the Y electrode 23;
For example, the waveform 73 is a part of the drive waveform applied to the first and second rows (Y1, Y2), and the waveform 73 is a part of the drive waveform applied to one of the address A electrodes 29. Waveform 7
4 indicates the timing of the discharge. Note that the same drive pulses and discharges as those in FIG.

In FIG. 7, a waveform 70 applied to the X electrode 22 includes a selective reset pulse 52 in reset periods 43a and 44a, an X scan pulse 51 in an address period 43b, and a sustain discharge pulse 58 in a sustain discharge period 43c. Consists of The voltage of the sustain discharge pulse 58 is set substantially equal to the voltage of the first sustain discharge pulse 55.

Waveforms 71 and 72 applied to the Y electrode 23
Is the same as the waveform of the second subfield shown in FIG. 1 except that the sustain discharge pulse 59 is added. The waveform 73 applied to the address A electrode 29 is the same as the waveform of the second subfield shown in FIG.

In the sustain discharge period 43c, as shown by a waveform 74, one discharge occurs for each of the sustain discharge pulses 58 and 59. As described above, in the cell selected in the third subfield, sustain discharges 65, 68, and 69 by the address discharge 64, the first sustain discharge pulse 55 and the sustain discharge pulses 58 and 59, and the subsequent subfield selection A write discharge 66 and an erase discharge 67 of the selected cell are generated. In order to obtain four gradations of luminance in the third subfield, eight discharges are required. Therefore, the X and Y sustain discharge pulses 58 and 59 are two each. 4th ~
The same driving waveform is applied to the eighth subfields 44 to 48.

The number of gradations to be displayed in each subfield and the number of sustain discharge pulses 75 and 76 are as follows. That is, the fourth subfield has eight gradations and six sustain discharge pulses. The fifth subfield has 16 gradations and 14 sustain discharge pulses. The sixth subfield has 32 gradations and 30 sustain discharge pulses. The seventh subfield has 64 gradations and 62 sustain discharge pulses. The eighth sub-field has 128 gradations and 127 sustain discharge pulses each.

As described above, the number of sustain discharge pulses 75 and 76 in the third to seventh subfields is n bits (2 ⁿ
In the case of (gradation) display, the number is (2 ^(n-1) -2). That is, from the discharge for n gradations, the address discharge 64, the sustain discharge 65 by the first sustain discharge pulse 55, and the write discharge 66 and the erase discharge 67 of the selected cell in the subfield following the discharge are performed. Number of subtractions.

In the last eighth subfield 48, the writing discharge and the erasing discharge in the following subfields are not only in the selected cells but also in all the cells.
It is excluded from the discharge for gradation display, and the sustain discharge pulses 58 and 59 are increased by one correspondingly to (2 ^(n-1) -1).

As described above, write discharge 60 and erase discharge 61 in all cells in the first subfield.
In each sub-field are discharges counted as the gradation display of the selected cell in each sub-field, and by making them multiples of the factorial of 2, the 0th gradation, that is, the 255th floor from the black level It is possible to obtain a linear luminance change up to the tone.

In the first embodiment, the subfields are arranged in ascending order of the number of discharges. However, in the subfield following the subfield in which the selective erasing pulse 54 of the selective erasing period 41c is arranged after the address period, the reset period is In the subfield immediately before the full reset pulse 50, the number of sustain discharge pulses is set to (2 ⁽ⁿ⁻¹⁾ − in the case of n-bit (2 ⁿ gradation) display.
If 1), the arrangement of subfields is arbitrary. For example, when the subfield immediately before the full reset pulse 50 is the second from the lower order (n = 2), the number of sustain discharge pulses is one.

Next, a second embodiment of the method for driving a plasma display panel according to the present invention will be described with reference to FIGS.

FIG. 8 is a diagram showing a field configuration in the second embodiment, where 80 indicates one field period, the horizontal axis indicates time t (one field period), and the vertical axis indicates cell row y. Each is represented. Note that in this embodiment, one gradation is a luminance due to two discharges.

Referring to FIG. 8, in the second embodiment,
One field includes first to eighth eight sub-fields 81
The first sub-field 81 is assigned as the sub-field with the least number of discharges, and the sub-fields are arranged in the order of the least number of discharges.

The second sub-field following this first sub-field 81
In the subfield 82, a first reset period 82a in which writing for all cells and discharge for erasing or reducing charged particles are performed in all cells is provided. In each of the other subfields 81 and 83 to 88, first, only the cells in which the sustain discharge has been performed in the immediately preceding subfield initially perform the second reset periods 81a, 83a to 83c in which writing and discharging for reducing charged particles are selectively performed. 88a are provided. Subsequent to the first and second reset periods 81a to 88a, there are provided address periods 81b to 88b for defining cells to be displayed. Further, following this, a sustain discharge period 81c in which only cells in which charges are formed by the address discharge is discharged.
To 88c.

FIG. 9 shows the first to third embodiments in the second embodiment.
8 is a time chart showing a part of the drive waveforms of the subfields 81 to 83 of FIG.
To the third subfields 81 to 83 are part of the drive waveform applied to the X electrode 22, and the waveforms 91 and 92 are, for example, the first and second rows (Y 1 and Y 2) of the Y electrode 23. , And a waveform 93 is a part of the drive waveform applied to one of the address A electrodes 29.
The waveform 94 indicates the timing of the discharge.

In FIG. 9, for example, a waveform 9 applied to the X electrode 22 in the first to third subfields 81 to 83 is shown.
0 includes a selective reset pulse 52 in the second reset periods 81a and 83a, an X scan pulse 51 in the address periods 81b and 82b, and a full reset pulse 50 in the first reset period 82a of the second subfield. ing. At this time, the selection reset pulse 52 is set to a voltage higher than the discharge start voltage.

Next, for example, the adjacent one of the Y electrodes 23
Waveforms 91 applied to the second and third rows (Y1, Y2)
Reference numeral 92 denotes scan pulses 53a, 53b,... Of the address periods 81b, 82b, and sustain discharge periods 81c, 8 respectively.
2c of the first sustain discharge pulse 55. The voltages of the scan pulses 53a, 53b,... Are set so that the potential difference from the X scan pulse 51 falls within the sustain voltage range.

Next, the waveform 13 applied to one of the address A electrodes 29 includes the address pulse 56 of the address period 81b, 82b corresponding to the cell to emit light and the full-length pulse 57 corresponding to the first sustain discharge pulse 55. It consists of

When there is no cell to emit light, there is no address pulse 56. Further, the entire surface pulse 57 and the address pulse 56 are set to substantially the same voltage.

The discharge by each pulse occurs at the timing shown by the waveform 94. First, in the selective reset pulse 52 of the first subfield 81, the write discharge 66 and the erase discharge 67 are generated only in the cell in which the sustain discharge has been performed in the preceding subfield. Subsequent address period 8
In 1b, the address discharge 62 occurs only in the selected cell. Subsequently, the sustain discharge 65 by the first sustain discharge pulse 55 occurs only in the cell in which the charged particles are formed by the address discharge 62. As a result, two discharges occur in the cell selected in the first subfield 81, and the luminance of the first gradation from the black level is obtained.

Subsequently, in the entire reset pulse 50, a write discharge 60 and an erase discharge 61 are generated in all cells at the rising and falling timings. In the subsequent address period 82b, the scan pulses 53a, 5a
Address discharge 62 is generated only in the cells to which address pulse 56 is applied to 3b,. Subsequently, the sustain discharge 65 by the first sustain discharge pulse 55 occurs only in the cell in which the charged particles are formed by the address discharge 62.

Further, in the selective reset pulse 52 of the third subfield 83, the write discharge 66 and the erase discharge 67 are generated only in the cells where the sustain discharge has been performed in the preceding subfield. Thus, in the cell selected in the second sub-field 82, four discharges occur, and the luminance of the second gradation is obtained.

FIG. 10 is a time chart showing a driving waveform in the third subfield 83 according to the second embodiment. A waveform 100 is a part of the driving waveform applied to the X electrode 22. 101 and 102 are Y electrodes 23
For example, the waveform 103 is a part of the drive waveform applied to the first and second rows (Y1, Y2), and the waveform 103 is a part of the drive waveform applied to one of the address A electrodes 29. A waveform 104 indicates the timing of the discharge. Note that the same drive pulses and discharges as those in FIG. 9 are given the same numbers and description thereof is omitted.

In FIG. 10, a waveform 100 applied to the X electrode 22 includes a selection reset pulse 52 in a reset period 83a and an X scan pulse 51 in an address period 43b.
And a sustain discharge pulse 75 in the sustain discharge period 43c.

Here, the voltage of the sustain discharge pulse 75 is the first
And the waveforms 101 and 102 applied to the Y electrode 23 are the same as those in the first sub-field shown in FIG. 9 except that the sustain discharge pulse 76 is added. Same as the waveform. Address A
The waveform 103 applied to the electrode 29 is also the first waveform shown in FIG.
Is the same as the waveform of the subfield.

In the sustain discharge period 83c, one discharge occurs for each of the sustain discharge pulses 58 and 59, as shown by the waveform 104. As described above, in the selected cell in the third subfield, the address discharge 62, the first sustain discharge pulse 55, and the sustain discharge pulses 58 and 59 are provided.
, A write discharge 66 and an erase discharge 67 of the selected cell in the subfield subsequent thereto are generated. In order to obtain the luminance of the fourth gradation in the third subfield, eight discharges are required.
Therefore, the X and Y sustain discharge pulses 58 and 59 are 2
Individually.

The fourth to eighth subfields 84 to 88 have similar driving waveforms.

The number of gradations to be displayed in each subfield and the number of sustain discharge pulses 58 and 59 are as follows.

That is, the fourth subfield has eight gradations and six sustain discharge pulses. The fifth subfield has 16 gradations and 14 sustain discharge pulses. The sixth subfield has 32 gradations and 30 sustain discharge pulses. The seventh subfield has 64 gradations and 62 sustain discharge pulses. 8th
Are 128 gradations, and the sustain discharge pulse is 1 for each.
26 pieces.

As described above, the number of sustain discharge pulses 58 and 59 in the third to seventh subfields is n bits (2 ⁿ
In the case of (gradation) display, the number is (2 ^(n-1) -2). This is because, from the discharge of (2 ⁿ ) gradations, an address discharge 64, a sustain discharge 65 by the first sustain discharge pulse 55, and a write discharge 66 and an erase discharge 67 of the selected cell in the subfield subsequent thereto. Is the number of times subtracted.

As described above, write discharge 60 and erase discharge 61 in all cells in the second subfield.
In all sub-fields, discharges counted as gradation display of the selected cell in each sub-field can be a linear luminance change from the black level to 255 gradations.

In the second embodiment, the subfields are arranged in ascending order of the number of discharges. However, as is apparent from the above description, the entire reset pulse is applied after the subfield with the smallest number of discharges. By doing so, the arrangement order of the subfields is arbitrary.

As described above, all the discharges (address discharge, sustain discharge, and discharge by the selective reset pulse) except the discharge performed by the entire surface reset pulse at the same time for all cells are counted as the discharge for gradation display.
Linear gradation display can be performed.

[0062]

As described above, according to the present invention,
By counting all of the discharge light emission except the reset discharge that is performed simultaneously on the entire surface as a discharge for gradation display, a linear luminance change from the black level to 255 gradations can be obtained.

[Brief description of the drawings]

FIG. 1 is a time chart showing driving waveforms of first to third subfields in a first embodiment of a driving method of a plasma display panel according to the present invention.

FIG. 2 is an exploded perspective view showing a part of the structure of a plasma display panel to which the present invention is applied.

FIG. 3 is a cross-sectional view showing one cell portion of the plasma display panel as viewed from the direction of arrow A in FIG. 2;

FIG. 4 is a cross-sectional view showing three cell portions of the plasma display panel as viewed from the direction of arrow B in FIG. 2;

FIG. 5 is a schematic diagram showing electrode wiring and a circuit configuration in the plasma display panel shown in FIG. 2;

FIG. 6 is a schematic diagram showing a field configuration in the first embodiment shown in FIG.

FIG. 7 is a time chart showing driving waveforms from a third subfield to a fourth field shown in FIG. 1;

FIG. 8 is a schematic diagram showing a field configuration in a second embodiment of the driving method of the plasma display panel according to the present invention.

FIG. 9 is a time chart showing driving waveforms of first to third subfields in the second embodiment shown in FIG. 8;

FIG. 10 is a time chart showing a driving waveform of a third subfield in the second embodiment shown in FIG. 8;

[Explanation of symbols]

 10 to 13 drive waveform 21 front glass substrate 22 X electrode 23 Y electrode 28 rear glass substrate 29 address A electrode 31 partition 34 X drive circuit 35 Y drive circuit 36 A drive circuit 40 1 field 41 to 48 subfield 41a, 43a to 48a Reset period 41b-48b Address period 41c Select erase period 42c-48c Sustain discharge period 50 Full reset pulse 51 X scan pulse 52 Select reset pulse 53a, 53b Scan pulse 54 Select erase pulse 55 First sustain discharge pulse 56 Address pulse 58, 59 Sustain discharge pulse 60 Write discharge 61 Erase discharge 62 Address discharge 63 Selective erase discharge 65 to 67 Sustain discharge 80 1 field 81 to 88 Subfield Reset period 81a to 88a Reset period

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yuichiro Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliances and Information Media Business Division, Hitachi, Ltd. (292) Inventor: Shoji Ishigaki, Ltd.Household Electronics and Information Media Business Division, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture

Claims (3)

[Claims] A first glass substrate disposed on a front glass substrate;
Electrode group, a second electrode group disposed in parallel with the first electrode and capable of being driven independently, and a second electrode group disposed on the rear glass substrate and intersecting the first and second electrode groups at right angles. And a plurality of display cells having a third electrode group that can be driven independently and defined at intersections of the first and second electrode groups and the third electrode group. In the driving method of the plasma display panel, the writing and the charge erasing are simultaneously performed in the entire sub-field, and in the other sub-fields, only the cells discharged in the immediately preceding sub-field are selectively subjected to the writing and the erasing discharge. A method for driving a plasma display panel, wherein all discharges except for writing and charge erasing discharges are counted as discharges for gradation display. 2. The method of driving a plasma display panel according to claim 1, wherein a light-emitting cell is provided in a sub-field displaying the lowest gray scale, except for a writing and charge erasing discharge performed once and entirely simultaneously in one field. A driving method for a plasma display panel, comprising only an address discharge defining the following, and an erase discharge for erasing a charge formed by the address discharge by one discharge. 3. The method of driving a plasma display panel according to claim 1, wherein in a subfield displaying the lowest gradation, an address discharge defining a light emitting cell and a charge formed by the address discharge are used. In a subfield subsequent to the subfield displaying the lowest gray level, a discharge for writing and erasing charges is first performed simultaneously over the entire surface. Drive method.