JPH11259041A - Driving method of plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To let all cells satisfactorily execute reset discharge and address discharge by decreasing discharge current in all reset discharging. SOLUTION: According to order of an arrangement on a panel 1, X-electrodes Xo of odd number data are driven at the same time by a driving circuit 2, and X-electrodes Xe of even number data are also driven at the same time by a driving circuit 3. For a reset discharging period in each sub-field, the driving circuit 2 firstly impresses a reset pulse on the X-electrodes Xo of odd number data and forms wall charges on all the cells of odd number data line Lo, and then, sequentially drives Y-electrodes Yo of odd number data and address-discharges the cells to be maintenance-discharged. When the above- mentioned discharge ends about the line Lo of odd number data, the reset- and address-discharges are performed in the same way to the line Le of even number data consisting of X electrodes Xe of even number data and Y- electrodes Ye of even number data by the driving circuit 3. The maintenance discharge is performed to all the lines of the panel 1 simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display panel constituted by a set of display elements (cells) having a memory function, and more particularly, to an AC type plasma display panel (PDP), which has a high quality. The present invention relates to a driving method for enabling a simple image display.

[0002]

2. Description of the Related Art In a conventional AC type plasma display panel, as shown in Japanese Patent Application Laid-Open No. 6-186927, one field period is divided into two or more subfields, and each subfield is entirely written and erased. A discharge period, an address discharge period, and a sustain discharge period are set.

The sustain discharge period of each subfield is determined by, for example, the number of repetitions of the sustain discharge weighted as a ratio of 1: 2: 4: 8:...: 128 in binary code.
Each gradation is displayed by selecting and combining these light emission times within one field period.

Further, during the entire writing and erasing discharge periods of each subfield, all the writing and erasing discharges are performed on all the cells to make the wall charge uniform, and during the address discharging period, the cells are maintained in that subfield. An address discharge is performed only in a cell to be discharged (selected cell) to store a positive charge near the Y electrode, and a sustain discharge is performed using the charge. In the sustain discharge period, the X electrode and the Y electrode
Sustain discharge pulses of the same voltage are applied to the electrodes at regular intervals alternately in time. A set of sustain discharge pulses for one X electrode and one Y electrode is applied to each electrode repeatedly according to the weight of each subfield.

[0005] The above-mentioned full writing and erasing discharge periods are as follows.
This period is simply referred to as “all reset period” because the wall charge amount in all cells is uniformly reset.
In this period, all writing and erasing discharges in this period are referred to as “all reset”.

When the application of the last sustain discharge pulse in the sustain discharge period is completed, all resets are performed in the next subfield, and the next subfield is repeated following the address discharge period and the sustain discharge period.

FIG. 3 is a perspective view showing a part of the structure of an AC plasma display panel, wherein 1 is an AC plasma display panel (hereinafter simply referred to as a panel),
Is a front glass substrate, 5a is an X transparent electrode, 5b is an X bus electrode, 6a is a Y transparent electrode, 6b is a Y bus electrode, 7 is a protective film, 8a and 8b are dielectric layers, 9 is a partition, 10R and 10
G and 10B are phosphors, 11 is an address electrode, 12 is a rear glass substrate, and 13 is a discharge space. The X transparent electrode 5a and the X bus electrode are collectively referred to as an X electrode 5, and the Y transparent electrode 6a and the Y bus electrode 6b are collectively referred to as a Y electrode 6.

In FIG. 1, a plurality of address electrodes 11 are arranged on a back glass substrate 12 in parallel with each other, and a dielectric layer 8b is formed so as to completely cover the address electrodes 11. On the dielectric layer 8b, a partition 9 is provided at a position where the address electrode 11 is interposed therebetween.
1 and a space extending in a direction parallel to the address electrodes 11 partitioned by the partition walls 9 is formed. In each of these spaces, a phosphor that emits color light by ultraviolet irradiation is applied to the wall surface of the partition wall 9 and the surface of the dielectric layer 8b, and the phosphor 10R applied to every third space is The phosphor 10G applied to the red space and the other two spaces emits green light, and the phosphor 10B applied to the other two spaces emits the blue light.

On the other hand, on the front glass substrate 4, X transparent electrodes 5a and Y transparent electrodes 6a are arranged alternately and parallel to each other in a direction orthogonal to the address electrodes 11 formed on the rear glass substrate 12. An X bus electrode 5b and a Y bus electrode 6b are formed on the X transparent electrode 5a and the Y transparent electrode 6a, respectively. Here, one adjacent X transparent electrode 5a and one Y transparent electrode 6a
In the same electrode pair, the X bus electrode 5b is formed at the end of the X transparent electrode 5a opposite to the Y transparent electrode 6a, and the Y bus electrode 6b is connected to the Y transparent electrode 6a.
a at the end opposite to the X transparent electrode 5a. A dielectric layer 8a is formed so as to completely cover the X transparent electrode 5a and the Y transparent electrode 6a and the X bus electrode 5b and the Y bus electrode 6b, and furthermore, MgO or the like is formed on the dielectric layer 8a. Is formed.

The rear glass substrate 12 provided with the electrodes and the like and the front glass substrate 4 are abutted as shown by arrows, and the protective film on the front glass substrate 4 is formed on the partition walls 9 of the rear glass substrate 12. The panel 1 is configured so that 7 contacts.

The protective film 7 and the phosphors 10R, 10R
A predetermined gas is sealed in the discharge space 13 formed by the partition 9 coated with G and 10B and the dielectric layer 8b.
Also, the X bus electrode 5b and the Y bus electrode 6b in the same electrode pair
The space located between the two forms one discharge cell.

FIG. 4 is a diagram showing the wiring of each electrode in the panel 1 shown in FIG. 3, wherein A1,..., Al (where l is an integer of 1 or more) are the address electrodes shown in FIG. 11, X
1, X2,..., Xm (where m is an integer of 1 or more) is the X electrode 5 composed of the X transparent electrode 5a and the X bus electrode 5b shown in FIG. 3, and Y1, Y2,. The Y electrode 6 includes the Y transparent electrode 6a and the Y bus electrode 6b shown in FIG.

In FIG. 1, a panel 1 has m X electrodes X1, X2,..., Xm and Y electrodes Y1, Y2,
,..., Xm are arranged in parallel and alternately with each other. One end of each of the X electrodes X1, X2,.
, Ym are provided independently of each other, and different drive waveforms are applied to each of them. Also, the n address electrodes A1,..., An are independent of each other and the X electrodes X
1, X2,..., Xm and Y electrodes Y1, Y2,.
m, and different drive waveforms are applied to them.

FIG. 5 is a diagram showing an example of a conventional driving method in one field of the plasma display panel 1 having the above-described structure. The horizontal axis represents time, and the vertical axis represents the Y electrode Y1.
ＹYm, respectively.

In this figure, one field period 15 is composed of eight subfields SF1 to SF8, the total time of all subfields, and one of the vertical synchronization signal Vsync.
It is assumed that the period includes a blank period 14 that is generated by a difference from the periodic period.

FIG. 6 shows the ith (where i =
It is a figure which shows the structure of subfield SFi of 1,2, ..., 8). However, the description of this subfield SFi is the same for all subfields.

In FIG. 1, a subfield SFi is composed of an entire reset period T _R , an address discharge period T _A, and a sustain discharge period T _S. The entire reset period T _R and the address discharge period T _A correspond to all the subfields SFi, respectively.
And the same time length is required, for example, the address period T _A
Is determined by the number m of Y electrodes (FIG. 4) and the period of the scan pulse applied to each Y electrode 6 in order. The sustain discharge period T _S is determined by the pulse period and the number of sustain discharge pulses forming a pulse train.

In the entire reset period T _R , discharge is performed between the X electrode 5 and the Y electrode 6 for all the cells, thereby making the wall charges uniform. In the address period T _A, performs discharge between the Y electrode 6 and address electrodes 11 in the cell to perform sustain discharge in the sustain discharge period T _S, the discharge cells perform a sustain discharge during the sustain discharge period T _S select. Then, in the selected cell, the discharge is repeatedly performed by the number of sustain discharge pulses applied in the sustain discharge period T _S of the subfield SFi. Here, as shown in FIG.
The number of subfields in one field is eight, and as described above, these subfields SF1, SF2,.
.., The number of sustain discharge pulses in the sustain discharge period T _S of SF8 is weighted by, for example, a binary code. Now, the subfields SF1, SF2,..., S
Assuming that the number of sustain discharge pulses applied in the sustain discharge period T _S of F8 (that is, the number of sustain discharges) is N _{SF1 to} N _SF8 , the ratio of the number of sustain discharges is the above-mentioned weighting ratio, that is, a binary code. N _SF1 : N _SF2 :...: N _SF8
= 1: 2: 4: 8:...: 128, and 256 combinations of subfields in which sustain discharge is performed in the sustain discharge period T _S enable 256 types of gradation display. For example,
In the case where a certain discharge cell displays the tenth gradation (excluding the gradation 0) from the low luminance, the subfield S corresponding to the relative ratio of the number of sustain discharge pulses of 2 and 8 respectively.
F2 and SF4 may be selected by the address discharge, and the sustain discharge may be performed in each sustain discharge period T _S.

FIG. 7 is a diagram showing a part of a driving waveform of an example of a conventional driving method of the panel 1 having such a configuration. The horizontal axis represents time, and the vertical axis represents a voltage applied to the X electrode 5 in order from the top. , Y
The voltage applied to the electrode 6 and the voltage applied to the address electrode 11 are respectively shown. Here, all the X electrodes X1 to X1
The same voltage is applied to Xm.
The voltage applied to the electrodes Y1 and Ym is shown. For the address electrode 11, the voltage applied to the address electrode An is shown.

FIG. 7 shows an example in which the preceding subfield S
When the application of the last sustain discharge pulse 17 of the voltage Vs to the Y electrode 6 is completed in the sustain discharge period of Fi, during the entire reset period of the next succeeding subfield SF (i + 1),
At the time of full write discharge, a full write discharge pulse 19 of a positive voltage Vw is applied to the X electrode 5 serving as an anode to perform full write discharge.

By the way, according to the above conventional driving method,
During the entire reset period of each subfield, all the X electrodes are simultaneously supplied with the entire reset pulse 19 of the voltage Vw as described with reference to FIG. It is applied.

If a very large number of cells are discharged at the same time, a very large current will flow through the X electrode and its driving circuit, and the resistance of these X electrodes and transistors such as transistors in the driving circuit. A large voltage drop is caused by the resistance of the circuit element, and as shown in FIG. The size of the reduced portion 19a increases as the number of cells increases, and each cell has a sufficient voltage value Vw.
Will not be applied.

When the entire reset pulse 19 rises, discharge is performed in the cell slightly later than that. When the discharge starts, the discharge current increases, and the above-mentioned voltage drop increases to cause a full reset. Pulse 19 decreases.

When the voltage value of all reset pulses 19 decreases in this manner, sufficient discharge is not performed in each cell, and each cell is inconvenient for performing an address discharge in the next address period. Wall charges remain, which may cause an error in the operation of selecting a cell to be subjected to sustain discharge during the sustain discharge period. In particular, when the definition of the plasma display panel is advanced and the number of cells is further increased, this becomes a more serious problem.

On the other hand, in Japanese Patent Application Laid-Open No. Hei 7-191627, as shown in FIG. 9, the X and Y electrodes of the panel are divided into a plurality (here, three) blocks in the arrangement direction. In each subfield, first, preliminary discharge and preliminary discharge erase (all reset) for block 1 are performed.
, Address discharge, and the first sustain discharge in the sustain discharge period, and the same operation is performed from the initial sustain discharge period in the block 1 from the full reset of the next block 2. Then, all reset, address discharge, and first sustain discharge are sequentially performed for each block, and when such an operation is completed for all blocks, the remaining sustain discharge is performed for all these blocks. Even if the generated wall charge is small, the first sustain discharge in the sustain discharge period is performed immediately after that, so that the wall charge becomes large,
When the above operation is completed for all blocks and the remaining sustain discharge is performed at the same time, a sufficient wall charge is obtained, and a technique is disclosed that facilitates the transition of discharge to the sustain discharge period. .

According to the prior art, since all resets are performed for each block, the number of cells to be reset simultaneously is smaller than the number of cells of the entire panel.
The discharge current during the entire reset period of each block is also reduced, and the voltage value of all the reset pulses is also reduced, so that a more preferable amount of wall charge is formed as compared with the case where the entire panel is simultaneously reset-discharged. Will be done.

[0027]

However, in the conventional driving method as shown in FIG. 9, a driving circuit for the X electrodes is required for each block, and variations in characteristics among these driving circuits are completely eliminated. Cannot be excluded. Further, the characteristics cannot be completely completely matched between the cells. Thus, the characteristics are different between the respective blocks.

If the characteristics are different as described above, the voltage values of all reset pulses vary between blocks, and even if these voltage values are accurately matched, the discharge current due to all resets differs. At least the amount of wall charges formed for each block varies. When such a variation occurs, the sustain discharge is also affected, and the contrast or the like varies from block to block, resulting in deterioration in image quality.

An object of the present invention is to provide a method of driving a plasma display panel which solves such a problem and can prevent deterioration of image quality while reducing discharge current during the entire reset period. .

[0030]

In order to achieve the above-mentioned object, the present invention provides a plurality of cell lines each including a first and a second electrode arranged in parallel on a front glass substrate. Are sequentially arranged in the arrangement, the lines are divided into n lines (where n is an integer of 1 or more) in the arrangement sequence to form line segments, and the odd-numbered line segments and the even-numbered line segments are arranged. The timing of the entire reset discharge period is made different from the line section.

With this configuration, the number of cells to be discharged in the same all-reset discharge period is reduced as compared with the case where all-reset discharge is performed simultaneously for all cells. The voltage drop is reduced, and the voltage drop of all the reset pulses is suppressed, so that the celite discharge in each cell is favorably performed. In addition, even if the drive circuits for the odd-numbered line sections and the even-numbered line sections have variations in the characteristics, the effects of the respective characteristics will appear uniformly on the entire panel, and therefore, such variations in the characteristics will also occur. The uniformity over the entire panel makes the influence of the variation less noticeable.

Further, according to the present invention, each of the above-mentioned sub-fields may be constituted by an entire reset discharge period of an odd-numbered line section, an address discharge period of an odd-numbered line section, a total reset discharge period of an even-numbered line section, and an even-numbered line section. The address discharge period of the line section, the sustain discharge period of the odd-numbered and even-numbered line sections, or the order in which the order of the odd-numbered and even-numbered lines is replaced.

According to this configuration, the timing of the entire reset discharge period is different between the odd-numbered line section and the even-numbered line section. Therefore, the same operation as described above is performed, and the address discharge period in each line section is also reduced. As compared with the case where the address discharge of all the cells is performed in one address discharge period, the time is sufficiently short, and the time from the reset discharge to the address discharge of all the cells is shortened.
Therefore, the address discharge is performed in a state where the space charge generated by the reset discharge is good.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a view showing one embodiment of a driving method of a plasma display panel according to the present invention, wherein X ₁
To X _2m X-electrodes, Xo is the odd-numbered X electrodes, Xe is the even-numbered X electrodes, Y ₁ to Y _2m is Y electrodes, Yo odd-numbered Y electrodes, Ye even-numbered Y electrodes, 1 Plasma display panels (hereinafter simply referred to as panels) 2 and 3 are X electrode drive circuits.

As shown in FIG. 3, the panel 1 has X electrodes and Y electrodes alternately arranged in parallel with each other by 2 m pieces, as described above with reference to FIG. X electrodes X ₁ , X ₃ ,..., X arranged in odd order in order
_2m-1 is an electrode Xo, and X electrodes X ₂ ,
X _4, ......, X _2m to represent electrode Xe and respectively, likewise, Y electrodes Y ₁ to be arranged in the odd-numbered, Y _3, ......, is arranged Y _2m-1 and the electrode Yo, the even-numbered Y electrodes Y ₂ , Y ₄ , ...
..., and the Y _2m represents electrodes Ye and respectively. A series of cells are formed by adjacent odd-numbered X electrodes Xo and Y electrodes Yo.
In addition, a row of a series of cells between adjacent even-numbered X electrodes Xe and Y electrodes Ye is referred to as an even-numbered line Le.

The odd-numbered X electrodes Xo are simultaneously driven by the driving circuit 2, and the even-numbered X electrodes Xe are driven by the driving circuit 3.
Driven at the same time. Also in this embodiment,
As described with reference to FIG. 5, one field 15 is divided into a plurality of (for example, eight) subfields SF, and each subfield SF is composed of an entire reset discharge period, an address discharge period, and a sustain discharge period. However, since the odd-numbered X electrodes Xo and the even-numbered X electrodes Xe are configured to be driven by different driving circuits, all of the odd-numbered X electrodes Xo and the even-numbered X electrodes Xe are formed. The timings of the reset discharge period and the address discharge period are made different.

FIG. 1 is a diagram showing the configuration of each subfield SF in this embodiment.

In the figure, in the subfield SF,
First, the reset discharge period T _R o is provided by applying a reset pulse simultaneously to the odd-numbered all X electrodes Xo from the drive circuit 2, the odd-numbered every line Lo, to perform a reset discharge The wall charges are made uniform in the cells of all the lines Lo. Next, an address discharge period T _A o is provided, and by applying a scan pulse to the odd-numbered Y electrodes Yo in the order of arrangement, and applying an address pulse to a desired address electrode (not shown), A discharge is performed between the Y electrode Yo and the address electrode in the cell in which the sustain discharge is performed during the subsequent sustain discharge period on the line Lo, and a discharge cell performing the sustain discharge is selected. As described above, first, in the period To illustrated, the reset discharge and the address discharge in the odd-numbered line Lo are performed.

Next, the reset discharge period T _R e is provided, by applying a reset pulse simultaneously to all the X electrodes Xe in even numbers from the driving circuit 3, for all the even-numbered lines Le, reset Discharge is performed, and wall charges are made uniform in the cells of all these lines Le. Next, an address discharge period T _A e is provided, and a scan pulse is applied to the even-numbered Y electrodes Ye in the order of arrangement, and an address pulse is applied to a desired address electrode (not shown), whereby an even-numbered Y electrode Ye is applied. A discharge is performed between the Y electrode Ye and the address electrode in a cell in which the sustain discharge is performed during the sustain discharge period in the line Le, and a discharge cell in which the sustain discharge is performed is selected. Thus, in the illustrated period Te, the even-numbered line L
Reset discharge and address discharge at e are performed.

By the above operation, the reset discharge in all the cells on panel 1 and the address discharge in the desired cells to be sustained are performed.
When such operation is completed, then, all the X in the sustain discharge period T _S, the discharge sustain pulse to the Y electrode is applied, address discharge period T _A o, the sustain discharge of T _A e in the selected discharge cell Done.

As described above, the X electrodes are replaced with the odd-numbered X electrodes X.
o and even-numbered X electrodes Xe.
Since the timing of the reset discharge is different between o and the X electrode Xe, the number of cells to be reset discharged at the same time is halved and sufficiently reduced as compared with the case where the cells of the entire panel 1 are simultaneously reset discharged. At this time, the discharge current is also reduced by half and becomes sufficiently small, and the number of X electrodes through which the discharge current flows is also reduced by half, so that the voltage drop due to the X electrodes and the circuit elements of the driving circuit becomes sufficiently small, and at the same time, the reset is performed. The decrease in the voltage value as described with reference to FIG. 8 due to the reset pulse applied to the cells to be performed can be suppressed, and the wall charges are formed in each cell in a sufficiently satisfactory state.

In addition, there is a variation in the characteristics of the drive circuit 2 for the odd-numbered X electrodes Xo and the drive circuit 3 for the even-numbered X electrodes Xe, and the odd-numbered lines Lo and the even-numbered lines Le form a cell. Even if the amount of wall charges formed varies, the influence of the characteristics of the drive circuit 2 appears on the X electrodes Xo over the entire panel 1, and the influence of the characteristics of the drive circuit 3 on the entire panel 1. Since it appears on the electrode Xe, the influence of the variation in the characteristics of the drive circuits 2 and 3 is uniformly distributed throughout the panel 1, and therefore, the influence is hardly a problem.

The address discharge period T shown in FIG.
_A o, T _A in e, in either a reset discharge period T _R o, if T _R e is completed, immediately odd-numbered Y electrodes Yo
(That is, in the order of Y ₁ , Y ₃ ,..., Y _2m-1 , assuming that the number of lines in the panel 1 is 2 m), and the order of arrangement of the even-numbered Y electrodes Ye (ie, Y ₂ , Y ₄ , ..., Y _2m
Scan pulses) are applied. Therefore, these address discharge period T _A o, T _A e is the panel 1 than the case of applying a scanning pulse sequentially for the whole Y electrodes, it will be approximately halved. So, for all cells,
The elapsed time from when the reset discharge is performed to when the address discharge is performed is shorter than when a scan pulse is sequentially applied to the Y electrodes of the entire panel 1. For this reason,
The address discharge is performed while the amount of space charge generated by the reset discharge is small, so that the discharge cells for the sustain discharge are selected with high precision, thereby preventing the malfunction of the sustain discharge and deteriorating the image quality. Is suppressed.

In the above-described embodiment, the reset discharge and the address discharge are performed at different timings for the odd-numbered lines Lo and the even-numbered lines Le, respectively. N pieces in order
(Where, n is an integer of 1 or more) are classified by the respective line section, in FIG. 1, and the reset discharge period T _R o, an address discharge period T _A o and for odd-numbered line section, a reset discharge period T _R e, the address discharge period T _A e may be used for even-numbered line division.

Further, this is expanded to α (however, α
Are set to (α + 1) line division groups each including one or more integer divisions, a drive circuit is provided for each line division group, and reset discharge is performed for each line division group as shown in FIG. A period and an address discharge period may be provided. However, in this case, n and α are sufficiently smaller than the number of lines 2 m on the panel 1.

Further, in the above-described embodiment, the reset discharge period in which all cells are reset-discharged in all the sub-fields constituting the field is provided. All reset discharge period is provided only in subfield,
In the other sub-fields, there is a driving method in which only the discharge cells that have undergone the sustain discharge are reset. In this driving method, however, the odd reset period is used as the total reset discharge period as shown in FIG. , The even-numbered lines Lo and Le, or the odd- and even-numbered line sections, or the line section groups, the reset discharge timing and the address discharge timing may be made different.

[0048]

As described above, according to the present invention,
Since the number of cells for performing the reset discharge for forming the wall charges simultaneously in the cells can be sufficiently reduced, and the discharge current at the time of such reset discharge can be reduced, the formation state of the wall charges in all the cells is good. As a result, the address discharge in the selected cell can be performed favorably.

Further, according to the present invention, for all cells,
The elapsed time from the reset discharge to the address discharge can be shortened, the address discharge of the selected cell can be performed in a good space charge state, and the cell to be sustained is reliably selected to perform the sustain discharge. This makes it possible to eliminate malfunction and prevent image quality deterioration.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a subfield in a driving method of a plasma display panel according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an embodiment of a driving method of a plasma display panel according to the present invention.

FIG. 3 is an exploded perspective view showing a part of the structure of the AC type plasma display panel.

FIG. 4 is a diagram schematically showing an arrangement relationship of each electrode in an AC type plasma display panel.

FIG. 5 is a diagram showing a field configuration for driving an AC type plasma display panel.

FIG. 6 is a diagram showing a configuration of a subfield in FIG. 5;

FIG. 7 is a diagram showing a driving waveform of an example of a conventional driving method of a plasma display panel.

FIG. 8 is a waveform diagram showing all reset pulses in a conventional plasma display panel and the effects of the discharge current.

FIG. 9 is a diagram showing another example of a conventional driving method of a plasma display panel.

[Explanation of symbols]

 Reference Signs List 1 plasma display panel 2, 3 drive circuit 4 front glass substrate 5 X electrode 6 Y electrode Xo odd-numbered X electrode Xe even-numbered X electrode Yo odd-numbered Y electrode Ye even-numbered Y electrode Lo odd-numbered line Le even number Th line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takahisa Mizuta 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Information Media Business Division of Hitachi, Ltd.

Claims (3)

[Claims] 1. A plasma display panel comprising a plurality of lines sequentially arranged on a front glass substrate, the first and second electrodes being arranged in parallel with each other as one line.
The field is divided into a plurality of subfields, and at least one subfield is composed of a full reset discharge period, an address discharge period, and a sustain discharge period, and the first and second lines of each line are provided for each of these periods. In a method of driving by supplying a drive pulse to an electrode in accordance with a predetermined rule, the lines are divided into n lines (where n is an integer of 1 or more) in the order of arrangement, and each line is divided into lines. In the sub-field having odd-numbered line segments, the timing of the reset discharge period is made different between the odd-numbered line segments and the even-numbered line segments, and the reset discharge of all cells in the odd-numbered line segments and the even-numbered line segments are performed. A reset discharge of all cells in the plasma display panel at a shifted timing. 2. A plasma display panel comprising a front glass substrate and a plurality of lines sequentially arranged with a first electrode and a second electrode arranged in parallel with each other as one line.
The field is divided into a plurality of subfields, and at least one subfield is composed of a full reset discharge period, an address discharge period, and a sustain discharge period, and the first and second lines of each line are provided for each of these periods. In a method of driving by supplying a drive pulse to an electrode according to a predetermined rule, the lines are divided into n lines (where n is an integer of 1 or more) in the order of arrangement, and each line is divided into lines. The sub-field has a total reset discharge period for resetting all cells of the odd-numbered line segment, a first address discharge period for cells of the odd-numbered line segment, and a cell for even-numbered line segments. Reset discharge period, a second address discharge period for the even-numbered cells of the line section, an odd-numbered and even-numbered A plasma display panel comprising a sequence of sustain discharge periods for sustaining discharge of cells selected in the first and second address discharge periods in a line section, or a sequence in which the order of the odd and even numbers is interchanged. Drive method. 3. A plasma display panel in which a plurality of lines are sequentially arranged on a front glass substrate, the first and second electrodes being arranged in parallel with each other as one line.
The field is divided into a plurality of subfields, and at least one subfield is composed of a full reset discharge period, an address discharge period, and a sustain discharge period, and the first and second lines of each line are provided for each of these periods. In a method of driving by supplying a drive pulse to an electrode in accordance with a predetermined rule, the lines are divided into n (where n is an integer of 1 or more) in the order of arrangement, and each line is divided into lines. (Α + 1) line segment groups composed of the line segments are set (here, α is an integer of 1 or more, and n and α are sufficiently smaller than the total number of lines in the plasma display panel), In the subfield having the entire reset discharge period, a timing is different between the reset discharge period and the address discharge period for each line group. Zuma display panel driving method.