JP5026682B2 - PDP data driver and plasma display device using the same - Google Patents

Description

The present invention relates to a PDP data driver (data driver for a plasma display panel) and a plasma display device using the same .

A plasma display panel (hereinafter abbreviated as PDP) is generally thin, has no flicker, has a large display contrast ratio, is relatively easy to enlarge, has a high response speed, and is self-luminous. It has many features such as multi-color emission according to the selection of the phosphor.
For this reason, in recent years, PDPs have been widely used in fields such as computer-related display devices and home-use flat-screen television receivers.

Depending on the operation method, the PDP has an electrode covered with a dielectric and is operated in an AC discharge state indirectly, and an electrode is exposed to the discharge space, and a DC discharge. There is a DC discharge type that is operated in the above state.
Further, the AC discharge type includes a memory operation type that uses the memory function of the discharge cell and a refresh operation type that does not use the memory function of the discharge cell.
The refresh operation type is used mainly in the case of a small PDP having a small display capacity because the luminance decreases as the display capacity increases. In recent years, an AC discharge memory operation type is mainly used for a thin-screen television set.

FIG. 15 is a sectional view showing a configuration of one display cell in a general AC discharge memory operation type PDP.
As shown in FIG. 15, each display cell of the AC discharge memory operation type PDP includes a rear insulating substrate 1 made of glass, a front insulating substrate 2 made of glass, and a transparent scanning electrode formed on the front insulating substrate 2. 3, a transparent sustain electrode 4, a trace electrode 5 disposed so as to overlap the scan electrode 3, a trace electrode 6 disposed so as to overlap the sustain electrode 4, and a scan electrode on the back insulating substrate 1 3 and a data electrode 7 formed orthogonal to the sustain electrode 4 and a discharge gas filled with a discharge gas made of helium (H), neon (Ne), xenon (Xe), or a mixed gas thereof The space 8 and the discharge gas space 8 are secured, the partition wall 9 for separating the display cells, the phosphor 11 for converting the ultraviolet rays generated by the discharge of the discharge gas into the visible light 10, the scanning electrode 3 and the maintenance electrode. A dielectric film 12 covering the electrode 4, a protective layer 13 made of magnesium oxide (MgO) or the like for protecting the dielectric film 12 from discharge, and a dielectric film 14 covering the data electrode 7 are roughly configured. .

Next, the discharge operation of the selected display cell will be described with reference to FIG.
When a pulse voltage exceeding the discharge threshold is applied between the scan electrode 3 and the data electrode 7 to start discharge, positive and negative charges are generated from the dielectric film 12 and the dielectric film corresponding to the polarity of the pulse voltage. It is attracted to the surface of the body film 14 to cause charge accumulation. The wall voltage, which is an equivalent internal voltage due to this charge accumulation, has a polarity opposite to that of the pulse voltage, so the effective voltage inside the display cell decreases with the growth of the discharge, and the applied pulse voltage has a constant value. Even if held, the discharge cannot be maintained, and the discharge eventually stops.
Thereafter, when a sustain pulse having a pulse voltage having the same polarity as the wall voltage is applied between the adjacent scan electrode 3 and sustain electrode 4, the wall voltage is superimposed as an effective voltage. Even if the amplitude is small, the discharge can exceed the discharge threshold. Therefore, the discharge can be maintained by continuously applying the sustain pulse between the scan electrode 3 and the sustain electrode 4.
This function is the memory function of the discharge cell. Further, the scan electrode 3 or the sustain electrode 4 has a wide low voltage pulse that neutralizes the wall voltage, or a narrow erase pulse that is a pulse of a narrow sustain pulse voltage, and its transition time is several V. The above-mentioned sustain discharge can be stopped by applying a gentle pulse of about / microsecond.

Next, the configuration of a conventional PDP drive device will be described with reference to FIG. FIG. 16 is a block diagram showing an example of a conventional PDP driving device.
The PDP 21 is provided with a sustain electrode group 42 and a scan electrode group 53 parallel to each other on one surface thereof, and a data electrode group on the opposite surface in a direction orthogonal to the sustain electrode group 42 and the scan electrode group 53. 32 is provided, and the display cell 22 is formed at each intersection of the sustain electrode, the scan electrode, and the data electrode. The sustain electrodes X are provided close to the scan electrodes Y1, Y2, Y3,..., Yn (n is an arbitrary positive integer), and one ends thereof are connected in common.

Next, a description will be given of the configuration of a plurality of types of driver circuits necessary for driving the display cell 22 and a control circuit for controlling these driver circuits in a conventional PDP driving apparatus.
For the purpose of address discharge of the display cell 22, the data driver 31 that drives data of the data electrode group 32 for one line and the sustain electrode 42 are commonly used for the sustain discharge of the display cell 22. A sustain side driver circuit 40 for causing the scan electrode group 53 to perform a sustain discharge in common is provided.
Further, for the purpose of performing selective write discharge in the address period, a scan driver 55 that sequentially scans the scan electrode group 53 including the scan electrodes Y1 to Yn is provided. The scan driver 55 causes the scan-side driver circuit 50 to apply a sustain pulse to its own power supply to cause a sustain discharge.

The control circuit 61 controls all the operations of the data driver 31, the sustain side driver circuit 40, the scanning side driver circuit 50, the scanning driver 55, and the PDP 21.
The main part of the control circuit 61 is composed of a display data control unit 62 and a drive timing control unit 63. The display data control unit 62 rearranges display data input from the outside into data for driving the PDP 21 and temporarily stores the rearranged display data string, and scan driver 55 at the time of address discharge. And a function of transferring the data as display data DATA to the data driver 31 in accordance with the sequential scanning. The drive timing control unit 63 converts various signals such as a dot clock input from the outside into an internal control signal for driving the PDP 21, and controls each driver and driver circuit.

Next, with reference to FIG. 17, a driving sequence in a conventional PDP driving apparatus will be described. FIG. 17 is a time chart showing a state in which a plurality of subfields are formed in one field in a conventional PDP driving apparatus.
In FIG. 17, for example, the number of subfields (hereinafter abbreviated as “SF”) having different weights formed by dividing one field having a period of 16.7 ms is set to eight. Then, by appropriately combining these subfields and defining the drive sequence, 256 gradations can be displayed.
Each subfield is divided into a scanning period in which display data is written according to the weight of the subfield and a sustain discharge period in which display data for which writing is designated is displayed. One field image is displayed.

FIG. 18 shows the detailed operation of a subfield having a certain weight. The common sustain electrode drive waveform Wx applied to the sustain electrode X and the scan electrode drive applied to the scan electrodes Y1 to Yn. Waveforms Wy1 to Wyn and data electrode drive waveform Wdi (1 ≦ i ≦ k) applied to data electrodes D1 to Dk are shown.
One cycle of the subfield is composed of a scanning period and a sustain discharge period, and the scanning period is composed of a preliminary discharge period and an address discharge period. By repeating these, a desired video display is realized. It has become. The preliminary discharge period is used as necessary and may be omitted.

The preliminary discharge period is a period for generating active particles and wall charges in the discharge gas space in order to realize stable address discharge in the address discharge period, and is a preliminary discharge that simultaneously discharges all display cells of the PDP. It is formed by a pulse and a preliminary discharge erasing pulse for extinguishing a charge that hinders the write discharge and the sustain discharge among the wall charges generated by the application of the preliminary discharge pulse.
The sustain discharge period is a period in which light is emitted by performing a sustain discharge using a memory operation in order to obtain a desired luminance in a display cell that has performed an address discharge in the address discharge period.

In the preliminary discharge period, first, a preliminary discharge pulse Pp is applied to the sustain electrode X to cause discharge in all display cells. Thereafter, a preliminary discharge erasing pulse Ppe is applied to the scan electrodes Y1 to Yn to generate an erasing discharge, thereby erasing wall charges accumulated by the preliminary discharging pulse.
Subsequently, in the write discharge period, the scan pulse Pw is applied to the scan electrodes Y1 to Yn in a line-sequential manner, and the data pulse Pd is selectively applied to the data electrode Di (1 ≦ i ≦ k) corresponding to the video display data. When applied, a write discharge is generated in the cell to be displayed to generate wall charges.
Subsequently, in the sustain discharge period, only the display cell that has caused the write discharge continuously generates the sustain discharge by the sustain pulses Pc and Ps. After the last sustain discharge is performed by the final sustain pulse Pce, the wall discharge that has been formed is erased by the sustain discharge erasing pulse Pse, and the sustain discharge is stopped to complete the light emission operation on one surface.
Note that the luminance of the PDP is proportional to the number of discharges, that is, the number of repetitions of the pulse voltage within a unit time.

Next, the operation of the address driver circuit for generating the address discharge in the conventional PDP will be described in more detail.
The data driver 31 shown in FIG. 16 is generally configured using a plurality of PDP data driver ICs having tens to hundreds of display data output terminals.
A PDP data driver IC (hereinafter simply referred to as a data driver IC) has a function of outputting a data pulse corresponding to display data to a PDP panel. In general, a data driver IC has several tens to several hundreds of terminals for outputting data pulses, and the data pulses are composed of binary values of high level or low level.

For example, as shown in FIG. 19, the data driver IC includes a shift register 101, a latch circuit 102, an output control circuit 103, and a high breakdown voltage buffer 104.
The shift register 101 has a function of transferring and holding display data DATA105 input from one or a plurality of display data input terminals by a clock CLK106. The latch circuit 102 includes a register, and has a function of capturing and holding display data accumulated in the shift register 101 by a latch signal from the latch input terminal LE107. The display data fetched into the latch circuit 102 is output from the output terminal 108 as a data pulse through the output control circuit 103 and the high withstand voltage buffer 104.

  In general, the output control circuit 103 includes a high blank control terminal HBLK109 for inputting a high blanking signal for setting all data pulse outputs of the data driver IC to a high level (hereinafter referred to as high blank), A row blank control terminal LBLK110 for inputting a row blanking signal for setting a data pulse to a low level (hereinafter referred to as row blank) is provided. However, since the high blank control terminal HBLK109 and the low blank control terminal LBLK110 are intended to control all data pulse outputs simultaneously, each data driver IC has only one terminal.

The output control circuit 103 and the high voltage buffer 104 of the data driver IC have a configuration as shown in FIG. 20, for example.
As shown in FIG. 20, the output control circuit 103 includes buffer strings Ba1, Ba2, Ba3,..., Ba (n-2), Ba (n-1), Ban, and gate strings Ga1, Ga2 composed of NAND circuits. , Ga3,..., Ga (n-2), Ga (n-1), Gan, and gate rows Gb1, Gb2, Gb3,. Gbn.
.., Ga (n−2), Ga (n−1), and Gan all the NAND gates have one input and the previous buffer columns Ba1, Ba2, BAa,. , Ba (n-2), Ba (n-1), Ban are connected to the input data IDATA1, IDATA2, IDATA3, ..., IDATA (n-2), IDATA (n-1), IDATAn, and the other input Are connected in parallel to the high blank control terminal HBLK.
Further, all NAND gates constituting the gate rows Gb1, Gb2, Gb3,..., Gb (n-2), Gb (n-1), Gbn have one input connected to the preceding gate row Ga1, Ga2, Ga3, respectively. ,..., Ga (n−2), Ga (n−1), and Gan, and the other input is connected in parallel to the row / blank control terminal LBLK.

  The high-voltage buffer 104 has inputs connected to the outputs of the preceding gate lines Gb1, Gb2, Gb3,..., Gb (n-2), Gb (n-1), Gbn, and outputs to the output terminals OUT1. , OUT2, OUT3,..., OUT (n-2), OUT (n-1), OUTn, and high voltage buffer circuits Bb1,..., Bbn connected between the high voltage power source and the ground. ing.

In the circuit shown in FIG. 20, since both the high blank control terminal HBLK and the low blank control terminal LBLK are low active, when both are high, the display data IDATA1 to IDATAAn input from the previous latch circuit are Output as is. When only the high blank control terminal HBLK is set to active (low level), all outputs become high level (high blank) regardless of input data. Further, when the row / blank control terminal LBLK is set to active (low level), all outputs are set to the low level (low blank) regardless of the input data.
Here, in the high blank state, by setting the data electrode to a high level (for example, about 80 V), the voltage between the data electrode and the scan electrode is lowered, so that the counter discharge between both electrodes is stopped. Be controlled. In the row / blank state, the application of the data pulse to the data electrode is forcibly terminated.
Such a data driver IC is also described in Non-Patent Document 1, for example. However, Non-Patent Document 1 describes that the output voltage of the data driver is controlled to a high level, a low level, or a high impedance. However, in the present invention, the output voltage is set to a high level and a low level. Only the points controlled by the level are targeted.

FIG. 21 shows a general connection method between the data driver IC and the PDP.
As shown in FIG. 21, in the PDP 21, there are data electrodes for each of a red display cell, a green display cell, and a blue display cell (hereinafter, red is displayed as R, green is displayed as G, and blue is displayed as B). They are arranged in that order, and the output terminals of the data driver IC are sequentially connected thereto.
In the PDP 21, as described above, in the address period, a data pulse is applied to the data electrode to select a cell to be displayed. At this time, the control circuit 61 sends display data DATA to each data driver IC. , Clock CLK, latch signal, high blanking signal, low blanking signal and the like are input to the respective input terminals, whereby the data driver 31 outputs a data pulse to the PDP 21.
NEC Paper Machine: μPD16373, NEC Corporation General Technology Devices Division, Sales Technology Support Group, March 2001 (p.5, Truth Table 3 (Driver)) and others)

The PDP is composed of cells of each color of RGB, and phosphors of any color of RGB are applied to each cell. Since the phosphors of each color of RGB have different physical properties, the voltage characteristics of the cells for each color may be different.
At this time, if the difference in voltage characteristics for each color is large, erroneous lighting occurs at the time of display, so that the display quality deteriorates or the necessary panel drive voltage increases, so that the withstand voltage of the drive circuit element can be increased. This causes a problem that it becomes necessary and causes an increase in the cost of the product.

On the other hand, in the PDP, it is the data electrode that can independently drive the cells of each color of RGB, so that the drive pulse is independently applied to the data electrodes of the cells of each color corresponding to RGB in each period other than the writing period. Thus, a driving method for compensating the voltage characteristics of each color is conceivable.
In this case, in the case of the connection relationship between the PDP 21 and the data driver 31 as shown in FIG. 21, in order to apply the drive pulse to each of the RGB cells independently, display data is input to the data driver. Therefore, it is necessary to control ON / OFF of the pulse output for each color output terminal of the data driver.
However, it takes several microseconds to transfer display data to the shift register of the data driver IC that constitutes the data driver. Therefore, in order to be able to control each RGB color independently, pulse switching is required. Occasionally, there is a restriction that such a data transfer time is required.

  As a method for avoiding such a problem, as shown in FIG. 22, it can be considered that a data driver is separated and provided independently for each color of the PDP. As described above, a general data driver IC has a function for forcibly setting all its output terminals to a high level or a low level. If this function is used, data transfer is not performed. In addition, it is possible to apply a drive pulse to the data electrode. In this case, since the connection shown in FIG. 21 cannot be controlled independently for each color of RGB, by providing a data driver independently for each color as shown in FIG. Can be controlled independently.

However, if the connection as shown in FIG. 22 is made between the PDP and the data driver IC, there is a demerit that the wiring from the data driver 31 to the PDP 21 becomes complicated.
In general, the data driver 31 and the PDP 21 are connected by a flexible printed circuit board (hereinafter abbreviated as FPC) or the like. Therefore, if an attempt is made to make a connection as shown in FIG. 22 in an FPC that connects a printed circuit board on which a data driver IC is mounted and the PDP, the shape of the printed circuit board increases or the number of layers of the printed circuit board increases. It becomes necessary to increase the cost.

Particularly in recent PDPs, it is common to use COF (Chip On Film) or TCP (Tape Carrier Package) etc. in which a data driver IC is directly mounted on an FPC for cost reduction. Furthermore, in order to perform wiring as shown in FIG. 22, it is necessary to mount at least three data driver ICs on the FPC, and the shape of the FPC becomes large. This results in higher costs than mounting a driver IC.
Furthermore, in order to route the wiring on the FPC as shown in FIG. 22, it is necessary to use a double-sided FPC, which further increases the cost. Is possible. In addition, it is conceivable to mount a plurality of data driver ICs with a reduced number of output terminals on the FPC. However, in this case, the number of ICs used increases, which inevitably increases the cost.

The present invention has been made in view of the above-described circumstances, and makes it possible to realize compensation for differences in voltage characteristics of phosphors of RGB colors in a PDP without increasing the cost, and a PDP data driver therefor An object of the present invention is to provide a plasma display device using the above.

In order to solve the above problems, the invention described in claim 1 relates to a PDP data driver, and a plurality of PDP data drivers that sequentially drive a data electrode group of a plasma display panel (hereinafter referred to as PDP) according to display data are arranged. In the output control circuit of each data driver IC , three input / output terminals are provided for each color of red (R), green (G), and blue (B) constituting the screen of the PDP . In addition to dividing into groups, a first gate row is provided corresponding to each input / output, and in the first gate row, input data is output as it is for each group according to a first control input. or it is configured to perform one of the control is set to high level, further providing the second gate array subsequent to said first gate array, a gate array of the second In accordance with the second control input, each group is configured to control whether the output data of the corresponding first gate column is output as it is or set to a low level, In the PDP pre-discharge period, a pre-discharge pulse composed of a sawtooth wave is applied to the scan electrode to generate a pre-discharge between the scan electrode, the sustain electrode and the data electrode, and then the PDP data is applied during the pre-discharge pulse application. From the state in which the R, G, and B data electrode groups are set to the low level by the driver, first, the R data electrode group is controlled to be set to the high level, and the preliminary discharge is terminated. by terminating the predischarge performs control to set the data electrode group to the high level, that is configured to control the termination timing of the preliminary discharge R, G, for each electrode group B It is characterized.

According to a second aspect of the present invention, there is provided a first substrate having a plurality of electrode pairs each composed of a scan electrode and a sustain electrode parallel to each other, and a second substrate having a plurality of data electrodes so as to be orthogonal to the electrode pairs. The electrode pair and the data electrode are driven by a driving circuit so that the display cell formed at each intersection of the electrode pair and the data electrode between the two substrates emits light. A digital signal processing circuit for controlling a digital image information formed by converting the format of an analog image signal or a digital image signal and outputting a signal for driving the PDP and a control signal It relates to a plasma display device formed by adding a circuit for the circuit and a power supply, a driving circuit for driving the data electrodes, made of PDP data driver according to claim 1 It is characterized by a door.

According to the configuration of the present invention , it is not necessary to make the data driver independent for each group (R, G, B) . Therefore, the preliminary discharge of the PDP can be performed without complicating the wiring between the data driver IC and the PDP. During the period, the preliminary discharge is terminated for each color by controlling the data electrode to be set to a high level for each group during the preliminary discharge pulse application and terminating the preliminary discharge.

A PDP data driver that drives a data electrode group of a PDP according to display data is composed of a plurality of data driver ICs arranged in sequence, and in the output control circuit of each data driver IC, the red color that constitutes the screen for the input / output terminals (R), green (G), and blue (B) are divided into three groups for each color, and a first gate row and a second gate row are sequentially provided corresponding to each input / output. in one gate array, for each group in response to a first control input, do the control sets the input data to, or high level is output as it is, in the second gate array, a second control wherein each group in response to the input, or whether to transfer the output data of the corresponding first gate array as it performs one of the control is set to low level.

  FIG. 1 is a circuit diagram showing a configuration of an output control circuit and a high voltage buffer in the PDP data driver IC according to the first embodiment of the present invention. FIG. 2 shows an output control circuit of the PDP data driver IC in the present embodiment. FIG. 3 is a timing chart showing the operation of the output control circuit of the PDP data driver IC and the high voltage buffer in the present embodiment, and FIG. 4 is a diagram showing the PDP data driver IC of the present embodiment. FIG. 5 is a timing chart showing a driving method for a general PDP preliminary discharge period, and FIG. 6 is a diagram showing a PDP according to the present embodiment. It is a timing chart which shows the drive method of the preliminary discharge period.

As shown in FIG. 1, the PDP data driver IC in this example includes an output control circuit 103A and a high breakdown voltage buffer 104A.
The output control circuit 103A includes buffer strings BA1, BA2, BA3,..., BA (3n-2), BA (3n-1), BA3n, and gate strings GA1, GA2, GA3,. -2), GA (3n-1), GA3n, and gate rows GB1, GB2, GB3, ..., GB (3n-2), GB (3n-1), GB3n comprising NAND circuits.
.., GA (3n-2), GA (3n-1), and GA3n, all the NAND gates receive one input and are connected to the preceding buffer columns BA1, BA2, BA3,. , BA (3n-2), BA (3n-1), BA3n are connected to the input data IDATA1, IDATA2, IDATA3,..., IDATA (3n-2), IDATA (3n-1), IDATA3n. , GA (3n-2) are connected to the first high blank control terminal HBLK1, and GA2, GA5, ..., GA (3n-1) are connected to the second input. The GA3, GA6,..., GA3n are connected to the third high blank control terminal HBLK3.
Further, all NAND gates constituting the gate arrays GB1, GB2, GB3,..., GB (3n-2), GB (3n-1), GB3n have one input connected to the preceding gate arrays GA1, GA2, GA3, respectively. ,..., GA (3n-2), GA (3n-1), and GA3n are connected to the outputs, but the other inputs are all connected to the row / blank control terminal LBLK.

  Further, the high voltage buffer 104A has inputs connected to the outputs of the preceding gate lines GB1, GB2, GB3,..., GB (3n-2), GB (3n-1), GB3n, and outputs respectively to the output terminal OUT1. , OUT2, OUT3,..., OUT (3n-2), OUT (3n-1), OUT3n and high-voltage buffer circuits BB1,..., BB3n connected between the high-voltage power source and the ground. ing.

  Thus, in the data driver IC of this example, the output is divided into three groups, and corresponding to the divided three groups represented by 3n-2, 3n-1, and 3n in the order of arrangement, By providing the high blank control terminals HBLK1, HBLK2, and HBLK3, the outputs of the three groups can be set to a high blank independently.

In the case of the circuit shown in FIG. 1, the truth table of the output control circuit of the PDP data driver IC and the high voltage buffer is as shown in FIG. That is,
Since the high blank control terminals HBLK1, HBLK2, and HBLK3 and the low blank control terminal LBLK are low active, the high blank control terminals HBLK1, HBLK2, HBLK3, and the low blank control terminal LBLK are all at a high level. In this case, the display data is output as it is to the output corresponding to the display data IDATA (3n-2), IDATA (3n-1), and IDATA3n input from the latch circuit in the previous stage.
When only the high blank control terminal HBLK1 is set to active (low level), the output data OUT1, OUT4,..., OUT (3n-2) become high level (high blank) regardless of the input data. .
When only the high blank control terminal HBLK2 is set active (low level), the output data OUT2, OUT5,..., OUT (3n-1) are high level (high blank) regardless of the input data. become.
Further, when only the high blank control terminal HBLK3 is set active (low level), the output data OUT3, OUT6,..., OUT3n become high level (high blank) regardless of the input data.

Therefore, the operation of the output control circuit of the PDP data driver IC and the high voltage buffer in the circuit shown in FIG. 1 is as shown in the timing chart shown in FIG. 3, and independently in the output group divided into three. High blank control can be performed.
In FIG. 3, by setting the output OUT (3n-2), OUT (3n-1) or OUT3n to high blank, the display data IDATA (3n-2), IDATA (3n-1) or IDATA3n are respectively set. The corresponding data electrode is set to a high level (for example, about 80V), the voltage between the data electrode and the scan electrode is lowered, and the opposing discharge between the two electrodes is stopped independently. In the row / blank state, the application of data pulses to the data electrodes corresponding to the display data IDATA (3n-2), IDATA (3n-1), and IDATA3n is forcibly terminated.

  Thus, according to the data driver of this example, the display data IDATA (3n-2), IDATA (3n-1), and IDATA3n corresponding to the respective colors of red (R), green (G), and blue (B) A high blank can be set independently for each color, and a low blank can be set for each color data electrode at the same time.

Next, a preferred application example of the data driver of this example will be described with reference to FIGS.
In the PDP, the data electrodes of each color are sequentially arranged as R, G, B, R, G, B, R,. In this case, the difference in voltage characteristics of the cells of each color of RGB can be compensated by controlling the input waveform. Therefore, in this example, the output terminals of the data driver ICs divided into the first to third groups are connected to the R, G, and B electrodes of the PDP 21, respectively, as shown in FIG. .

Hereinafter, a driving example in the PDP having the circuit configuration shown in FIG. 1 will be described. This driving method uses the function of the data driver IC in the preliminary discharge period of the PDP driving waveform shown in FIG.
The preliminary discharge pulse Pp shown in FIG. 17 is a sawtooth wave, the potential change has a gradient of about several volts per microsecond, and the final ultimate potential is a pulse of about 300V to 400V.
When this preliminary discharge pulse Pp is applied and its potential exceeds the discharge start voltage between the scan electrode and the sustain electrode and between the data electrodes, a weak discharge is generated and the discharge continues while the potential is changing. . And when the final potential is reached, the discharge stops. The preliminary discharge pulse is applied for the purpose of activation in the cell and equalization of wall charges.

In the PDP, each color cell is separately coated with R, G, and B phosphors. As described above, the voltage characteristics of each color cell differ depending on the electrical characteristics of the phosphors. Yes.
When the voltage characteristics of the cells of each color are different as described above, since the phosphor is on the data substrate, a significant difference occurs in the discharge start voltage between the data electrode and the scan electrode or between the data electrode and the sustain electrode.

For example, assume that the discharge start voltage between the data electrode and the scan electrode is 190 V for the R cell, 195 V for the G cell, and 200 V for the B cell, and the final potential of the preliminary discharge pulse Pp is 300 V. In the case of a general PDP, as shown in FIG. 5, when the potential of the preliminary discharge pulse Pp reaches 190V, discharge of the R cell is started, then discharge of the G cell is started, and finally discharge of the B cell is started. After that, the discharge of each cell continues until the potential of the preliminary discharge pulse Pp reaches 300V, and the discharge is also stopped when the rise of the potential is stopped. Note that light emission waveforms R, G, and B shown in FIG. 5 are discharge light emission waveforms generated between the scan electrode and the data electrodes Wd-R, Wd-G, and Wd-B, respectively.
In the discharge in this case, since the data electrode serves as a cathode, positive wall charges are accumulated in the data electrode. This wall charge amount is most in the R cell having a long discharge duration, and in the G cell. Next to B, there are the fewest B cells.

The wall charges accumulated in this way are then superimposed on the positive data pulse applied to the data electrode during the write discharge period, thereby lowering the discharge start voltage and facilitating the occurrence of the write discharge. Produce.
At this time, in the B cell having the highest discharge start voltage, the final ultimate potential of the preliminary discharge pulse Pp is set so that such an effect sufficiently occurs. Therefore, the cell having the low discharge start voltage, particularly the discharge start voltage is the highest. In the low R cell, an excessive preliminary discharge is generated.
Since the preliminary discharge occurs regardless of whether the cell is selected or not, the result is an increase in the brightness of the cell that should display black, thereby causing a so-called “black floating” phenomenon and improving the display quality of the image. Will be reduced.

On the other hand, in the data driver IC of this example, after the preliminary discharge occurs, during the application of the preliminary discharge pulse Pp, the data bias pulse Pdb is applied to the data electrode, and the preliminary discharge of the cell having a low discharge start voltage is maintained. By shortening the period, excessive preliminary discharge in a cell having a low discharge start voltage is suppressed, and an increase in luminance of the black display cell is prevented.
FIG. 6 is a timing chart showing a driving method during the preliminary discharge period in the PDP using the data driver IC of this example.
In this example, after the preliminary discharge occurs, during the application of the preliminary discharge pulse Pp, the data bias pulse Pdb is applied to the data electrode, the amplitude of this pulse is set to 80 V, and the voltage applied between the data electrode and the scan electrode is By reducing the voltage by 80 V, the preliminary discharge between the data electrode and the scan electrode is stopped. The light emission waveforms R, G, and B shown in FIG. 6 are discharge light emission waveforms generated between the scan electrode and the data electrodes Wd-R, Wd-G, and Wd-B, respectively.

As shown in FIG. 6, by applying the data bias voltage Pdb (R) to the R data electrode Wd-R and applying the data bias voltage Pdb (G) to the G data electrode Wd-G in the order shown, Excessive preliminary discharge in the R cell and G cell can be stopped.
Thus, by preventing excessive preliminary discharge in the R cell and the G cell, it is possible to suppress an increase in the luminance of black display and improve the display quality of the image.

However, in actuality, in the driving method of the data driver IC described above, when the rising slope of the preliminary discharge pulse is a potential change of 6 V per microsecond, the data bias pulse Pdb is pulsed at intervals of 1 microsecond or less. Since it is necessary to apply the data, considering the data transfer operation of the shift register 101, there is no time for transferring such a signal as a normal data display signal.
Therefore, instead of using the data bias pulse Pdb, a function of setting a high blank for the data electrode is used. Therefore, as shown in FIG. 1, the high blanking function for forcibly setting the output to the high level is divided into R, G, and B, and the divided high blank control terminals HBLK1 to HBLK1 are divided into three. 3 is connected to the R, G, B data electrodes of the PDP so that the same 80 V pulse as that of the data bias pulse Pdb is applied during the preliminary discharge period by the high blank control. Thus, it is possible to control such excessive preliminary discharge.

As described above, in the data driver IC of this example, in the output control circuit 103A, the high blank control terminal for performing the high blank control is divided and controlled for each of the R, G, B cells, and the preliminary discharge pulse Pp. By applying a high blank to the data electrode corresponding to a cell having a color with a low pre-discharge start voltage during application, the data for each color is reduced by shortening the pre-discharge duration of the cell with a low pre-discharge voltage. Compensate for the difference in pre-discharge period based on the difference in voltage characteristics of the phosphor in each color cell without the need to make the driver independent, and thus without complicating the wiring between the data driver IC and the PDP. It is possible to suppress the excessive preliminary discharge generated in the color cell and improve the image display quality.
The conventional data driver IC shown in FIG. 19 can also suppress the preliminary discharge in the preliminary discharge period, but it is possible to control the discharge period independently for each color as in this example. Can not.

As shown in FIGS. 1 to 3, in this example, by setting the high blank control terminals HBLK1 to HBLK1 to a low level, outputs OUT (3n-2), OUT (3n-1), and OUT3n, respectively. Is set to high blank, and the low blank control terminal LBLK is set to low level, thereby setting the outputs OUT (3n-2), OUT (3n-1), and OUT3n to low blank. Instead of setting the row / blank control terminal LBLK to a low level, all the outputs of OUT (3n-2), OUT (3n-1), and OUT3n can be set to a low level by a data signal. In this case, the gate trains GB1, GB2, GB3,..., GB (3n-2), GB (3n-1), GB3n are not necessary, so that the output control circuit 103A can be made simpler.
In this example, the stop timing of the preliminary discharge between the data electrode and the scan electrode is controlled independently for each color cell. For example, the difference in the discharge start voltage between the R cell and the G cell is small. In the case where only the difference between the discharge start voltage of the B cell and the discharge start voltage of the cells of other colors is large, the R cell and the G cell are controlled by only the two terminals of the high blank control terminals HBLK1 and HBLK2 in the configuration shown in FIG. The stop timing of the preliminary discharge of the cell and the stop timing of the preliminary discharge of the B cell may be controlled independently, thereby further simplifying the configuration of the output control circuit 103A.

  FIG. 7 is a circuit diagram showing the configuration of the output control circuit and the high voltage buffer in the PDP data driver IC according to the second embodiment of the present invention. FIG. 8 shows the output control circuit of the PDP data driver IC in this embodiment. FIG. 9 is a timing chart showing a driving method during a write discharge period of the plasma display in this embodiment, and FIG. 10 shows a capacitance between adjacent data electrodes in the plasma display panel. It is a schematic diagram.

As shown in FIG. 7, the PDP data driver IC in this example includes an output control circuit 103B and a high breakdown voltage buffer 104A.
In the output control circuit 103B, buffer rows BA1, BA2, BA3,..., BA (3n-2), BA (3n-1), BA3n, and gate rows GA1, GA2, GA3,. -2), GA (3n-1), GA3n are the same as the circuit of the first embodiment shown in FIG. 1, but the gate trains GC1, GC2, GC3,. The input method of the row / blank control signal to GC (3n-2), GC (3n-1), and GC3n is different.
The high voltage buffer 104A is the same as that of the first embodiment shown in FIG.

.., GA (3n-2), GA (3n-1), and GA3n, all the NAND gates receive one input and are connected to the preceding buffer columns BA1, BA2, BA3,. , BA (3n-2), BA (3n-1), BA3n, the other inputs are GA1, GA4,..., GA (3n-2) are the first high blank. , GA (3n−1) are connected to the second high blank terminal HBLK2, and GA3, GA6,..., GA3n are connected to the third high blank terminal HBLK3. It is connected.
In addition, all NAND gates constituting the gate rows GB1, GB2, GB3,..., GB (3n-2), GB (3n-1), GB3n have one input connected to the preceding gate rows GA1, GA2, GA3, respectively. ,..., GA (3n-2), GA (3n-1), and BG3n are connected to the outputs of GB1, GB4,. .., GB (3n-1) are connected to the second row blank terminal LBLK2, and GB3, GB6,..., GB3n are third row blank terminals. Connected to LBLK3.

  In this way, in the data driver IC of this example, since the output is divided into three groups, it corresponds to the divided three groups represented by 3n-2, 3n-1, and 3n in the order of arrangement. By providing the high blank control terminals HBLK1, HBLK2, and HBLK3 and the low blank control terminals LBLK1, LBLK2, and LBLK3, respectively, the outputs of the three groups can be set to the high blank and the low blank, respectively. Can do.

In the case of the circuit shown in FIG. 7, the truth table of the output control circuit of the PDP data driver IC and the high voltage buffer is as shown in FIG.
The high blank control terminals HBLK1, HBLK2, and HBLK3 and the low blank control terminals LBLK1, LBLK2, and LBLK3 are each low active.
When the high blank control terminal HBLK1 and the low blank control terminal LBLK1 are both at the high level, the display data IDATA1, IDATA4,..., IDATA (3n-2) input from the preceding latch circuit are directly output as OUT1 and OUT4. ,..., OUT (3n-2). When only the high blank control terminal HBLK1 is set active (low level), the outputs OUT1, OUT4,..., OUT (3n-2) become high level (high blank) regardless of the input data. When the low / blank control terminal LBLK1 is set active (low level), the outputs OUT1, OUT4,..., OUT (3n-2) become low level (high blank).

  When the high blank control terminal HBLK2 and the low blank control terminal LBLK2 are both at the high level, the display data IDATA2, IDATA5,..., IDATA (3n-1) input from the previous latch circuit are directly OUT2, Output to OUT5,..., OUT (3n-1). When only the high blank control terminal HBLK2 is set active (low level), the outputs OUT2, OUT5,..., OUT (3n-1) become high level (high blank) regardless of the input data. Further, when the row / blank control terminal lBLK2 is set to active (low level), the outputs OUT2, OUT5,..., OUT (3n-1) become low level (low blank).

  Similarly, when the high blank control terminal HBLK3 and the low blank control terminal LBLK3 are both at the high level, the display data IDATA3, IDATA6,..., IDATA3n input from the preceding latch circuit are directly output as OUT3, OUT6,. , OUT3n. When only the high blank control terminal HBLK3 is set active (low level), the outputs OUT3, OUT6,..., OUT3n become high level (high blank) regardless of the input data. Further, when the row / blank control terminal lBLK3 is set to active (low level), the outputs OUT3, OUT6,..., OUT3n become low level (low blank).

As described above, in the circuit shown in FIG. 7, high blanks are respectively provided corresponding to the output groups of the output terminals represented by 3n-2, 3n-1, and 3n divided into three groups of data driver ICs. Control terminals HBLK1, HBLK2, and HBLK3 and row and blank control terminals LBLK1, LBLK2, and LBLK3 are provided, and the outputs of the three groups can be independently controlled to a high blank and a low blank.
In the case of the configuration shown in FIG. 7, not only the high blank control terminal but also the low blank control terminal is divided into three, so that the PDP drive control in the preliminary discharge period similar to the case of the first embodiment can be performed. In addition, drive control different from this can be performed.

Next, a preferred application example of the data driver of this example will be described with reference to FIGS.
As described above, in the write discharge period, the data pulse corresponding to the display data is applied to the data electrode. At this time, an electromagnetic wave is generated when a displacement current for charging and discharging the data electrode flows. Moreover, since all the data electrodes are driven simultaneously, the level of this electromagnetic wave is high, which can cause noise.
Therefore, in the data driver IC of this example, electromagnetic waves can be suppressed by reducing the number of data electrodes driven at the same time by using the three-partitioned row blanking.

In the data driver IC of this example, the data electrodes are driven in the write discharge period according to the timing chart shown in FIG. 9 using row blanking divided into three.
In FIG. 9, Pd (R), Pd (G), and Pd (B) indicate waveforms of data pulses applied to the R data electrode, the G data electrode, and the B data electrode, respectively, and LBLK (R), LBLK (G ), LBLK (B) are row blanking signals for driving the R data electrode, G data electrode, and B data electrode, respectively, and LE is a latch enable signal for transferring the data in the shift register 101 to the high breakdown voltage buffer 104. is there. Vd indicates the peak value of the output voltage of the data pulse, and is set to several tens of volts. In each LBLK signal and LE signal, H indicates the high level of the logic signal, and L indicates the low level. In general, H is a voltage of about several V (for example, 5 V or less), and L is a GND level.

In the data driver IC of this example, at the end of the data pulse, in each of the R, G, and B electrode groups, the timing is shifted and the row blanking is activated to set the data pulse to the GND level. Next, the LE signal is activated, and the next display data is transferred from the shift register to the high voltage buffer. Thereafter, row blanking is canceled at different timings for each of the R, G, and B electrode groups, and the next data pulse is applied.
By doing so, the application timing of the data pulse can be shifted for each of the R, G, and B electrode groups.

As described above, in the data driver IC of this example, it is not necessary to make the data driver independent for each color, and therefore, R, G, B data pulses are not required without complicating the wiring between the data driver IC and the PDP. By shifting the application timing little by little, the number of data electrode drives within the same time can be reduced, so that electromagnetic waves based on the displacement current can be suppressed.
In addition, since the application timing of the data pulse to the data electrode is shifted for each color of R, G, and B, the driving method of this example shifts the data pulse application timing between the adjacent data electrodes. Since there is a capacitance between the data electrodes as shown in FIG. 10, the rise of the data pulse becomes slow compared to the case where a pulse is applied simultaneously between adjacent cells. Therefore, even if the number of data electrodes driven simultaneously is the same, the driving method of this example in which the application timing of the data pulse is shifted between adjacent data electrodes can further improve the electromagnetic wave suppression effect.
According to the data driver IC of this example, as described above, the image quality can be improved by performing the PDP drive control in the preliminary discharge period using the high / blank setting function as in the case of the first embodiment. It goes without saying that it is possible.

As described above, in the data driver IC of this example, the PDP drive control in the preliminary discharge period can be performed by the low / blank setting function or the high / blank setting function. Therefore, in the configuration shown in FIG. 7, the gate rows GA1, GA2, GA3,..., GA (3n-2), GA (3n-1), GA3n or the gate rows GC1, GC2, GC3,. -2) By providing only one of GC (3n-1) and GC3n, desired control can be performed.
Further, in the second embodiment, it is only necessary to be able to control the application timing of data pulses between adjacent data electrodes, and it is not particularly necessary to drive at three application timings corresponding to the cell colors. Therefore, the cells may be driven at six application timings or nine application timings in the order of arrangement of the cells arranged sequentially, or may be driven at four application timings or eight application timings regardless of the cell color. Also good.
In addition, the application of the data pulse can be shifted to an arbitrary number of timings in the arrangement order of the cells arranged sequentially.

  FIG. 11 is a circuit diagram showing the configuration of the output control circuit and the high voltage buffer in the PDP data driver IC according to the third embodiment of the present invention. FIG. 12 shows the output control circuit of the PDP data driver IC in this embodiment. It is a timing chart which shows operation | movement of a high voltage | pressure-resistant buffer.

In the PDP data driver IC of this example, the output control circuit 103C and the high breakdown voltage buffer 104A have a configuration as shown in FIG.
In the output control circuit 103C, the buffer strings BA1, BA2, BA3,..., BA (3n-2), BA (3n-1), BA3n and the high voltage buffer 104A are the same as those in the first embodiment shown in FIG. Same as the case.

All NAND gates constituting the gate strings GD1, GD2, GD3,..., GD (3n-2), GD (3n-1), GD3n can set one input to a high blank via the buffer BC1. GD1, GD4,..., GD (3n-2) are connected to the first blank timing adjustment input IN1, and GD2, GD5, and GD1, GD4,. ..., GD (3n-1) are connected to the second blank timing adjustment input IN2, and GD3, GD6, ..., GD3n are connected to the third blank timing adjustment input IN3.
.., GE (3n-2), GE (3n-1), and GE3n all input NAND gates GE1, GE2, GE3,. , BA (3n-2), BA (3n-1), and BA3n, and the other inputs are connected to the preceding gate lines GD1, GD2, GD3,..., GD (3n-2), GD (3n, respectively. -1), connected to the output of GD3n.

All the NAND gates constituting the gate rows GF1, GF2, GF3,..., GF (3n-2), GF (3n-1), GF3n can set one input to a row / blank via the buffer BC2. .., GF (3n-2) are connected to the first blank timing adjustment input IN1, and GF2, GF5, GF1, GF4,. ..., GF (3n-1) are connected to the second blank timing adjustment input IN2, and GF3, GF6, ..., GF3n are connected to the third blank timing adjustment input IN3.
All the NAND gates constituting the gate strings GG1, GG2, GG3,..., GG (3n-2), GG (3n-1), GG3n receive one input and the previous gate strings GE1, GE2, GE3,. , GE (3n-2), GE (3n-1), and GE3n, and the other input is connected to the preceding gate row GF1, GF2, GF3, ..., GF (3n-2), GF (3n -1), connected to the output of GF3n.

The data driver IC of this example has its output terminal divided into three groups represented by 3n−2, 3n−1, and 3n, and outputs the divided three groups to high blank and low • Equipped with input terminals HBLK and LBLK that select states that can be set to blanks, and blank timing adjustment inputs IN1, IN2, and IN3 corresponding to the three divided groups, independently adjusting the blank timing of the three groups of outputs The circuit configuration is made possible.
Thus, by having a high blank setting input and a low blank setting input, and having the same number of blank timing adjustment inputs as the number of divided output groups, the high blank and low blank of each output group are obtained. The blank timing can be adjusted independently.

  The circuit shown in FIG. 11 can select a state in which a high blank and a low blank can be set by the HBLK input and the LBLK input, respectively, as shown by the operation timing chart of FIG. Since the HBLK input and the LBLK input are both low active, when both the HBLK input and the LBLK input are at a high level, the display data IDATA1, IDATA2, IDATA3,..., IDATA (3n− 2), IDATA (3n-1), IDATA3n are output as they are. Even if the HBLK input or the LBLK input is active (low level), if the blank timing adjustment inputs are IN1, IN2, and IN3 are non-active (low level), the display data is output as it is. .

  In order to set to high blank or low blank, the blank timing adjustment inputs IN1, IN2, and IN3 are made active (high level) while the HBLK input or LBLK input is active (low level). It is necessary. Since the blank timing adjustment inputs IN1, IN2, and IN3 correspond to the outputs OUT (3n-2), OUT (3n-1), and OUT3n, respectively, they are divided into three by the blank timing adjustment inputs IN1, IN2, and IN3. It is possible to adjust the blank timing of the output group.

As described above, in the data driver IC of this example, there is a restriction that the high blank and the low blank cannot be set simultaneously in different output groups, but the high blank and the low blank of the output group divided into three are included. Can be controlled independently.
Also in the data driver IC of this example, PDP drive control using the same high blank setting function as in the first embodiment, and the same high blank setting function and low level as in the second embodiment. Needless to say, PDP drive control using a blank setting function is possible.

FIG. 13 is a block diagram showing the configuration of the plasma display device according to the fourth embodiment of the present invention.
The plasma display device of this example is characterized in that the data driver is constituted by the data driver IC shown in the first to third embodiments.
The plasma display device 200 of this example is configured to have a module structure, and specifically includes an analog interface 220 and a plasma display panel module 230 as shown in FIG. The plasma display panel module 230 includes a plasma display panel 250.

The analog interface 220 includes a Y / C separation circuit 221 having a chroma decoder, an A / D conversion circuit 222, a synchronization signal control circuit 223 including a PLL circuit, an image format conversion circuit 224, and an inverse γ (gamma). A conversion circuit 225, a system control circuit 226, and a PLE control circuit 227 are included.
In general, the analog interface 220 has a function of converting a received analog video signal into a digital signal and supplying the digital signal to the plasma display panel module 230.

For example, an analog video signal transmitted from a TV tuner is decomposed into RGB luminance signals in a Y / C separation circuit 221 and then converted into a digital signal in an A / D conversion circuit 222.
Thereafter, when the pixel configuration of the plasma display panel module 230 is different from the pixel configuration of the video signal, the image format conversion circuit 224 performs a necessary image format conversion process.

In the plasma display panel, the display luminance characteristic with respect to the input signal is linear, but the normal video signal is corrected (γ correction) in advance in accordance with the characteristics of the CRT (cathode ray tube).
Therefore, after the A / D conversion circuit 222 performs A / D conversion of the video signal, the inverse γ conversion circuit 225 performs inverse γ conversion on the video signal to restore the linear video signal. Is generated. The digital video signal generated in this way is output to the plasma display panel module 230 as an RGB video signal.

Since the analog video signal does not include the sampling clock signal and the data clock signal for A / D conversion, the PLL (phase-locked loop) circuit built in the synchronous signal control circuit 223 simultaneously with the analog video signal. A sampling clock signal and a data clock signal are generated based on the supplied horizontal synchronization signal, and supplied to the plasma display panel module 230.
The PLE control circuit 227 of the analog interface 220 controls the brightness of the plasma display panel. Specifically, the display brightness is controlled to increase when the average brightness level is equal to or lower than a predetermined value, and the display brightness is controlled to decrease when the average brightness level exceeds a predetermined value.
The system control circuit 226 outputs various control signals to the plasma display panel module 230.

The plasma display panel module 230 further includes a digital signal processing / control circuit 231, a panel unit 232, and an in-module power supply circuit 233 incorporating a DC / DC converter.
The digital signal processing / control circuit 231 includes an input interface signal processing circuit 234, a frame memory 235, a memory control circuit 236, and a driver control circuit 237.

For example, the average luminance level of the video signal input to the input interface signal processing circuit 234 is calculated by an input signal average luminance level calculation circuit (not shown) in the input interface signal processing circuit 234 and output as, for example, 5-bit data. Is done.
The PLE control circuit 227 sets PLE control data in accordance with the average luminance level and supplies it to a luminance level control circuit (not shown) in the input interface signal processing circuit 234.

  In the digital signal processing / control circuit 231, the input interface signal processing circuit 234 processes the various input signals described above, and then transmits the control signal to the panel unit 232. At the same time, the memory control circuit 236 transmits a memory control signal and the driver control circuit 237 transmits a driver control signal to the panel unit 232, respectively.

  The panel unit 232 includes a plasma display panel 250, a scan driver 238 that drives scan electrodes of the plasma display panel 250, a data driver 239 that drives data electrodes of the plasma display panel 250, and the plasma display panel 250 and the scan driver 238. A high voltage pulse circuit 240 that supplies a pulse voltage and a power recovery circuit 241 that recovers surplus power from the high voltage pulse circuit 240 are configured.

The plasma display panel 250 is configured to have pixels arranged in, for example, 1365 × 768. In the plasma display panel 250, the scanning driver 238 controls the scanning electrodes, and the data driver 239 controls the data electrodes, thereby controlling lighting or non-lighting of predetermined pixels among these pixels. An image is displayed.
A logic power supply (not shown) supplies logic power to the digital signal processing / control circuit 231 and the panel unit 232. Further, the in-module power supply circuit 233 is supplied with DC power from the display power supply, converts the voltage of the DC power into a predetermined voltage, and then supplies the voltage to the panel unit 232.

In such a plasma display device, the data driver 239 is composed of the data driver IC shown in any of the first to third embodiments, and the data driver output is divided into three groups of RGB to be converted into a PDP. By outputting and performing blanking control described in detail in each embodiment, there is no need to make the data driver independent for each color, and there is no cost increase due to the complicated wiring structure between the data driver and the PDP In addition, the specific effects obtained by the respective embodiments can be obtained.
That is, when the data driver IC of the first embodiment is employed, the high / blank setting for the display data corresponding to each color of R, G, and B can be performed independently for each color. And by using this function, by controlling the time of the preliminary discharge between the data electrode and the scan electrode in the preliminary discharge period for each color, an appropriate time corresponding to the difference in the voltage characteristics of the phosphors of each RGB color can be obtained. Display quality can be improved by performing preliminary discharge.

  Further, when the data driver IC of the second embodiment or the third embodiment is adopted, the high blank setting and the low blank setting for the display data corresponding to each color of R, G, and B are independent of each color. Can be done. And by using the high blank setting function, the time of the counter discharge between the data electrode and the scan electrode in the preliminary discharge period is controlled for each color, so that it is appropriate for the difference in the voltage characteristics of the phosphors of each RGB color It is possible to improve the display quality by performing preliminary discharge for a long time, and by using the row / blank setting function to shift the application timing of the data pulse for each color, Occurrence can be suppressed.

  In this example, as shown in FIG. 13, the plasma display device provided with the analog interface 220 has been described. However, a digital interface is provided instead of the analog interface 220, and a digital image signal is input as an input instead of the analog image signal. The case where it uses is considered.

FIG. 14 shows an example of the configuration of the plasma display device 200A when the personal computer (PC) input signal is a digital RGB signal and the television input signal is a digital luminance signal and a digital color difference signal. The plasma display panel module 230 is generally configured. Among these, the plasma display panel module 230 is the same as that shown in FIG.
The digital interface 220A is roughly composed of an image format conversion circuit 224, an inverse γ conversion circuit 225, a system control circuit 226, a PLE control circuit 227, an RGB conversion circuit 228, and a clock generation circuit 229. Among these, the system control circuit 226 and the PLE control circuit 227 are the same as those shown in FIG.
When the input is composed of a digital RGB signal, a digital luminance signal, and a digital color difference signal, the clock signal is input separately. Therefore, the synchronization signal control circuit shown in FIG. 13 is unnecessary, and the input synchronization signal and clock are input. From the signal, the clock generation circuit 229 generates a sampling clock signal and a data clock signal.

  The RGB conversion circuit 228 converts the digital luminance signal and the digital color difference signal into a digital RGB signal. The image format conversion circuit 224 performs image format conversion processing when the pixel configuration of the plasma display panel module 230 is different from the pixel configuration of the converted digital RGB signal. When the input digital image signal is subjected to γ correction in accordance with the characteristics of the CRT, the inverse γ conversion circuit 225 performs the inverse γ correction and outputs the RGB video signal restored to the linear characteristics.

  As described above, in the plasma display device shown in FIG. 14, even if the input is a digital image signal, the plasma display panel module 230 can perform the same image display as in the case of the analog image signal.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and even if there is a design change or the like without departing from the gist of the present invention. Included in the invention. For example, in each embodiment, the arrangement order of the gate row for performing the high / blank setting and the gate row for performing the low / blank setting may be reversed. In addition, the gate circuit constituting the gate row is not limited to the NAND gate, and may be another gate element.

  The PDP data driver, the PDP driving method, the plasma display device and the control method thereof according to the present invention are not limited to the plasma display panel for television and the plasma display device for television, but are all kinds of computer devices, control devices, measuring devices, and entertainment devices. The present invention can be applied to a plasma display panel and a plasma display device used as a display for the device and various other devices.

FIG. 3 is a circuit diagram showing a configuration of an output control circuit and a high voltage buffer in the PDP data driver IC according to the first embodiment of the present invention. It is a figure which shows the truth table of the output control circuit of the PDP data driver IC and the high voltage | pressure-resistant buffer in the Example. 4 is a timing chart showing operations of an output control circuit and a high voltage buffer of the PDP data driver IC in the same embodiment. It is a figure which shows the connection for controlling each electrode of RGB in PDP independently using the PDP data driver IC of the Example. It is a timing chart which shows the drive method of the preliminary discharge period of a general PDP. It is a timing chart which shows the drive method of the preliminary discharge period of PDP in the Example. It is a circuit diagram which shows the structure of the output control circuit and the high voltage | pressure-resistant buffer in the PDP data driver IC which is 2nd Example of this invention. It is a figure which shows the truth table of the output control circuit of the PDP data driver IC and the high voltage | pressure-resistant buffer in the Example. It is a timing chart which shows the drive method of the write-discharge period of the plasma display in the Example. It is a schematic diagram which shows the electrostatic capacitance between the adjacent data electrodes in a plasma display panel. It is a circuit diagram which shows the structure of the output control circuit and the high voltage | pressure-resistant buffer in the PDP data driver IC which is 3rd Example of this invention. 4 is a timing chart showing operations of an output control circuit and a high voltage buffer of the PDP data driver IC in the same embodiment. It is a block diagram which shows the structure of the plasma display apparatus which is 4th Example of this invention. It is a block diagram which shows the structural example of the plasma display apparatus in case a PC input signal consists of a digital RGB signal and a television input signal consists of a digital luminance signal and a digital color difference signal. It is sectional drawing which shows the structure of the display cell in a general alternating current discharge memory operation type PDP. It is a block diagram which shows an example of the drive device of a general PDP. It is a time chart which shows operation | movement of 1 field in a general PDP. It is a time chart which shows operation | movement of 1 subfield in a general PDP. It is a block diagram which shows the circuit structure of a general PDP data driver IC. It is a figure which shows the circuit structure of the output control circuit and high voltage | pressure-resistant buffer in a general PDP data driver IC. It is a figure which shows the general connection of PDP and a PDP data driver. It is a figure which shows the connection for controlling each RGB electrode of PDP independently using the conventional PDP data driver IC.

Explanation of symbols

21 PDP
31 Data Driver 101 Shift Register 102 Latch Circuit 103, 103A, 103B, 103C Output Control Circuit 104, 104A High Voltage Buffer BA1, BA2, BA3, BA4, BA5, BA6, ..., BA (3n-2), BA (3n- 1), BA3n, BC1, BC2 buffer BB1,..., BB3n high voltage buffer circuit GA1, GA2, GA3,..., GA (3n-2), GA (3n-1), GA3n, GB1, GB2, GB3,. GB (3n-2), GB (3n-1), GB3n, GC1, GC2, GC3,..., GC (3n-2), GC (3n-1), GC3n, GD1, GD2, GD3,. 3n-2), GD (3n-1), GD3n, GE1, GE2, GE3, ..., GE (3n-2), GE (3n-1), GE3 , GF1, GF2, GF3, ..., GF (3n-2), GF (3n-1), GF3n, GG1, GG2, GG3, ..., GG (3n-2), GG (3n-1), GG3n NAND gate

Claims (2)

A PDP data driver for driving a data electrode group of a plasma display panel (hereinafter abbreviated as PDP) according to display data is composed of a plurality of data driver ICs arranged in sequence, and an output control circuit of each data driver IC includes:
The input / output terminals are divided into three groups for each color of red (R), green (G), and blue (B) constituting the screen of the PDP, and a first gate row is provided corresponding to each input / output. The first gate row is configured to control whether the input data is output as it is or set to a high level for each group according to a first control input ,
Further, a second gate row is provided subsequent to the first gate row, and in the second gate row, the output of the corresponding first gate row for each group according to a second control input. It is configured to control whether data is output as is or set to low level,
In the PDP pre-discharge period, a pre-discharge pulse composed of a sawtooth wave is applied to the scan electrode to generate a pre-discharge between the scan electrode, the sustain electrode and the data electrode, and then the PDP data is applied during the pre-discharge pulse application. From the state in which the R, G, and B data electrode groups are set to the low level by the driver, first, the R data electrode group is controlled to be set to the high level, and the preliminary discharge is terminated. It is configured to control the end timing of the preliminary discharge for each of the R, G, and B electrode groups by ending the preliminary discharge by performing control for setting the data electrode group to a high level. PDP data driver. A first substrate having a plurality of electrode pairs each composed of a scan electrode and a sustain electrode parallel to each other, and a second substrate having a plurality of data electrodes so as to be orthogonal to the electrode pairs, For a PDP configured to drive the electrode pair and the data electrode by a driving circuit to emit light at a display cell formed at each intersection of the electrode pair and the data electrode between the two substrates, A digital signal processing circuit that outputs a signal for driving the PDP by processing the digital image information formed by converting the format of the image signal or the digital image signal, a control circuit, and a power supply circuit are added. A plasma display device formed,
2. A plasma display device, wherein a driving circuit for driving the data electrode comprises the PDP data driver according to claim 1 .

Images