KR100692825B1 - Method for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel.

A method of driving a plasma display panel according to the present invention includes a) a first step in which wall charges are formed by surface discharge between a Y electrode and a Z electrode in a reset period of a first subfield, and b) in a reset period of a first subfield. A second step in which the wall charges are erased to a predetermined level by the surface discharge between the Y electrode and the Z electrode, c) an opposite discharge between the X electrode and the Z electrode or between the X electrode and the Y electrode in the reset period of the first subfield. A third step in which the wall charges are erased to a predetermined level by d) a fourth step in which the wall charges are erased to a predetermined level by surface discharge between the Y electrode and the Z electrode in the reset period of the subsequent subfield including the second subfield; And a fifth step in which the wall charges are erased to a predetermined level by the counter discharge between the X electrode and the Y electrode in the reset period of the subsequent subfield including the second subfield.

As described above, according to the present invention, the jitter characteristic is improved and the contrast is improved by the multi-stage reset pulse in the reset period, and thus the mis-discharge can be prevented.

Description

Driving Method for Plasma Display Panel {Method for Driving Plasma Display Panel}

1 illustrates a structure of a general plasma display panel.

2 is a diagram illustrating a driving waveform diagram of a conventional plasma display panel.

3 is another embodiment of a driving waveform diagram of a conventional plasma display panel.

4 is a view illustrating a driving waveform diagram of a plasma display panel according to the present invention.

5 illustrates a reset waveform of a first subfield of a driving waveform according to an embodiment of the present invention.

6 illustrates reset waveforms from a second subfield among driving waveforms according to an embodiment of the present invention.

7A illustrates a light emission waveform due to a reset waveform of a first subfield according to an embodiment of the present invention.

7B illustrates light emission waveforms due to reset waveforms from the second subfield according to an embodiment of the present invention.

8A shows a cell voltage after a reset period of a conventional driving waveform.

8B shows the cell voltage after the reset period of the drive waveform of the present invention.

The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel.

1 illustrates a structure of a general plasma display panel. As shown in FIG. 1, in a typical plasma display panel, a front substrate 10 on which an image is displayed and a rear substrate 20 forming a rear surface are coupled in parallel with a predetermined distance therebetween.

The front substrate 10 includes electrode pairs 11 and 12 for maintaining light emission of cells by mutual discharge in one pixel, that is, transparent electrodes 11a and 12a made of a transparent ITO material and a bus electrode made of a metal material. (11b, 12b). These electrode pairs 11 and 12 serve as Y electrodes and Z electrodes.

The electrode pairs 11 and 12 are covered with a dielectric layer 13a that limits the discharge current and insulates the electrode pairs, and magnesium oxide (MgO) is deposited on the top surface of the dielectric layer 13a to facilitate discharge conditions. The protective layer 14 is formed.

In the rear substrate 20, a plurality of X electrodes 22 performing address discharge in a portion where a plurality of discharge spaces, that is, a partition wall 21 for forming a cell are formed and intersect with the sustain electrodes 11 and 12, are formed. Is placed.

In addition, a dielectric layer 13b is formed on the upper surface of the X electrode 22, and R, G, and B fluorescent layers 23 that emit visible light for displaying an image upon address discharge are coated on the upper surface of the dielectric layer 13b. .

2 is a diagram illustrating a driving waveform diagram of a conventional plasma display panel. In the reset period, the bias voltage is applied to the Z electrode that is commonly bundled and the ramp down waveform voltage is applied to the Y electrode in order to erase the wall charge to a certain degree and to uniform the wall charge of each cell. Initialize the state. At this time, wall charges are accumulated on the dielectrics of the front substrate and the back substrate to be suitable for the address discharge at the last point of the falling ramp-down waveform.

The distribution of wall charges is influenced by the final voltage value of the ramp down waveform. When the final voltage value is 0V, the wall charges accumulated in the dielectrics covering the Y electrode and the Z electrode on the front substrate are not sufficiently erased, which is not suitable for address discharge.

Therefore, the final voltage applied to the Y electrode in the reset period is lowered to a negative voltage to sufficiently erase the wall charge. This waveform has the effect of widening the address voltage margin and shortening the address discharge.

3 is another embodiment of a driving waveform diagram of a conventional plasma display panel. Unlike the driving waveform shown in FIG. 2, the driving waveform shown in FIG. 3 has no erase period. In addition, scan pulses above the second subfield (third subfield, ……) have no ramp-up waveform, and the highest voltage of the scan pulse is less than the highest voltage of the first scan pulse. Able to know.

As shown in FIG. 3, the driving waveform shown in FIG. 3 is formed by the type of charge accumulated in the dielectrics on the Y and Z electrodes of the turned-on cell when the sustain period is completed, and the ramp-up pulse shown in FIG. 2. The types of charges accumulated in the dielectrics on the Y electrode and the Z electrode are the same.

In addition, the types of charges accumulated in the dielectrics on the Y and Z electrodes of the cell turned off during the sustain period and the types of charges accumulated in the dielectrics on the Y and Z electrodes of the cell by the ramp-up pulse shown in FIG. same.

Rather, in the driving waveform shown in Fig. 3, since the charge of the turned-on cell is erased and the turned-off cell does not change its state, black luminance is reduced by not emitting light in the black state. Such driving waveforms form a very good image quality.

However, when such a driving waveform is applied to a plasma display panel having a high Xe content, a scan pulse voltage must be very high due to an increase in the Xe content, and a panel margin is reduced when a large screen is applied. In addition, a plasma display panel having a high Xe content has a long address jitter and does not secure stable sustain in the sustain period.

The present invention is to solve the above problems, and to provide a method of driving a plasma display panel having good contrast and jitter characteristics.

In order to achieve the above object, a method of driving a plasma display panel including an X electrode, a Y electrode, and a Z electrode, the method of driving a plasma display panel according to the present invention includes: a) a Y electrode in a reset period of a first subfield; A first step in which wall charges are formed by surface discharges between the Z electrodes, b) a second step in which wall charges are erased to a predetermined level by surface discharges between the Y and Z electrodes in the reset period of the first subfield, and c) A third step in which the wall charges are erased to a predetermined level by opposing discharge between the X electrode and the Z electrode or between the X electrode and the Y electrode in the reset period of the first subfield, d) a subsequent subfield including the second subfield A fourth step in which the wall charges are erased to a predetermined level by the surface discharge between the Y electrode and the Z electrode in the reset period of the subfield; and e) the reset phrase of the subsequent subfield including the second subfield. And in the wall charge by the opposite discharge between the X electrode and the Y electrode, a fifth step is erased at a predetermined level.
A driving method of a plasma display panel including an X electrode, a Y electrode, and a Z electrode for achieving the above object, the method comprising: a surface discharge between the Y electrode and the Z electrode in at least one subfield of a plurality of subfields; A first step in which charge is formed; A second step in which wall charges are erased to a predetermined level by surface discharge between the Y electrode and the Z electrode; And a third reset section in which a wall charge is erased to a predetermined level by opposing discharge between the X electrode and the Z electrode or between the X electrode and the Y electrode, and at least one other subfield A fourth step in which wall charges are erased to a predetermined level by surface discharge between the Y electrode and the Z electrode; And a second reset section including a fifth step in which wall charges are erased to a predetermined level by opposing discharge between the X electrode and the Y electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating a reset waveform of a first subfield among driving waveforms according to an exemplary embodiment of the present invention.

As shown in FIG. 4, scan pulses are sequentially applied to the Y electrode and data pulses are applied to the X electrode to realize an image. As shown in FIG. 5, the reset section of the first subfield consists of three stages of discharge.

In the first step ①, a ramp up pulse is applied to the Y electrode Y, and surface discharge occurs between the Y electrode Y and the Z electrode Z. FIG. When surface discharge occurs between the Y electrode Y and the Z electrode Z, sufficient wall charges are formed.

In the second step ②, the potential of the Z electrode Z which is the common electrode rapidly rises to Vs, and the potential of the Y electrode drops to -Vmy. At this time, due to the high potential difference between the Y electrode Y and the Z electrode Z, the surface discharge between the Y electrode Y and the Z electrode Z occurs again. This second step (2) discharge partially erases the wall charges formed in the first step (1).

In the third step ③, the potential of the Y electrode Y may be rapidly increased to zero potential, maintained for a predetermined time, and then lowered to the level of -Vny. At this time, the potential of the Z electrode Z may be set to a zero potential or a Vz level lower than Vs. In this third step ③, the potential difference between the Y electrode Y and the Z electrode Z decreases than the second step ②. Further, as the potentials of the Y electrode Y and the Z electrode suddenly change, a potential difference between the Y electrode Y and the X electrode X and a potential difference between the Z electrode Z and the X electrode X occur. Accordingly, the potential difference between the Y electrode Y, the X electrode X, the Z electrode Z, and the X electrode X becomes larger than the potential difference between the Y electrode Y and the Z electrode, thereby increasing the Z electrode Z and the X electrode. Opposite discharges occur between (X) or between the Y electrode Y and the X electrode X. Here, the cell voltage between the Y electrode Y and the Z electrode Z may be slightly lower than the surface discharge starting voltage.

FIG. 6 illustrates reset waveforms from a second subfield among driving waveforms according to an embodiment of the present invention. As shown in FIG. 6, the reset waveform from the second subfield is the same concept as the reset waveform of the second and second steps 2 and 3 in the first subfield. .

That is, in the fourth step (4), the potential of the Z electrode Z, which is the common electrode, rises sharply to Vs, and the potential of the Y electrode drops to -Vmy. As such, surface discharge occurs due to a high potential difference between the Y electrode Y and the Z electrode Z, and the wall charge formed in the sustain section of the first subfield is the surface discharge between the Y electrode Y and the Z electrode Z. It is partially erased.

In the fifth step (⑤), the potential of the Y electrode Y may be rapidly increased to zero potential, maintained for a predetermined time, and then lowered to the level of -Vny. At this time, the potential of the Z electrode Z may be set to a zero potential or a Vz level lower than Vs. As such, the potential difference between the Y electrode Y and the Z electrode Z decreases relatively, and the potential difference between the Y electrode Y and the X electrode X becomes relatively large, thereby increasing the Y electrode Y and the X electrode X. The opposite discharge of the liver occurs. Accordingly, the cell voltage between the Y electrode Y and the Z electrode Z may be slightly lower than the surface discharge starting voltage.

At this time, the reset waveform from the second subfield may ramp down immediately from Vs voltage to -Vmy when falling from Vs voltage to -Vmy voltage, or ramp down to -Vmy after falling from Vs voltage to 0V. You can also descend.

7A illustrates a light emission waveform due to a reset waveform of a first subfield according to an embodiment of the present invention. 7B illustrates light emission waveforms due to reset waveforms from the second subfield according to an embodiment of the present invention.

As shown in FIG. 7A, the wall charge is adjusted by the weak discharge of the first to third steps (①, ②, ③) in the case of the first subfield. In addition, as shown in FIG. 7B, the wall charge is adjusted by the fourth and fifth steps ④ and ⑤ from the second subfield.

In this way, the wall charge is controlled by the surface discharge and the counter discharge in the reset period, so that the wall charge state of all the cells is uniformly formed. That is, as an example, as shown in FIG. 7A, a large voltage is applied to the Y electrode Y in the first step ① to cause surface discharge between the Y electrode Y and the Z electrode Z to form wall charges. Subsequently, in the second step (②), surface discharge is generated between the Y electrode (Y) and the Z electrode (Z) again to erase wall charges. In the third step (③), the counter discharge is discharged, for example, the Z electrode (Z) and the X electrode (X). ), Or opposite discharges between Y electrodes (Y) and X electrodes (X) cause partial wall charges to be erased. In this way, by optimizing the state of the wall charge in the discharge cell so that the address discharge can be more accurately, the address jitter is greatly reduced and the false discharge is reduced.

More specifically, in FIG. 7A, when the potential of the Y electrode Y rises to a large voltage Vry, surface discharge occurs between the Y electrode Y and the Z electrode Z to form wall charges. Further, while the potential of the Y electrode Y drops and the potential of the Z electrode Z rapidly rises to Vs, surface discharge occurs again between the Y electrode Y and the Z electrode Z, and wall charges are erased. When the potential of the Y electrode Y reaches the voltage -Vmy and the potential of the Z electrode Z drops to 0 V or Vz, the potential of the Y electrode Y rises to 0 V and then ramps down again.

As described above, when the potential of the Y electrode Y rapidly rises to 0 V and then ramps down again in the third step ③, between the Z electrode Z and the X electrode X or between the Y electrode Y and the X electrode ( The counter discharge occurs between X) and part of the wall charge is erased to prepare for addressing.

As described above, light emission by the reset waveform over three steps is reduced by about 30% compared to light emission by the reset waveform shown in FIGS. 2 and 3.

As shown in FIGS. 2 and 3, the amount of light emission increases as the potential of the Y electrode decreases and decreases to a negative voltage in the reset period. On the other hand, in the driving waveform of the present invention, the light emission amount is reduced in the second step (②) and the wall charge is controlled by the opposite discharge generated in the third step (③), so the light emission amount is reduced. In other words, by adjusting the voltage applied to the Y electrode in the present invention, the light emission in the reset period is reduced to improve the contrast. For example, light emission in the reset period can be effectively reduced by dropping stepwise to voltages such as -Vmy and -Vny. In addition, it is possible to reduce the amount of light emission by making the negative voltage not too large by controlling the wall charge by the opposite discharge.

FIG. 8A shows a cell voltage after a reset period of a conventional drive waveform, and FIG. 8B shows a cell voltage after a reset period of a drive waveform of the present invention.

As shown in FIG. 8A, the cell voltage Vc, yz between the Y electrode and the Z electrode and the cell voltage Vc, xy between the X electrode and the Y electrode are both a discharge starting voltage in the case of the conventional driving waveform. May be kept equal to (Vc, xy = Vf, xy), (Vc, yz = Vf, yz).

On the other hand, as shown in FIG. 8B, in the driving waveform of the present invention, the cell voltage (Vc, xy) between the X electrode and the Y electrode is maintained at the discharge start voltage Vf, xy, but the cell voltage between the Y electrode and the Z electrode ( Vc, yz is smaller than the discharge start voltage Vf, yz. That is, the cell voltage Vc, yz between the Y electrode and the Z electrode may be smaller than the discharge starting voltage Vf, yz as shown in Vc, yz <Vf, yz of FIG. 8B, for example.

The reason why the cell voltage Vc, yz between the Y electrode and the Z electrode is smaller than the discharge start voltage Vf, yz is because the third step (③) of FIG. 7A or the fifth step (⑤) of FIG. This is because the voltage Vz is applied to the electrode Z. The Vz voltage is an amount determined by the panel and is usually 0V or more and less than Vs. At this time, Vs is a sustain voltage.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

As described above, according to the present invention, the jitter characteristic is improved and the contrast is improved by the multi-stage reset pulse in the reset section, and the mis-discharge can be prevented.

Claims (13)

A driving method of a plasma display panel including an X electrode, a Y electrode, and a Z electrode, A first step of forming wall charges by surface discharge between the Y electrode and the Z electrode in the reset period of the first subfield; A second step of erasing wall charges to a predetermined level by surface discharge between the Y electrode and the Z electrode in the reset period of the first subfield; A third step of erasing wall charge to a predetermined level by opposing discharge between the X electrode and the Z electrode or between the X electrode and the Y electrode in the reset period of the first subfield; A fourth step of erasing wall charges to a predetermined level by surface discharge between the Y electrode and the Z electrode in a reset period of a subsequent subfield including a second subfield; And And a fifth step in which wall charges are erased to a predetermined level by a counter discharge between the X electrode and the Y electrode in a reset period of a subsequent subfield including a second subfield. The method of claim 1, The surface discharge in the first step is performed by a ramp up pulse applied to the Y electrode. The method of claim 1, The surface discharge in the second step is performed by the potential of the Z electrode rapidly rising to Vs and the potential of the Y electrode falling to -Vmy. The method of claim 1, The surface discharge in the third step is maintained by increasing the potential of the Y electrode to zero potential for a predetermined time and then lowering to -Vny, wherein the potential of the Z electrode is a first voltage. Method of driving the display panel. The method of claim 4, wherein And the first voltage is equal to or greater than 0 V and smaller than the voltage Vz applied to the Z electrode during an addressing period. The method of claim 1, The surface discharge in the fourth step is performed by increasing the potential of the Z electrode to Vs and lowering the potential of the Y electrode to -Vmy. The method of claim 6, And the potential of the Y electrode is ramped down from Vs to a voltage of -Vmy. The method of claim 6, And ramping down from 0V to -Vmy after the potential of the Y electrode drops to 0V from the Vs voltage. The method of claim 1, The opposing discharge in the fifth step is performed by maintaining the potential of the Y electrode after rising to zero potential for a predetermined time and decreasing to -Vny, and the potential of the Z electrode being the second voltage. Method of driving the display panel. The method of claim 9, And the second voltage is equal to or greater than 0 V and smaller than the voltage Vz applied to the Z electrode during an addressing period. A driving method of a plasma display panel including an X electrode, a Y electrode, and a Z electrode, A first step of forming wall charges by surface discharge between the Y electrode and the Z electrode in at least one of the plurality of subfields; A second step in which wall charges are erased to a predetermined level by surface discharge between the Y electrode and the Z electrode; And At the same time having a first reset section consisting of a third step of the wall charge is erased to a predetermined level by opposing discharge between the X electrode and the Z electrode or between the X electrode and the Y electrode, A fourth step of eliminating wall charges to a predetermined level by surface discharge between the Y electrode and the Z electrode in at least one other subfield; And And a second reset section comprising a fifth step in which wall charge is erased to a predetermined level by opposing discharge between the X electrode and the Y electrode. The method of claim 11, And the subfield having the first reset section is a first subfield or a lowest gray level subfield. The method of claim 11, And the subfield having the second reset period is all subfields after the first subfield or all subfields except the lowest gray level subfield.

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