KR100562939B1 - Method for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel. In the reset period of the first subfield of the present invention, a voltage falling after the ramp rises is applied to the Y electrode, and a voltage falling after the voltage is kept constant at the Z electrode during the period in which the falling voltage is applied to the Y electrode is applied. Applying a first reset step; And a second reset step of applying a falling voltage while maintaining the ground level to the Y electrode and applying a positive ramp erase voltage to the Z electrode in the reset period of the second or more subfields.

The present invention is composed of three ramp waveforms in the reset section, and by adjusting the Z electrode voltage in the address section, the black brightness is lowered to increase the contrast ratio, the address jitter is reduced, and the single scan is possible, and the driving margin is widened. In addition, it is easy to adjust the wall charge.

Plasma, display, panel, drive, reset, brightness, contrast

Description

Driving Method for Plasma Display Panel {Method for Driving Plasma Display Panel}

1 is a structural diagram of a general AC surface discharge plasma display panel.

FIG. 2 is a driving waveform diagram of the plasma display panel shown in FIG. 1.

3 is another driving waveform diagram of a conventional plasma display panel.

4 is another driving waveform diagram of a conventional plasma display panel.

5 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention.

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel having a low driving brightness, a high contrast ratio, a reduction in address jitter, a single scan, and a wide driving margin.

1 is a structural diagram of a general AC surface discharge plasma display panel. As illustrated in FIG. 1, a typical AC type surface discharge plasma display panel includes a front substrate 122 and a back substrate 124 made of transparent glass facing each other in parallel with each other at predetermined intervals. In this case, the partition wall 126 is formed in parallel on the rear substrate 124 to maintain a distance from the front substrate 122.

Further, columns Xj (j = 1, 2, ..., m) of the X electrodes formed of a conductor between the adjacent partition walls 126 and 126 are formed parallel to the partition walls to perform an addressing function. The light emitting layer 136 is formed while the R, G, and B phosphor films cover the respective X electrodes.

Meanwhile, the row electrodes Yi and Zi (i = 1, 2, ..., n) of the Y electrode and the Z electrode are formed perpendicular to the X electrode on the surface of the front substrate 122 facing the rear substrate 124. Adjacent row electrodes Yi and Zi form a pair to form row electrode pairs Yi and Zi.

Further, in each of the row electrodes Yi and Zi, metal bus electrodes? I and? I narrower than the widths of the row electrodes Yi and Zi are formed in close contact with the row electrodes Yi and Zi. These bus electrodes alpha i and beta i are complementary to the row electrodes Yi and Zi having low conductivity as auxiliary electrodes.

The dielectric layer 130 is formed to protect the row electrodes Yi and Zi. The MgO layer 132 made of magnesium oxide (MgO) is formed in contact with the dielectric layer 130.

 After the electrodes Xj, Yi, Zi, αi, βi, the dielectric layer 130 and the light emitting layer 136 are formed, the front substrate 122 and the back substrate 124 are sealed and exhaust of the discharge space 128 Then, moisture on the surface of the MgO layer 132 is removed by baking. Subsequently, an inert mixed gas including NeXe gas is injected into the discharge space 128 at 400 to 600 torr.

The unit emission region is defined as one pixel cell P _{(i, j)} around the intersection with the Xj electrode intersecting the Yi, Zi electrode. When the wall voltage is formed by the addressing discharge between the Xj electrode and the Yi electrode _{, the} pixel cell P _{(i, j)} is sustained by applying a sustain pulse between the Yi electrode and the Zi electrode, so that the discharge of the phosphor 136 is maintained. The light emission is controlled by selecting, holding and erasing the light emission discharge of the pixel cells P _{(i, j)} by applying voltage between the Xj, Yi and Zi electrodes. At this time, a sustain pulse is alternately applied to the Yi electrode and the Zi electrode, respectively.

FIG. 2 is a driving waveform diagram of the plasma display panel shown in FIG. 1. In the reset period, in order to erase the wall charges to a certain degree, an erase voltage is applied to the Z electrode, which is commonly bundled, and a ramp waveform voltage is applied to the Y electrode to initialize the cell state. At this time, wall charges are accumulated on the dielectrics of the front substrate and the rear substrate to be suitable for the address discharge at the last point of the falling ramp waveform.

The distribution of wall charges is influenced by the final voltage value of the ramp waveform. When the final voltage value is 0V, the wall charges accumulated in the dielectrics covering the Y electrode and the Z electrode on the front substrate are not sufficiently erased, which is not suitable for address discharge. Therefore, the final voltage applied to the Y electrode in the reset period is lowered to a negative voltage to sufficiently erase the wall charge. This waveform has the effect of widening the address voltage margin and shortening the address discharge.

3 is another driving waveform diagram of a conventional plasma display panel. Unlike the driving waveform shown in FIG. 2, the driving waveform shown in FIG. 3 has no erase period. In addition, scan pulses above the second subfield (third subfield, ……) have no ramp-up waveform, and the highest voltage of the scan pulse is less than the highest voltage of the first scan pulse. Able to know.

As shown in FIG. 3, the driving waveform shown in FIG. 3 is formed by the type of charge accumulated in the dielectrics on the Y and Z electrodes of the turned-on cell when the sustain period is completed, and the ramp-up pulse shown in FIG. 2. The kinds of charges accumulated in the dielectrics on the Y electrode and the Z electrode are the same. In addition, the types of charges accumulated in the dielectrics on the Y and Z electrodes of the cell turned off during the sustain period and the types of charges accumulated in the dielectrics on the Y and Z electrodes of the cell by the ramp-up pulse shown in FIG. same. Rather, in the driving waveform shown in Fig. 3, since the charge of the turned-on cell is erased and the turned-off cell does not change its state, black luminance is reduced by not emitting light in the black state. Such driving waveforms form a very good image quality.

However, when the driving waveform is applied to a plasma display panel having a high Xe content, a scan pulse voltage must be very high due to an increase in the Xe content, and a panel margin is reduced when a large screen is applied. In addition, a plasma display panel having a high Xe content has a long address jitter and does not secure stable sustain in the sustain period.

4 is another driving waveform diagram of a conventional plasma display panel. Another conventional driving waveform shown in FIG. 4 is a waveform that can reduce address jitter and stabilize sustain discharge quickly, which is a problem of the driving waveform shown in FIG.

The basic subfield method of the driving waveform shown in FIG. 4 is the same as the conventional waveform shown in FIG. 3, but the waveform of the reset section operates in three stages unlike the conventional driving waveform. That is, it is set so that the discharge of surface discharge 2 and the opposite discharge may occur. In the case of the conventional waveform, when the address is set in the address section by resetting to the surface discharge No. 2, the address discharge generates a discharge in which both the surface discharge and the opposite discharge occur simultaneously.

In the reset period of the driving waveform shown in FIG. 4, the counter discharge is set to occur first in the address discharge, so that address jitter is reduced, and wall charges are sufficiently accumulated in the upper dielectric layer after addressing so that the sustain discharge is quickly stabilized in the sustain period. Have

However, the driving waveform shown in FIG. 4 has a disadvantage in that black luminance is high because a reset waveform having a high voltage is used in all subfields as in the driving waveform shown in FIG. 2, and a ramp waveform is applied to the Y electrode and the Z electrode in the reset period. There is a problem that the circuit becomes complicated because it must be applied.

The present invention is to solve the above problems, lowering the black brightness to increase the contrast ratio, reduce the address jitter to enable a single scan (single-scan) as well as wider the drive margin wall SUMMARY OF THE INVENTION An object of the present invention is to provide a method of driving a plasma display panel that is easy to control charge.

In order to achieve the above object, a plasma display panel is driven by a combination of subfields in which voltage is applied to the X electrode, the Y electrode, and the Z electrode in a reset period, an address period, and a sustain period. In the method, a voltage falling after the ramp is applied to the Y electrode in the reset period of the first subfield, and the voltage is lowered after being kept constant at the Z electrode during the period in which the falling voltage is applied to the Y electrode. Applying a first reset step; And a second reset step of applying a falling voltage while maintaining the ground level to the Y electrode in the reset period of the second or more subfields, and applying a positive ramp erase voltage to the Z electrode.
In this aspect, the second reset step applies the final voltage level applied to the Y electrode to be equal to the final voltage level of the first reset step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention. An image is realized by sequentially applying scan voltages to the Y electrodes Y1 to Yn and applying a data voltage to an address section.

In the conventional driving waveform shown in FIG. 4, the voltage applied to the Y electrode in the reset period includes two lamp rising portions in which the voltage applied to the Z electrode rises after the lamp rises.

On the other hand, in the driving waveform according to the present invention, as shown in FIG. 5, only one voltage applied to the Y electrode exists and the voltage applied to the Z electrode is maintained at a constant voltage. At this time, since a voltage is required by the amount of reduction of the voltage applied to the Z electrode to cause the discharge, the voltage applied to the Y electrode is further lowered by the amount of reduction, causing a discharge between the Y electrode and the Z electrode.

That is, Vmy in the reset period of FIG. 4 is a positive voltage, but Vmy in the reset period of FIG. 5 is a negative voltage, and the voltage applied to the Z electrode is maintained at a constant voltage, thereby discharging the discharge between the Y electrode and the Z electrode. The voltage difference to generate is maintained. Such a driving waveform does not require a lamp voltage on the Z electrode side, so that the driving circuit can be configured more simply.

In addition, the conventional driving waveform shown in FIG. 4 is determined not only by the Vmy voltage but also by the Vrz voltage as the main variable, but the operating point is determined by changing only the Vmy voltage to determine the operating point. It can be chosen easily.

On the other hand, in the ramp falling section of the reset section, both the voltage applied to the Y electrode and the voltage applied to the Z electrode fall in the same manner as the conventional waveform shown in FIG. 4, but since the Vmy value is lower than the conventional one, the -Vny value is as much as Vmy is lower. Lowers. This operation causes two different points from the prior art.

In the conventional driving waveform of FIG. 4, the final wall voltage difference between the Y electrode and the Z electrode just before the address period is almost 0 V, and the wall voltage difference between the X electrode and the Y electrode is about half of the sustain voltage.

However, in the driving waveform according to the present invention, since the voltage applied to the Y electrode is lowered more negatively than before, the wall voltage difference between the Y electrode and the Z electrode is almost close to 0 V as in the prior art, and the wall voltage difference between the X electrode and the Y electrode It is also close to 0V. Therefore, since the wall voltage difference is adjusted to 0V as a whole, resistance to any fluctuation factor becomes strong, which is advantageous for mis-discharge or jitter.

On the other hand, the final cell voltage just before the address is the sum of the wall voltage and the applied voltage. As the wall voltage is close to 0V as described above, the final cell voltage mostly follows the final applied voltage of the Y electrode and the Z electrode. Therefore, since the Y electrode, the Z electrode, and the voltage are larger than the conventional driving waveform shown in FIG. 4, the Vz value of the address period may be lowered.

Next, the reset section at the second subfield or more in the driving waveform according to the present invention will be described.

As shown in FIG. 4, in the conventional driving waveform, after the sustain voltage is finally applied to the Y electrode in the sustain period, an erase pulse is applied to the Z electrode in the erase period, and then the voltage is again applied to the Y electrode in the reset period of the next subfield. Initialization is done by applying.

However, the driving waveform according to the present invention has a separate erasing section, the erase voltage Ve applied to the Z electrode and the voltage Vz of the reset section are combined, and the Y electrode has a waveform which immediately descends without a ramp rising section. At this time, the final voltage level applied to the Y electrode is applied to be equal to the final voltage level of the reset period of the first subfield.

When the cell is turned on in the previous subfield, the erasing is performed by the Ve voltage of the Z electrode. When the cell is turned off in the previous subfield, the reset process is performed without erasing. Even when the reset voltage is applied to the turned-off cell, since the discharge is not generated because it is the same as the previous reset voltage, the wall charge state is maintained.

Since there is no light emission in the resetting process of this section, light emission in the black screen only occurs in the first subfield of the entire subfield, and thus has a very low black luminance compared with the conventional driving waveform shown in FIG. 4. Therefore, the contrast ratio is very high, and excellent image quality can be obtained.

Unlike the voltage waveform applied to the Z electrode of the first subfield, the driving waveform applied to the Z electrode in the reset process of this section erases wall charges of the turned-on cell due to the voltage Ve applied to the Z electrode. The voltage drops to Vz and then ramps down to 0V.

The reason for doing this is to induce a counter discharge by lowering the voltage applied to the Z electrode in order to suppress the surface discharge occurs in the ramp falling section of the voltage applied to the Y electrode if it immediately falls from the Ve voltage. This operation returns to the initial state regardless of whether the cell is turned on or off, thereby ensuring stable driving performance.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

As described above, the present invention comprises three ramp waveforms of the reset section and adjusts the Z electrode voltage of the address section to increase the contrast ratio by reducing the black brightness, reduce the address jitter, and enable a single scan. As well as widening, it is easy to control the wall charge.

Claims (6)

A driving method of a plasma display panel in which gray levels are expressed by a combination of subfields in which voltage is applied to the X electrode, the Y electrode, and the Z electrode in the reset period, the address period, and the sustain period, Applying a falling voltage to the Y electrode after the ramp rises in the reset period of the first subfield, and applying a falling voltage to the Z electrode while the falling voltage is applied to the Y electrode. 1 reset step; And a second reset step of applying a falling voltage while maintaining a ground level to the Y electrode and applying a positive ramp erase voltage to the Z electrode in the reset period of the second or more subfields. Driving method. delete delete delete delete The method of claim 1, And the second reset step applies the final voltage level applied to the Y electrode to be equal to the final voltage level of the first reset step.

Images