KR100622698B1 - Method for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel. The driving method of the plasma display panel of the present invention is a driving method of a plasma display panel in which gray levels are expressed by a combination of subfields in which voltage is applied to the X electrode, the Y electrode, and the Z electrode in the reset period, the address period, and the sustain period. In a subsequent reset period including the second subfield, a first step of ramping up a voltage on the Y electrode; A second step in which the voltage drops in the first step; In the second step, a voltage is applied to the third step of decreasing the voltage, and a voltage that is kept constant is applied to the Z electrode during the second step, and then a voltage of decreasing to a certain slope is applied during the third step. According to the present invention, it is composed of a ramp waveform of three stages of the reset section and by adjusting the Z electrode voltage of the address section to lower the black brightness to increase the contrast ratio, reduce the address jitter to enable a single scan and drive margin As well as widening, it is easy to control the wall charge.

Plasma, display, panel, driven, reset, lamp

Description

Driving Method for Plasma Display Panel {Method for Driving Plasma Display Panel}

1 is a structural diagram of a typical AC surface discharge plasma display panel.

2 is a driving waveform diagram of a conventional plasma display panel.

3 is another drive waveform diagram of a conventional plasma display panel;

4 is another driving waveform diagram of a conventional plasma display panel.

5 is a driving waveform diagram of a conventional plasma display panel.

FIG. 6 is a driving waveform diagram in a method of driving a plasma display panel according to an embodiment of the present invention; FIG.

Fig. 7 is a driving waveform diagram in the driving method of the plasma display panel according to another embodiment of the present invention.

8 is a wall charge distribution diagram of a conventional second subfield reset section.

9 is a wall charge distribution diagram of a second subfield reset section of the present invention.

The present invention relates to a method of driving a plasma display panel. More particularly, the present invention relates to a method of driving a plasma display panel with a low black brightness, a high contrast ratio, a reduction in address jitter, and a single scan.

In general, a plasma display panel emits a phosphor by ultraviolet rays of 147 nm generated when a He + Xe or Ne + Xe inert mixed gas is discharged to display an image including a character or a graphic.

1 is a perspective view illustrating a structure of a general plasma display panel. As shown in FIG. 1, the Y electrode 12A and the Z electrode 12B formed on the upper substrate 10 of the plasma display panel and the X electrode 20 formed on the lower substrate 18 are provided. do.

Each of the Y electrode 12A and the Z electrode 12B includes a transparent electrode and a bus electrode. The transparent electrode is formed of indium tin oxide (ITO). The bus electrode is formed of a metal for reducing resistance.

An upper dielectric layer 14 and a passivation layer 16 are stacked on the upper substrate 10 on which the Y electrode 12A and the Z electrode 12B are formed.

In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. The protective film 16 is usually formed of magnesium oxide (MgO).

Meanwhile, the lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the X electrode 20 is formed. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24.

The X electrode 20 is formed in the direction crossing the Y electrode 12A and the Z electrode 12B. The partition wall 24 is formed in parallel with the X electrode 20 to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells.

The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

2 is a driving waveform diagram of a conventional plasma display panel. In the reset period, in order to erase the wall charges to a certain degree, an erase voltage is applied to the Z electrode, which is commonly bundled, and a ramp waveform voltage is applied to the Y electrode to initialize the cell state. At this time, wall charges are accumulated on the dielectrics of the front substrate and the rear substrate to be suitable for the address discharge at the last point of the falling ramp waveform.

The distribution of wall charges is influenced by the final voltage value of the ramp waveform. When the final voltage value is 0V, the wall charges accumulated in the dielectrics covering the Y electrode and the Z electrode on the front substrate are not sufficiently erased, which is not suitable for address discharge. Therefore, the final voltage applied to the Y electrode in the reset period is lowered to a negative voltage to sufficiently erase the wall charge. This waveform has the effect of widening the address voltage margin and shortening the address discharge.

3 is another driving waveform diagram of a conventional plasma display panel. Unlike the driving waveform shown in FIG. 2, the driving waveform shown in FIG. 3 has no erase period. In addition, the reset pulses above the second subfield, the third subfield, ...… have no ramp-up waveforms, and the peak voltage of the reset pulse is less than the peak voltage of the first reset pulse. Able to know.

As shown in FIG. 3, the driving waveform shown in FIG. 3 is formed by the type of charge accumulated in the dielectrics on the Y and Z electrodes of the turned-on cell when the sustain period is completed, and the ramp-up pulse shown in FIG. 2. The kinds of charges accumulated in the dielectrics on the Y electrode and the Z electrode are the same. In addition, the types of charges accumulated in the dielectrics on the Y and Z electrodes of the cell turned off during the sustain period and the types of charges accumulated in the dielectrics on the Y and Z electrodes of the cell by the ramp-up pulse shown in FIG. same. Rather, in the driving waveform shown in Fig. 3, since the charge of the turned-on cell is erased and the turned-off cell does not change its state, black luminance is reduced by not emitting light in the black state. Such driving waveforms form a very good image quality.

However, when such a driving waveform is applied to a plasma display panel having a high Xe content, the voltage of the reset pulse must be very high due to the increase of the Xe content and the panel margin is reduced when the large screen is applied. In addition, a plasma display panel having a high Xe content has a long address jitter and does not secure stable sustain in the sustain period.

4 is another driving waveform diagram of a conventional plasma display panel. Another conventional driving waveform shown in FIG. 4 is a waveform capable of reducing address jitter and stabilizing sustain discharge quickly by eliminating the problem of high address jitter and unstable sustain discharge, which is a problem of the driving waveform shown in FIG.

The driving waveform shown in FIG. 4 is the same as the conventional waveform shown in FIG. 3, but the waveform of the reset section operates in three stages unlike the conventional driving waveform. That is, it is set so that the discharge of surface discharge 2 and the opposite discharge may occur. In the case of the conventional waveform, when the address is set in the address period by resetting to the surface discharge No. 2, the address discharge generates a discharge in which both the surface discharge and the opposite discharge occur simultaneously.

In the reset period of the driving waveform shown in FIG. 4, the counter discharge is set to occur first in the address electrode to reduce the address jitter, and after the address, the wall charge is sufficiently accumulated in the upper dielectric layer, so that the sustain discharge is quickly stabilized in the sustain period. Have

5 is a driving waveform diagram of a conventional plasma display panel. An image is realized by sequentially applying scan voltages to the Y electrodes Y1 to Yn and applying a data voltage to an address section.

In the conventional driving waveform shown in FIG. 4, the voltage applied to the Y electrode in the reset period includes two lamp rising portions in which the voltage applied to the Z electrode rises after the lamp rises.

On the other hand, in the driving waveform shown in FIG. 5, only one voltage applied to the Y electrode exists and the voltage applied to the Z electrode is maintained at a constant voltage. At this time, since a voltage is required by the amount of reduction of the voltage applied to the Z electrode to cause the discharge, the voltage applied to the Y electrode is further lowered by the amount of reduction, causing a discharge between the Y electrode and the Z electrode.

That is, Vmy in the reset section of FIG. 4 is a positive voltage, but Vmy in the reset section of FIG. 5 is a negative voltage, and the voltage applied to the Z electrode is maintained at a constant voltage, so that the Y electrode and Z The voltage difference for generating a discharge between the electrodes is maintained. This driving waveform is simpler because the driving voltage is not required on the Z electrode side.

In addition, in the conventional driving waveform shown in FIG. 4, not only the Vmy voltage but also the Vrz voltage becomes a main variable, thereby determining the operating point. In addition, since the operating waveform of FIG. 5 determines only an operating point by changing only the voltage Vmy, an optimal driving voltage can be easily selected.

On the other hand, in the ramp falling section of the reset section, both the voltage applied to the Y electrode and the voltage applied to the Z electrode fall in the same manner as the conventional waveform shown in FIG. 4, but since the Vmy value is lower than the conventional one, the -Vny value is as much as Vmy is lower. Lowers.

In the conventional driving waveform of FIG. 4, the final wall voltage difference between the Y electrode and the Z electrode just before the address period is almost 0 V, and the wall voltage difference between the X electrode and the Y electrode is about half of the sustain voltage.

In the driving waveform of FIG. 5, since the voltage applied to the Y electrode is further lowered to a negative voltage, the wall voltage difference between the Y electrode and the Z electrode is almost close to 0 V as in FIG. 4, and the wall voltage difference between the X electrode and the Y electrode is also 0 V. FIG. Come close. Therefore, since the wall voltage difference is adjusted to 0V as a whole, resistance to any fluctuation factor becomes strong, which is advantageous for mis-discharge or jitter.

On the other hand, the final cell voltage just before the address is the sum of the wall voltage and the applied voltage. As the wall voltage is close to 0V as described above, the final cell voltage mostly follows the final applied voltage of the Y electrode and the Z electrode. Therefore, since the Y electrode, the Z electrode, and the voltage are larger than the conventional driving waveform shown in FIG. 4, the Vz value of the address period may be lowered.

Next, the reset section at the second subfield or more in the driving waveform of FIG. 5 will be described.

As shown in FIG. 4, in the conventional driving waveform, after the sustain voltage is finally applied to the Y electrode in the sustain period, an erase pulse is applied to the Z electrode in the erase period, and then the voltage is again applied to the Y electrode in the reset period of the next subfield. Initialization is done by applying.

The driving waveform of FIG. 5 has no separate erasing section, and the erase voltage Ve applied to the Z electrode and the voltage Vz of the reset section are combined, and the Y electrode has a waveform falling immediately without a ramp rising section.

When the cell is turned on in the previous subfield, the erasing is performed by the Ve voltage of the Z electrode. When the cell is turned off in the previous subfield, the reset process is performed without erasing. Even when the reset voltage is applied to the turned-off cell, since the discharge is not generated because it is the same as the previous reset voltage, the wall charge state is maintained.

Since there is no light emission in the reset process of this section, light emission only occurs in the first subfield of the entire subfield.

Unlike the voltage waveform applied to the Z electrode of the first subfield, the driving waveform applied to the Z electrode in the reset process of this section erases wall charges of the turned-on cell due to the voltage Ve applied to the Z electrode. The voltage drops to Vz and then ramps down to 0V.

The reason for doing this is to induce a counter discharge by lowering the voltage applied to the Z electrode in order to suppress the surface discharge occurs in the ramp falling section of the voltage applied to the Y electrode if it immediately falls from the Ve voltage.

Therefore, the driving waveform shown in FIG. 4 has a disadvantage in that black luminance is high because a reset waveform having a high voltage is used in all subfields as in the driving waveform shown in FIG. 2, and a rising voltage is applied to the Z electrode in the reset period. The problem arises that must be added.

FIG. 5 is a waveform improved from the application of a high lamp voltage to the sustain electrode, which was pointed out as a problem in the waveform of FIG. 4.

At this time, the waveform applied to the scan electrode and the sustain electrode after the second sustain pulse is mainly used to erase the positive wall charge when controlling the wall voltage. Since the wall charges remain in the scan electrodes much, the erase is not uniform due to the falling ramp voltage applied to the scan electrodes during the reset period. have.

The present invention is to solve the above problems, lowering the black brightness to increase the contrast ratio, reduce the address jitter to enable a single scan (single-scan) as well as wider the drive margin wall SUMMARY OF THE INVENTION An object of the present invention is to provide a method of driving a plasma display panel that is easy to control charge.

In order to achieve the above object, a method of driving a plasma display panel according to an embodiment of the present invention is a plasma display in which gray levels are expressed by a combination of subfields in which voltages are applied to X, Y, and Z electrodes in a reset period, an address period, and a sustain period. A method of driving a panel, comprising: a first step of ramping a voltage on the Y electrode during a reset period including a second subfield; A second step in which the voltage drops in the first step; In the second step, a voltage is applied to the third step in which the voltage decreases, and a voltage that is kept constant is applied to the Z electrode during the second step, and then a voltage falling in a predetermined slope is applied during the third step. It is characterized by.
The second step is characterized in that the voltage applied to the Y electrode is lowered from the ground level.

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The ramp rising voltage applied to the Y electrode in the first step is increased to the sustain voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a driving waveform diagram of a method of driving a plasma display panel according to an embodiment of the present invention.

The scan voltage is sequentially applied to the scan side and the data voltage is applied to the address section to implement the image.

7 is a driving waveform diagram in the driving method of the plasma display panel according to another exemplary embodiment of the present invention.

The difference between FIG. 6 and FIG. 7 is that the scan voltage of the reset section after the second subfield is set to the zero potential in FIG. 6 after the reset section (1). On the other hand, in Fig. 7, the potential is Vs. As described above, the operation of the two methods shows no difference in principle but only the method of implementing the waveform.

Referring to FIGS. 6 and 7, the first step is a period in which the voltage of the Y electrode ramps up to the first voltage Vs in the reset period after including the second subfield, and the second step is the first step. The third voltage Vmy falls from the first voltage Vs to the third voltage Vmy through the second voltage 0V, and the third step falls from the third voltage Vmy to the fourth voltage -Vny. Meanwhile, as shown in FIG. 7, the second step may drop from 0V (ground voltage) to the third voltage Vmy.

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In the fourth step, the voltage of the Z electrode maintains the fifth voltage (0 V) during the first step, and the fifth step of the second electrode maintains the sixth voltage Vs during the second step. In the sixth step, the voltage of the Z electrode ramps down the fifth voltage during the third step.

And the second voltage and the fifth voltage are 0V.

In the reset period of the second subfield, the first voltage Vs is a sustain voltage.

The operating point is determined by the potential difference between the third voltage Vmy and the sixth voltage Vs.

In the present invention, it is important to maintain the third voltage Vmy at a time when the sustain voltage falls in the erase period 3 in the reset period after the second subfield at a constant value. Maintaining this voltage almost equal to the voltage of the third voltage Vmy in the reset period of the first subfield, that is, determining the operating point by the third voltage is an important operation in the waveform to be implemented in the present invention. It becomes a principle.

The operation principle of the present invention of FIG. 6 is the same as or similar to that of FIG. 5. The operation of the first subfield is similar to the conventional invention in FIG. 5, and the ramp rise is only one Y voltage and the Z voltage is maintained at a constant voltage. At this time, since the voltage is required as much as the Z voltage is decreased to cause the discharge, the Y voltage is further lowered by this decrease to cause the Y-Z discharge. This eliminates the need for a ramp voltage on the Z side, which is very advantageous in circuit. This section is very important for the principle of the three-stage reset waveform of the present invention. In the conventional waveform of FIG. 4, not only the Vrz voltage but also the Vmy voltage becomes a variable to determine the operating point of the waveform. In the reset waveform, the Z voltage is maintained and only the Vmy voltage is changed to determine the operating point of the waveform. Thus, the optimum driving voltage can be easily adjusted.

On the other hand, in the ramp falling section, both Y and Z voltages fall in the same manner as the conventional waveform of FIG. 5, but since the Vmy value is lower than the conventional waveform, the -Vny value becomes lower as Vmy is lowered. This operation will be described because two things are different from the prior art.

First, in the conventional waveform of FIG. 4, the final wall voltage state just before the address has a wall voltage difference between Y and Z close to 0 V, and a wall voltage difference between X and Y has about half of the sustain voltage. However, in the present invention, since the Y voltage is lowered more negatively than before, the wall voltage difference between Y and Z is almost close to 0V, and the wall voltage difference between X and Y is also close to 0V as in the prior art. Therefore, since the wall voltage difference is adjusted to 0V as a whole, the resistance to any fluctuation factor becomes strong, which acts in favor of mis-discharge or jitter.

Since the final cell voltage state just before the second address is wall voltage + applied voltage, the wall voltage is almost 0V, so most of them follow the final applied voltage of Y and Z. Therefore, since the voltage between Y and Z is larger than that of the conventional waveform of FIG. 4, the Vz value of the address period may be lowered.

Next, a reset section above the second subfield of the present invention will be described. In FIG. 5, there is no erasure section separately, the erase voltage of the Z electrode and the voltage of the reset section are combined, and the Y electrode is set as a waveform which immediately descends without a ramp rising section. It is.

 In the present invention, the erase period is not applied to the sustain electrode but is applied to the scan electrode, so that the reset period after the second subfield is set as shown in FIGS. 6 and 7 as shown in FIGS. 2), (3) is formed in three steps to control the wall charge.

FIG. 8 is a wall charge distribution diagram of the second subfield reset section according to the conventional driving waveform shown in FIG. 5.

 FIG. 9 illustrates wall charge distribution by wall charge control in a second subfield reset section in the waveform of the present invention of FIGS. 6 and 7.

In the driving waveform according to the present invention, the wall charge inversion is sufficiently generated by the sufficient wall charge erasure in the erasing section (1) of FIG. 9, and the wall charge is disposed on the discharge gap side as shown in the wall charge distribution (c). It operates so that no transition occurs.

8 and 9, the distribution of the wall charges in the second subfield reset section will be described below.

First, FIG. 8 shows six negative charges on the Y electrode and four positive charges on the Z electrode in the section (1). Here, the Y electrode is maintained at 0V and the voltage of the Z electrode rises. As a result, three negative charges of the Y electrode become three positive charges of the Z electrode and erase discharge. As a result, three negative charges remain on the Y electrode, and one positive charge is positioned at a point far from the Y electrode.

The reason why one positive charge is far from the Y electrode is that when the voltage rises on the Z electrode and the erase discharge occurs, the positive charge is placed on the Z electrode, and the erase discharge occurs in sequence without the negative charge and the movement of the electric field formed in the discharge gap. The positive charges close to and are erased first, so that the remaining positive charges are located far from the discharge gap.

As a result, in the step (d), the wall charge is located outside the discharge gap, so that the discharge time is long and the discharge may occur due to insufficient erasure in the erase section 1.

9 is a wall charge distribution diagram of the second subfield reset section of the present invention, in which section (1) includes four positive charges on the Y electrode and six negative charges on the Z electrode. Here, the voltage of the Y electrode is increased and the voltage of the Z electrode is maintained at 0V. As a result, the three positive charges of the Y electrode become three negative charges and the erase discharge of the Z electrode, and the charges of the Y electrode and the Z electrode are replaced with each other. As a result, three negative charges remain on the Y electrode and one positive charge is positioned near the Y electrode on the Z electrode.

The reason why one positive charge is close to the Y electrode is that when the voltage rises on the Y electrode and the erasure discharge occurs, the positive charge on the Y electrode moves to the negative charge on the Z electrode, and the erase discharge occurs. The positive charges are located near the discharge gap where the electric field of the discharge gap is strong due to the displacement.

As a result, in step (d), the wall charge is located inside the discharge gap, the discharge time is shortened, and sufficient erasing is performed in the erasing section 1, so that no erroneous discharge occurs.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

 As described above, the present invention comprises three ramp waveforms of the reset section and adjusts the Z electrode voltage of the address section to increase the contrast ratio by reducing the black brightness, reduce the address jitter, and enable a single scan. As well as widening, it is possible to obtain the effect of easy to control the wall charge.

Claims (4)

A driving method of a plasma display panel in which gray levels are expressed by a combination of subfields in which voltage is applied to the X electrode, the Y electrode, and the Z electrode in the reset period, the address period, and the sustain period, In the subsequent reset interval including the second subfield, A first step in which a voltage rises to the Y electrode; A second step in which the voltage drops in the first step; In the second step, the voltage is applied to the third step of decreasing the voltage, And a voltage which is kept constant during the second step is applied to the Z electrode during the third step. The method of claim 1, And in the second step, the voltage applied to the Y electrode is lowered from the ground level. delete The method of claim 1, And a ramp rising voltage applied to the Y electrode in the first step rises to a sustain voltage.

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