KR20020090739A - Reset Driving Apparatus of Plasma Display Panel - Google Patents

Abstract

PURPOSE: A reset driving unit of a plasma display panel(PDP) is provided which has a simple circuit configuration using a constant voltage source to supply a bias voltage to a scan electrode during a reset period. CONSTITUTION: A sustain driving part(40) supplies a reference voltage to a scan electrode(12Y) during a reset period, and a ramp waveform supply part(45) supplies a rising ramp wave and a falling ramp wave to the above scan electrode. And a constant voltage source(ZDb) is installed between a base voltage source(GND) and the above ramp waveform supply part and supplies a constant DC voltage higher than a ground voltage to the above scan electrode after the falling ramp wave is supplied. The constant voltage source is a zener diode, and a rating voltage of the zener diode is in the range of 15V-25V according to a panel size.

Description

Reset Driving Apparatus for Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a reset driving apparatus of a plasma display panel which can simplify the circuit of the reset driving apparatus by using a constant voltage source to supply a predetermined bias voltage to the scan electrodes in the reset period. .

Recently, a liquid crystal display (hereinafter referred to as "LCD"), a field emission display (hereinafter referred to as "FED") and a plasma display panel (hereinafter referred to as "PDP") Flat display devices such as the like have been actively developed. The PDP emits a phosphor by 147 nm ultraviolet rays generated when the He + Xe or Ne + Xe inert mixed gas is discharged, thereby displaying an image including characters or graphics. Such a PDP is not only thin and large in size, but also simple in structure, and has a high luminance and high luminous efficiency as compared to other flat display devices. Due to these advantages, research on PDP is being actively conducted.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP includes scan electrodes 12Y and sustain electrodes 12Z formed on an upper substrate 10, and data formed on a lower substrate 18. An electrode 20X is provided.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases discharge efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the data electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The data electrode 20X is formed in the direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the data electrode 20X to prevent ultraviolet rays and visible rays generated by the discharge from leaking to the adjacent discharge cells.

The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cell provided between the upper substrate 10, the lower substrate 18, and the partition wall 24.

The PDP cell of this structure is selected by the counter discharge between the data electrode 20X and the scan electrode 12Y, and then maintains the discharge by the surface discharge between the scan electrode 12Y and the sustain electrode 12Z. In the PDP cell, the fluorescent material 26 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted outside the cell. As a result, the PDP having cells displays an image. In this case, the PDP implements a gray scale required for displaying an image by adjusting the discharge sustain period of the cell, that is, the number of sustain discharges, according to the video data.

The three-electrode AC surface discharge type PDP is driven by dividing the number of emission of one frame into several subfields to realize gray level of an image.

Each subfield is further divided into a reset period for generating discharge uniformly, and a sustain period for implementing gradation according to an address period for selecting a discharge cell and the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. In addition, each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased. In this way, since the sustain period is different in each subfield, gray levels of an image can be realized.

2 to 3C illustrate a process in which wall charges are generated by driving waveforms and driving waveforms supplied to a three-electrode AC surface discharge type PDP as shown in FIG. 1 in one subfield.

Referring to FIG. 2, during the reset period, the rising ramp waveform ramp1 and the falling ramp waveform ramp2 are continuously supplied to the scan electrode 12Y.

In the period (a) where the rising ramp waveform ramp1 is supplied, a weak discharge is generated between the scan electrode 12Y and the sustain electrode 12Z, as shown in FIG. 3A, on the scan electrode 12Y and the sustain electrode 12Z. Wall charges are accumulated in the upper dielectric layer 14. At this time, if the ramp voltage is gradually increased, the amount of wall charge increases. Subsequently, during the period (b) in which the falling ramp waveform ramp2 is supplied and the predetermined voltage Va is supplied to the sustain electrode 12Z, an appropriate amount of wall charges in the cell is erased to sufficiently secure an operating margin of the driving apparatus. . In this case, the wall charge may be reduced by gradually lowering the falling ramp voltage ramp2 to the ground potential GND. In the period (c) of FIG. 2, as shown in FIG. 3C, a predetermined amount of wall charges exist in the discharge space to prepare for the address period.

In this way, by supplying the ramp waveform to the scan electrode 12Y in the reset period, the visible light accompanying the discharge in the reset period, which is the non-display period, is reduced as much as possible to improve the contrast ratio and to provide uniform wall charge throughout the panel. The drive voltage required for address discharge is reduced.

In the address period, the positive data pulse data is supplied to the data electrodes 20X, and the negative scan pulse V_scan is sequentially supplied to the scan electrode Y in synchronization with the data pulse data. . Then, the cell to which the data pulse is supplied generates an address discharge by adding the voltage corresponding to the voltage difference between the data pulse and the scan pulse V_scan and the internal wall voltage accumulated by the wall charge in the cell. .

In the sustain period, sustain pulses SUSP are alternately supplied to the scan electrodes 12Y and the sustain electrodes 12Z. Then, the cells selected by the address discharge cause sustain discharge upon every sustain pulse SUPS supply. After all of the sustain discharges according to the luminance relative ratios occur, a small erase signal EP in the form of a ramp wave is supplied to the common sustain electrode 12Z to erase all wall charges inside the cell.

In this way, wall charges are generated in all cells using the rising ramp waveform ramp1 in the reset period, and then the falling ramp waveform ramp2 is supplied to reduce wall charges excessively generated in all cells. At this time, the falling ramp waveform ramp2 is maintained at the ground potential GND for a predetermined period so that a predetermined amount of wall charge exists in all cells to prepare for the address discharge.

In this manner, wall charges are generated in all cells by the reset period, thereby lowering the driving voltage of the data pulses supplied from subsequent address discharges.

4 to 5b illustrate a process of generating wall charges by driving waveforms and driving waveforms supplied to scan electrodes of a three-electrode AC surface discharge type PDP for lowering a driving voltage of a conventional data pulse.

Referring to FIG. 4, during the reset period, the rising ramp waveform and the falling ramp waveform are continuously supplied to the scan electrode 12Y.

In the period (a) where the rising ramp waveform ramp1 is supplied, a weak discharge is generated between the scan electrode 12Y and the sustain electrode 12Z, as shown in FIG. 5A, on the scan electrode 12Y and the sustain electrode 12Z. Wall charges are accumulated in the upper dielectric layer 14. At this time, if the ramp voltage is gradually increased, a high voltage is supplied to discharge all cells without a data voltage, thereby increasing the amount of wall charge. This results in a cell with the most wall charges in all the cells.

Subsequently, during the period (b) during which the falling ramp waveform ramp2 is supplied and the predetermined voltage Va is supplied to the sustain electrode 12Z, the wall circuit generated excessively in the cell is erased by an appropriate amount to reduce the operating margin of the driving circuit. Make sure you have enough. At this time, the period in which the falling ramp voltage ramp2 gradually falls to the predetermined bias voltage Vb and is maintained for a predetermined period is the amount by which wall charges accumulated excessively by the rising and falling ramp waveforms ramp1 and ramp2 decrease. It will be adjusted as shown in Figure 5b. This makes it possible to adjust the amount of wall charge in the period (b) during which the falling ramp waveform ramp2 is supplied to the bias voltage Vb. This bias voltage Vb has a voltage of 10-25V normally.

6 is a circuit diagram illustrating a reset driver of a conventional plasma display panel.

Referring to FIG. 6, a conventional reset driver includes a sustain driver 30 and a falling ramp waveform supply 35 connected in parallel to the scan electrode 12Y, and a falling ramp waveform supply 35 and a base voltage source GND. And a bias voltage source (Vs) provided at.

The sustain driver 30 supplies a sustain reference voltage to the panel. The panel is equivalently referred to as "panel capacitor Cp" hereafter.

The falling ramp waveform supply unit 35 further includes a switch Q1 for switching by a control signal input from the falling ramp waveform input line Set_down.

The switch Q1 receives a control signal from the falling ramp waveform input line Set_down and is turned on in a period in which the falling ramp waveform is supplied. The switch Q1 further includes a capacitor Cd and a resistor Rd connected in series between the gate terminal and the drain terminal.

The capacitor Cd and the resistor Rd serve to supply a falling ramp waveform that decreases to a predetermined slope after the sustain reference voltage is supplied from the sustain supply unit 30. The slope of this falling ramp waveform is determined by the RC time constant values of the capacitor Cd and the resistor Rd.

The bias voltage source Vs serves to maintain the falling ramp waveform at the predetermined bias voltage to fall to the ground potential GND. At this time, the bias voltage source (Vs) is provided with a bias capacitor (Cb) in parallel to remove and stabilize the noise of the output bias voltage. The stabilized positive DC bias voltage Vb by the bias capacitor Cb is supplied to the scan electrode 12Y through the switch Q1.

In the reset period, after the rising ramp waveform ramp1 is supplied from the rising ramp waveform supply unit (not shown) as shown in FIG. Thereafter, the rising ramp waveform ramp2 is supplied from the sustain driver 30 to the sustain reference voltage Vsus to drop to the sustain reference voltage Vsus. Accordingly, the wall ramp generated excessively in all the cells in the rising ramp waveform ramp1 is supplied to the falling ramp waveform ramp2 to reduce the predetermined amount.

The falling ramp waveform ramp2 is decreased by a predetermined slope in the sustain reference voltage Vsus by the RC time constant values of the capacitor Cd and the resistor Rd. At this time, the falling ramp waveform ramp2 drops to the positive DC bias voltage Vb supplied from the bias voltage source Vs and is maintained for the remaining reset period.

As described above, since the falling ramp waveform ramp2 does not fall to the ground potential GND but falls to the positive DC bias voltage Vbias, the voltage level thereof becomes smaller than the rising ramp waveform ramp1. The falling ramp waveform (ramp2) eliminates the minimum wall charge unnecessary for the address discharge. In other words, since the voltage level of the falling ramp waveform ramp2 is as small as the DC bias voltage Vb, the wall charges erased by that amount become smaller, so that the wall voltage in the cell prior to the address discharge has a smaller amount of wall charge remaining in the cell than before. It increases because it increases. As a result, the driving voltage of the low data pulse supplied in the address period can be reduced.

However, a bias voltage source for maintaining the lowest voltage of the falling ramp waveform ramp2 to a predetermined bias voltage and a capacitor for removing noise and stabilizing the bias voltage must be additionally installed. Accordingly, a problem arises in that circuit components increase.

Accordingly, an object of the present invention is to provide a reset driving apparatus for a plasma display panel which can simplify the circuit of the reset driving apparatus by using a constant voltage source to supply a predetermined bias voltage to the scan electrodes in the reset period.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.

2 is a driving waveform diagram for driving a conventional three-electrode alternating current PDP.

3A to 3C are views illustrating a wall charge generation process according to the reset period shown in FIG.

4 is a drive waveform diagram showing a reset waveform supplied with a conventional bias voltage;

5A and 5B illustrate a process of generating wall charges according to a driving waveform shown in FIG. 4.

6 is a circuit diagram showing a conventional reset driver.

7 is a circuit diagram showing a reset driver according to the present invention.

FIG. 8 is a waveform diagram showing a drive waveform supplied from a reset driver shown in FIG.

<Explanation of symbols for main parts of drawing>

10: upper substrate 12Y: scanning electrode

12Z: Sustain electrode 14: Upper dielectric layer

16: protective film 18: lower substrate

20X: Data electrode 22: Lower dielectric layer

24: partition 26: phosphor

30, 40: sustain drive unit 35, 45: falling ramp waveform drive unit

In order to achieve the above object, the reset driving apparatus of the plasma display panel according to the present invention includes a sustain driver for supplying a reference voltage to the scan electrodes in the reset period, and a lamp for supplying the rising ramp waveform and the falling ramp waveform to the scan electrodes. And a constant voltage source provided between the waveform supply unit and the base voltage source and the ramp waveform supply unit to supply a DC constant voltage higher than the ground voltage to the scan electrode after the falling ramp waveform is supplied.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 and 8.

7 and 8, the plasma display panel reset driving apparatus according to the present invention includes a sustain driver 40 and a falling ramp waveform supply 45 connected in parallel to the scan electrode 12Y, and a falling ramp waveform supply ( 45) and a constant voltage source ZDb provided between the base voltage source GND.

The sustain driver 40 supplies a sustain voltage to the panel. The panel is equivalently referred to as "panel capacitor Cp" hereafter.

The falling ramp waveform supply unit 45 further includes a switch Q1 that is switched by a control signal input from the falling ramp waveform input line Set_down.

The switch Q1 receives a control signal from the falling ramp waveform input line Set_down and is turned on in a period in which the falling ramp waveform is supplied. The switch Q1 further includes a capacitor Cd and a resistor Rd connected in series between the gate terminal and the drain terminal.

The capacitor Cd and the resistor Rd supply a falling ramp waveform ramp2 that decreases with a predetermined slope after the sustain reference voltage Vsus is supplied from the sustain supply unit 30. The slope of this falling ramp waveform is determined by the RC time constant values of the capacitor Cd and the resistor Rd.

The constant voltage source ZDb serves to maintain the lowest voltage of the falling ramp waveform ramp2 falling to the ground potential GND at a predetermined positive DC bias voltage Vb. Normally, the positive DC bias voltage Vb has a voltage in the range of 10V to 25V. Accordingly, the constant voltage source ZDb uses the general purpose zener diode ZDb of 15V to 25V depending on the size of the panel.

Zener diode ZDb keeps the voltage across the diode almost constant over a range of reverse current values. This causes the high falling ramp waveform ramp2 to gradually decrease due to the RC time constant values of the capacitor Cd and the resistor Rd. At this time, the zener diode ZDb operates according to its rated voltage. The zener diode ZDb having a rated voltage of 15V does not operate until the voltage of the falling ramp waveform decreases to 15V, and operates when the voltage of the falling ramp waveform ramp2 is 15V. Accordingly, the falling ramp waveform ramp2 maintains a voltage of 15 V supplied from the zener diode ZDb.

In this manner, in the reset period, the rising ramp waveform ramp1 is supplied from the rising ramp waveform supply unit (not shown) to rise to the reset voltage Vreset, and then reset discharge occurs. Thereafter, the rising ramp waveform ramp2 is supplied from the sustain driver 40 to the sustain reference voltage Vsus to fall to the sustain reference voltage Vsus.

The wall charge generated excessively in all the cells in the rising ramp waveform ramp1 is reduced by a predetermined amount by supplying a predetermined voltage Va to the falling ramp waveform ramp2 and the sustain electrode 12Z. The falling ramp waveform ramp2 falls to have a predetermined slope at the sustain voltage Vsus by the RC time constant values of the capacitor Cd and the resistor Rd. At this time, the falling ramp waveform ramp2 falls to the constant voltage Vb supplied from the constant voltage source ZDb and is maintained for the remaining reset period.

In this manner, by using the zener diode ZDb, the falling ramp waveform ramp2 is maintained at the constant voltage Vb rather than the ground potential GND, thereby preventing the wall charges in the cell from being excessively erased. Accordingly, the data pulse data supplied in the address period can be lowered by the constant voltage Vb.

As described above, the reset driving apparatus of the plasma display panel according to the present invention has an advantage of simplifying the structure of the reset driving apparatus by using a zener diode to supply a predetermined bias voltage to the scan electrodes in the reset period. As a result, the part cost is reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (3)

A sustain driver for supplying a reference voltage to the scan electrodes in the reset period; A ramp waveform supply unit for supplying a ramp ramp waveform and a ramp ramp waveform to the scan electrode; And a constant voltage source provided between a base voltage source and the ramp waveform supply unit to supply a DC constant voltage higher than a ground voltage to the scan electrode after the falling ramp waveform is supplied. The method of claim 1, And the constant voltage source is a zener diode. The method of claim 2, And a rated voltage of the zener diode is set within a range of 15V to 25V depending on the size of the panel.