KR100493917B1 - Method of driving plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a selective erasing plasma display panel to supply a reset voltage higher than the sustain voltage.

In the method of driving a selective erasing plasma display panel according to an embodiment of the present invention, a negative scan voltage lower than a base voltage is supplied to one of a plurality of scan electrodes during an address period, and the negative polarity during an address period. A scan pulse having a positive polarity higher than the base voltage is supplied to the remaining electrodes except for the electrode to which the scan voltage is supplied, and a sustain pulse having a sustain voltage higher than the positive scan voltage at the scan electrode and the sustain electrode during the sustain period. Is alternately supplied, and a ramp pulse is supplied to the scan electrode which increases from the positive scan voltage value to a value equal to or lower than the scan voltage value plus the sustain voltage during the reset period. .

Description

Driving method of plasma display panel {METHOD OF DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of driving a selective erasing type plasma display panel to supply a reset voltage higher than a sustain voltage.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of inert mixed gases such as He + Xe, Ne + Xe and He + Ne + Xe. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view illustrating a discharge cell structure typically arranged in an alternating-type PDP in a matrix form, and FIG. 2 is a cross-sectional view of the discharge cell shown in FIG. 1.

1 and 2, the discharge cells of the three-electrode AC surface discharge type PDP are formed on the scan electrode Y and the sustain electrode Z formed on the upper substrate 10, and the lower substrate 18. The address electrode X is provided. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrode 13Y is formed at one edge region of the transparent electrode. , 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (hereinafter, referred to as “ITO”). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, and He + Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed in 256 gray levels as shown in FIG. 3, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. In addition, each of the eight subfields SF1 to SF8 is divided into a reset and an address period and a sustain period. Here, the reset and address periods of each subfield are the same for each subfield, while the sustain period increases at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. do. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

3, the first subfield SF1 sustains discharge cells other than the discharge cells selected by the reset period, the address period for turning off the selected discharge cell, and the address discharge. It is divided into sustain periods. The second to eighth subfields SF2 to SF8 are address periods for turning off selected discharge cells without a full writing period (reset period) in which the full screen is lit, and discharge cells selected by address discharge. The cells are divided into sustain periods for sustain discharge of discharge cells other than these.

Such a PDP is roughly classified into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted up by the address discharge in the address period. First, the selective write driving method turns off the full screen in the reset period, and then turns on the selected discharge cells in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge.

4 is a diagram illustrating a driving waveform according to the PDP driving method illustrated in FIG. 3.

Referring to FIG. 4, the first subfield SF1 included in one frame of the conventional PDP is divided into a reset period RPD, an address period APD, and a sustain period SPD.

During the reset period RPD, all discharge cells in the PDP cause a reset discharge to turn on the discharge cells. In the address period APD, the discharge cells turned on in the reset period RPD are selectively turned off. In the sustain period SPD, sustain discharge is caused in discharge cells not selected in the address period APD.

The reset period RPD is divided into a lamp pulse supply period RPD1 for supplying a lamp pulse to the scan electrode Y and the sustain electrode Z and a pulse signal supply period RPD2 for supplying a pulse signal.

In the lamp pulse supply period RPD1, a positive pulse (+) lamp pulse RPy is supplied to the scan electrode Y, and a negative pulse pulse (RPz) is supplied to the sustain electrode Z. In addition, the ground potential GND is supplied to the address electrode X in the lamp pulse supply period RPD1. Here, the ramp pulse RPy of positive polarity (+) is set to the same voltage as the sustain voltage Vs. In addition, the ramp pulse RPz of negative polarity (-) is set to an absolute voltage higher than the sustain voltage Vs. As described above, the positive polarity (+) lamp pulse (RPy) is supplied to the scan electrode (Y) during the lamp pulse supply period (RPD1), and the negative (+) lamp pulse (RPz) is supplied to the sustain electrode (Z). In this case, the reset discharge is generated in all the discharge cells by the voltage difference between the scan electrode Y and the sustain electrode Z. Therefore, a negative wall charge is formed on the scan electrode Y to which the positive positive pulse pulse RPy is supplied, and a sustain electrode to which the negative pulse pulse RPz is supplied. (Z) forms positive wall charges.

In the pulse signal supply period RPD2, the second stabilization pulse Pz is supplied to the sustain electrode Z, and the first stabilization pulse Py is supplied to the scan electrode Y alternately. At this time, the voltage values of the first stabilization pulse Py and the second stabilization pulse Pz are set equal to the sustain voltage Vs. Therefore, stabilization discharge occurs between the scan electrode Y and the sustain electrode Z due to the difference in the sustain voltage Vs between the scan electrode Y and the sustain electrode Z, thereby forming uniform wall charge in all the discharge cells. (I.e., the discharge cells are turned on).

In the address period APD, scan pulses SP are sequentially supplied to the scan lines Y to the negative scan voltage −Vy, and scan pulses SP are applied to the address electrodes X. Is supplied to the data pulse DP that is synchronized. At this time, in the discharge cells supplied with the data pulse DP, an address discharge, that is, an erase discharge occurs, and the discharge cells are turned off.

In the sustain period SPD, sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. When a sustain pulse is supplied to the scan electrodes Y and the sustain electrodes Z, sustain discharge is generated in discharge cells that are not selected in the address period APD. In this case, the gray level value corresponding to the luminance weight is expressed by adjusting the number of sustain discharges.

Meanwhile, the remaining subfields except the first subfield do not include the reset period RPD. In other words, the remaining subfields repeat the address period APD and the sustain period SPD and express luminance according to the gray scale value. In detail, in the first subfield, all the discharge cells are turned on during the reset period RPD in order to drive the PDP in the selective erasing method. Thereafter, in the remaining subfields except for the first subfield, the gray level value is selectively turned off while selectively turning off the discharge cells turned on during the reset period (RPD) of the first subfield. Express.

FIG. 5 is a diagram illustrating a driving circuit of a scan driver of a selective erasure type PDP for generating a driving waveform of FIG. 4.

Referring to FIG. 4, the scan driver of the selective erasing PDP according to the conventional method is a sustainer 41, an integrated circuit (hereinafter referred to as an “IC”) 42, a setup supply unit 43, and a scan reference. And a voltage supply part 44 and a scan voltage supply part 45.

The sustainer 41 supplies the sustain voltage Vs and the ground voltage GND to the scan electrode Y during the sustain period SPD.

The scan IC 42 includes the fifth and sixth diodes D5 and D6 which are internal diodes of the fifth and sixth switches Q5 and Q6 and the fifth and sixth switches Q5 and Q6 connected in a push-pull form. It is provided. The fifth and sixth switches Q5 and Q6 selectively supply voltage signals to the scan electrode Y from the sustainer 41, the scan reference voltage supply unit 44, and the scan voltage supply unit 45.

The setup supply 43 is provided between the first switch Q1, the first switch Q1 and the scan reference voltage supply 44 connected between the setup voltage source Vsetup, the setup voltage source Vsetup and the sustainer 41. A connected second switch Q2 and first and second diodes D1 and D2 which are internal diodes of the first and second switches Q1 and Q2 are provided. The first and second switches Q1 and Q2 serve to supply a setup waveform to the scan electrode Y during the reset period.

The scan reference voltage supply 44 has a seventh switch Q7 connected in series between the scan IC 42 and the scan voltage source (-Vy), and a seventh diode D7 which is an internal diode of the seventh switch Q7. do. The seventh switch Q7 is switched in response to the control signal supplied to the address period APD to supply the scan voltage −Vy to the scan IC 42.

The scan voltage supply part 45 is provided with the third and fourth switches Q3 and Q4 and the third and fourth switches Q3 and Q4 connected in series between the scan voltage source Vsc and the scan reference voltage supply part 44. Third and fourth diodes D3 and D4, which are internal diodes, and a first capacitor C1 connected between the scan voltage source Vsc and the scan reference voltage supply unit 44 are provided. The third switch Q3 is switched in response to the control signal supplied to the address period APD to supply the scan voltage Vsc to the scan IC 42. At this time, the first capacitor C1 connected between the scan voltage source Vsc and the scan reference voltage supply unit 44 charges the scan voltage from the scan voltage source Vsc. The fourth switch Q4 switches the scan voltage Vsc supplied to the scan IC 42 in response to the control signal.

Referring to the driving method of the PDP, the first and second switches Q1 and Q2 are ON, the third switch Q3 is OFF, and the fourth and fifth switches during the reset period RPD. Q4 and Q5 are ON, and the sixth and seventh switches Q6 and Q7 are OFF. At this time, the setup voltage Vsetup outputs a pulse in the form of a ramp pulse rising from the base potential GND to the setup voltage Vsetup by the variable resistor of the first switch Q1. The lamp pulse RP is supplied to the panel through the sixth diode D6, which is an internal diode of the sixth switch Q6, through the first and second switches Q1 and Q2.

However, the setup voltage Vsetup used in the related art has used a power supply such as the sustain voltage Vs in order not to configure a separate power supply. Therefore, even if a higher reset voltage Vreset is required to cause a reset discharge depending on the panel, it is impossible to raise the setup voltage Vsetup higher than the sustain voltage Vs, and thus the reset voltage Vreset cannot be increased.

Accordingly, an object of the present invention is to provide a method of driving a selective erasing plasma display panel to supply a reset voltage higher than the sustain voltage.

In order to achieve the above object, a method of driving a selective erasing plasma display panel according to an exemplary embodiment of the present invention may include supplying a negative scan voltage lower than a base voltage to any one of a plurality of scan electrodes during an address period; And supplying a positive scan voltage higher than the base voltage to the remaining electrodes except for the electrode to which the negative scan voltage is supplied during the address period, and higher than the positive scan voltage to the scan electrode and the sustain electrode during the sustain period. A sustain pulse having a sustain voltage value is alternately supplied, and a ramp pulse that increases from a positive scan voltage value to a value equal to or lower than the scan voltage value plus a sustain voltage value during a reset period; It includes the step of supplying.

The reset period may be included in at least one or more of the plurality of subfields.

The slope of the lamp pulse to select any voltage between a lamp pulse having a voltage value higher than the positive scan voltage to a lamp pulse having a voltage value equal to or lower than that of the sustain voltage and the positive scan voltage. It characterized in that to adjust.

An apparatus of a selective erasing plasma display panel according to an exemplary embodiment of the present invention includes a sustainer alternately supplying sustain pulses to scan electrodes and sustain electrodes during a sustain period, and a lamp having a voltage value of the sustain pulse during a reset period. A setup supply unit for supplying a pulse and a scan voltage supply unit for supplying a scan pulse having a scan voltage value lower than the sustain voltage for selecting a discharge cell to the scan electrode during an address period, the scan voltage supply unit for a reset period After the scan voltage is charged in the capacitor installed in the added to the sustain voltage, characterized in that the supply to the panel.

The scan voltage source for supplying the scan voltage is floated with the sustain voltage source for supplying the sustain voltage.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIG. 6.

The present invention generates a reset voltage (Vreset) to which the setup voltage (Vsetup) and the scan voltage (Vsc) are added during the reset period (RPD) using a conventional driving circuit. Therefore, the driving method of the plasma display panel according to the present invention will be described with reference to the conventional driving circuit shown in FIG. 5, and the first to third switches Q1 to Q3 are turned on during the reset period RPD. ), The fourth switch Q4 is OFF, the fifth switch Q5 is ON, and the sixth and seventh switches Q6 and Q7 are OFF. Since the first and second switches Q1 and Q2 are ON, the setup voltage Vsetup is supplied to the node A Sus_dn through the first and second switches Q1 and Q2. At this time, since the setup voltage Vsetup and the scan voltage Vsc are connected by the floating power supply unit, the setup voltage Vsetup and the scan voltage Vsc are supplied to the B node Sus_up only when a path is connected. Once the scan voltage Vsc is connected to the path by the floating power supply, the setup voltage Vsetup is tied to the floating power supply. The scan voltage Vsc is charged in the first capacitor C1. Thereafter, when the path of the floating power supply unit is connected to the setup voltage Vsetup, the setup voltage Vsetup is supplied to the B node Sus_up. At this time, the setup voltage Vsetup is added to the scan voltage Vsc charged in the first capacitor C1 and the voltage added with the setup voltage Vsetup and the scan voltage Vsc is applied to the B node Sus_up. This voltage is supplied to the driver IC 42 via the third switch Q3. That is, since the B node Sus_up always floats the A node Sus_dn to float by the scan voltage Vsc, the B node Sus_up is connected to the A node Sus_dn by the setup voltage Vsetup. ) Plus a scan voltage Vsc is supplied. The voltage added with the setup voltage Vsetup and the scan voltage Vsc is supplied to the panel through the third and fifth switches Q3 and Q5 of the driver IC 42. At this time, the setup voltage Vsetup adjusts the variable resistance of the first switch Q1 to output a pulse in the form of a ramp pulse rising from the base potential GND to the setup voltage Vsetup. Accordingly, the voltage supplied to the panel during the reset period RPD is a reset value obtained by adding the voltage value of the pulse of the pulse form of the ramp pulse rising from the base potential GND to the voltage value of the setup voltage source Vsetup and the voltage value of the scan voltage source Vsc. A reset pulse having a voltage value Vreset is supplied to the panel.

Here, the reset voltage value Vreset obtained by adding the voltage value of the setup voltage source Vsetup and the scan voltage source Vsc may be higher than necessary. This is because the scan voltage Vsc cannot be lowered arbitrarily. However, if the slope of the lamp pulse is adjusted by adjusting the variable resistance of the first switch Q1, the voltage corresponding to the final height of the lamp pulse can be adjusted. Therefore, the setup voltage Vsetup and the scan voltage Vsc are added. Voltage lower than the voltage value can be applied. In other words, the reset period (RPD) is fixed regularly, and if the slope of the ramp pulse is adjusted within this time, if the slope rises rapidly, it goes up to the set-up voltage (Vsetup) within a predetermined time, but if the slope is gentle The ramp pulse does not rise to the set-up voltage (Vsetup) because the voltage that can rise within the time is lost at a voltage lower than the setup voltage (Vsetup). By using this, it is possible to apply a lamp pulse corresponding to a voltage value higher than the scan voltage Vsc and to which the scan voltage Vsc is added to the setup voltage Vsetup.

6 is a diagram illustrating a driving waveform of the selective erasing PDP according to the present invention.

Referring to FIG. 6, the first subfield SF1 included in one frame of the selective erasing type PDP according to the present invention is driven by being divided into a reset period RPD, an address period APD, and a sustain period SPD.

During the reset period RPD, all discharge cells in the PDP cause a reset discharge to turn on the discharge cells. In the address period APD, the discharge cells turned on in the reset period RPD are selectively turned off. In the sustain period SPD, sustain discharge is caused in discharge cells not selected in the address period APD.

The reset period RPD is divided into a lamp pulse supply period RPD1 for supplying a lamp pulse to the scan electrode Y and the sustain electrode Z and a pulse signal supply period RPD2 for supplying a pulse signal.

In the pulse pulse supply period RPD1, the scan electrode Y is supplied with a positive polarity (+) lamp pulse RPy higher than the sustain voltage Vs plus the setup voltage Vsetup and the scan voltage Vsc. The lamp pulse RPz of negative polarity (−) is supplied to the electrode Z. In this manner, when the positive (+) ramp pulse RPy higher than the sustain voltage Vs is supplied to the scan electrode Y, and the negative (-) ramp pulse RPz is supplied to the sustain electrode Z, the scan is performed. The reset discharge is caused by the voltage difference between the electrode Y and the sustain electrode Z. At the same time, a weak counter discharge between the scan electrode Y and the address electrode X is also generated to form a positive wall voltage at the address electrode X. In detail, the scan electrode Y is supplied with a positive polarity (+) lamp pulse RPy to which the setup voltage Vsc higher than the sustain voltage Vs and the scan voltage Vsc are added, and the sustain electrode Z is supplied. ) Is supplied with a negative pulse pulse (RPz). At this time, the potential difference between the scan electrode Y and the address electrode X is set higher than the potential difference between the sustain electrode Z and the address electrode X. Therefore, a weak counter discharge is generated between the scan electrode Y and the address electrode X during the lamp pulse supply period RPD1, and positive wall charges are applied to the address electrode X by the counter discharge. Is formed. The positive wall charges accumulated on the address electrode X by the reset discharge assist in the address discharge during the address period APD. That is, when the wall charges are weakly accumulated on the address electrode X due to the reset discharge, the cells selected by the counter discharge between the scan electrode Y and the address electrode X may not be turned off during the address period APD. In other words, the cells selected during the address period APD should not be discharged. If the cells to be selected are not selected because the address discharge does not occur due to the lack of wall charge, the cells are defined as the cells to be discharged. Normal sustain discharge occurs, resulting in unstable discharge. Accordingly, by supplying a high reset voltage Vreset during the reset period RPD without a separate power supply for increasing the setup voltage Vsetup, sufficient wall charges are accumulated to secure an operation margin, thereby enabling a more stable address discharge. Compared with the prior art, the conventionally used setup voltage (Vsetup) has been using a power source such as the sustain voltage (Vs) in order not to configure a separate power supply. Therefore, even if a higher reset voltage is required depending on the panel, it is impossible to raise the setup voltage Vsetup higher than the sustain voltage Vs, thereby making it difficult to secure a sufficient operating margin.

In the pulse signal supply period RPD2, the second stabilization pulse Pz is supplied to the sustain electrode Z, and the first stabilization pulse Py is supplied to the scan electrode Y alternately. At this time, the voltage values of the first stabilization pulse Py and the second stabilization pulse Pz are set equal to the sustain voltage Vs. Therefore, stabilization discharge occurs between the scan electrode Y and the sustain electrode Z due to the difference in the sustain voltage Vs between the scan electrode Y and the sustain electrode Z, thereby forming uniform wall charge in all the discharge cells. (I.e., the discharge cells are turned on).

In the address period APD, scan pulses SP are sequentially supplied to the scan lines Y to the negative scan voltage (-Vy), and the negative electrodes (-) are applied to the address electrodes X. The data pulse DP of positive polarity (+) synchronized with the scan pulse SP of () is supplied. Here, since the positive wall charges are formed in the address electrode X during the reset period RPD, stable address discharge occurs when the positive data pulse DP is supplied. At this time, in the discharge cells supplied with the data pulse DP, an address discharge, that is, an erase discharge occurs, and the discharge cells are turned off.

In the sustain period SPD, sustain pulses are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. When a sustain pulse is supplied to the scan electrodes Y and the sustain electrodes Z, sustain discharge is generated in discharge cells that are not selected in the address period APD. In this case, the gray level value corresponding to the luminance weight is expressed by adjusting the number of sustain discharges.

Meanwhile, the remaining subfields except the first subfield do not include the reset period (RPD). In other words, the remaining subfields repeat the address period APD and the sustain period SPD and express luminance according to the gray scale value. In detail, in the first subfield, all the discharge cells are turned on during the reset period RPD in order to drive the PDP in the selective erasing method. Thereafter, in the remaining subfields except for the first subfield, the gray level value is selectively turned off while selectively turning off the discharge cells turned on during the reset period (RPD) of the first subfield. Express.

In other words, the reset voltage Vreset supplied during the reset period RPD of the conventional PDP used the voltage of the setup voltage source Vsetup. Since the setup voltage Vsetup uses the same voltage as the sustain voltage source Vs, a voltage higher than the sustain voltage Vs cannot be used. In addition, in order to control the setup voltage Vsetup to have a voltage higher than the sustain voltage Vs, a separate setup voltage source Vsetup was controlled. In such a case, a separate circuit was added to increase the cost. If the conventional driving circuit is used as it is without an additional additional circuit, it does not have a sufficiently high reset voltage (Vreset), it was difficult to secure the operating margin. Accordingly, in the present invention, a reset voltage Vreset higher than the sustain voltage Vs is supplied using a conventional circuit without additional circuit. That is, a voltage obtained by adding the sustain voltage Vs and the scan voltage Vsc without using a setup voltage source Vsetup is used as the reset voltage Vreset. The increased reset voltage Vreset generates a counter discharge between the scan electrode Y and the address electrode X better, so that sufficient wall charges are accumulated on the address electrode X. Accordingly, the operating margin can be secured by applying a reset voltage Vreset higher by improving the control method of the driving circuit without changing the circuit.

As described above, the driving method of the plasma display panel according to the present invention improves the driving method without changing the circuit so that sufficient wall charges are accumulated by applying a higher reset voltage plus the setup voltage and the scan voltage to the scan electrode during the reset period. It is possible to secure the operating margin.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a layout view of electrodes of the plasma display panel shown in FIG. 1.

3 is a diagram illustrating a frame structure of an 8-bit default code for implementing 256 gray levels.

FIG. 4 is a diagram illustrating a driving waveform according to the driving method of the plasma display panel shown in FIG. 3.

5 is a diagram illustrating a driving circuit of a scan driver of a selective erasing plasma display panel for generating a driving waveform of FIG. 4.

6 is a view showing a driving waveform of the selective erasing plasma display panel according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 18: lower substrate

Y: scan electrode Z: sustain electrode

X: address electrode 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14: upper dielectric layer

16: protective film 22: lower dielectric layer

24: partition 26: phosphor layer

41: energy recovery circuit 42: driver IC

43: setup supply unit 44: scan reference voltage supply unit

45: scan voltage supply

Claims (5)

Supplying a negative scan voltage lower than the base voltage to any one of the plurality of scan electrodes during the address period; Supplying a positive scan voltage higher than a base voltage to the remaining electrodes except for the electrode to which the negative scan voltage is supplied during the address period; Alternately supplying a sustain pulse having a sustain voltage value higher than the positive scan voltage to the scan electrode and the sustain electrode during the sustain period; And a ramp pulse that increases from the positive scan voltage value to a scan voltage value equal to or lower than the sustain voltage plus the sustain voltage during a reset period, is supplied to the scan electrode. How to drive the panel. The method of claim 1, And the reset period is included in at least one or more subfields among the plurality of subfields. The method of claim 1, The slope of the lamp pulse to select any voltage between a lamp pulse having a voltage value higher than the positive scan voltage to a lamp pulse having a voltage value equal to or lower than that of the sustain voltage and the positive scan voltage. Method of driving a selective erasing plasma display panel, characterized in that for adjusting. A sustainer for alternately supplying sustain pulses to the scan electrode and the sustain electrode during the sustain period; A setup supply unit for supplying a ramp pulse having the voltage value of the sustain pulse during a reset period; A scan voltage supply unit supplying a scan pulse having a scan voltage value lower than the sustain voltage for selecting a discharge cell to the scan electrode during an address period; And the scan voltage is charged to a capacitor installed in the scan voltage supply unit during the reset period, and then supplied to the panel while being added to the sustain voltage. The method of claim 4, wherein And a scan voltage source for supplying the scan voltage is floated with a sustain voltage source for supplying the sustain voltage.