KR100433233B1 - Method And Apparatus Of Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel to reduce a driving voltage and secure a driving margin of the plasma display panel.

A method of driving a plasma display panel according to the present invention is a method of driving a plasma display panel including a plurality of first and second sustain electrode lines and a plurality of address electrode lines, wherein a reset pulse is applied to the plurality of first sustain electrode lines. Causing the reset discharge to occur; controlling the voltages applied to the plurality of first and second sustain electrode lines and the plurality of address electrode lines so that address discharge of the subfields occurs; And a sustain discharge is generated between the plurality of first sustain electrode lines and the plurality of second sustain electrode lines having the sustain voltage of a high voltage by using a reset pulse of a predetermined interval having a rising slope.

The method and apparatus for driving a plasma display panel according to the present invention provide a sustain voltage driving margin by applying a high voltage first sustain pulse to a scan / sustain electrode line using a lamp pulse applied during setup of a reset period without additional circuitry. In addition, the sustain drive voltage can be lowered.

Description

Method and apparatus for driving plasma display panel {Method And Apparatus Of Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel for reducing a driving voltage and securing a driving margin of the plasma display panel.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of inert mixed gases such as He + Xe, Ne + Xe and Ne + Ne + Xe. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 30Y and a common sustain electrode 30Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The scan / sustain electrode 30Y and the common sustain electrode 30Z each have a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and are formed on one edge region of the transparent electrode. Electrodes 13Y and 13Z. The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (hereinafter, referred to as “ITO”). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, and Ne + Ne + Xe for discharging is injected into the discharge space of the discharge cell provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. In addition, each of the eight subfields SF1 to SF8 is divided into a reset and an address period and a sustain period. Here, the reset and address periods of each subfield are the same for each subfield, while the sustain period increases at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. do. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

Such a driving method of the PDP is roughly classified into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted by the address discharge in the address period. First, the selective write driving method turns off the full screen in the reset period, and then turns on the selected discharge cells in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge.

In the selective erasing driving method, the entire screen is turned on by writing discharge in the reset period, and then the selected discharge cells are turned off in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells not selected by the address discharge.

Since the selective erasing method is a discharge for removing wall charges in the cell, the scanning pulse width is narrower than that of the selective writing method, that is, the addressing time can be reduced. The drive waveform of the selective writing method reduces the contrast as the number of lamp pulses increases, so the quality of the driving waveform becomes weaker as it is used more. Accordingly, in the driving method of the PDP, as shown in FIG. 3, one frame is composed of the selective write subfields SF1 through SF6 and the selective erase subfields SF7 through SF12 to configure the selective write and erase method. Drive in parallel.

Referring to FIG. 3, in the method of driving a three-electrode alternating surface discharge PDP, one frame includes subfields SF1 through SF6 of selective writing and subfields SF7 through SF12 of selective erasing. The first subfield SF1 is divided into a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustaining discharge for the discharge cell selected by the address discharge, and an erasing period for canceling the sustain discharge. . Each of the second to fifth subfields SF2 to SF5 is divided into an optional write address period, a sustain period, and an erase period. The sixth subfield SF6 is divided into an optional write address period and a sustain period. In the first to sixth subfields SF1 to SF6, the selective write address period and the erase period are the same for each subfield, while the sustain period is 2n in each subfield (n = 0, 1, 2, 3, 4). Is increased by 5). The seventh through twelfth subfields SF7 through SF12 sustain sustain discharge of discharge cells other than the discharge cells selected by the address discharge and the selective erase address period for turning off the selected discharge cells without a full surface writing period in which the full screen is lit. Divided into periods. In the seventh to twelfth subfields SF7 to SF12, not only the selective erasure address period but also the sustain period are set equally. The sustain period of the seventh to twelfth subfields SF7 to SF12 is set to a luminance relative ratio of 25 to have the same luminance relative ratio as that of the sixth subfield SF6.

Each of the seventh to twelfth subfields SF7 to SF12 driven by the selective erasing method must have the previous subfield turned on to turn off unnecessary discharge cells whenever the subfields are consecutive. For example, in order for the seventh subfield SF7 to be turned on, the sixth subfield SF6 driven by the selective write method, which is the previous subfield, must be turned on. After the sixth subfield SF6 is turned on, the unnecessary discharge cells are turned off in the seventh to twelfth subfields SF7 to SF12. To this end, the cells turned on in the sixth subfield WSF, which is the last selective write subfield WSF, must be turned on by the sustain discharge in order for the selective erase subfield ESF to be used. Therefore, the seventh subfield SF7 does not need a separate writing discharge for the selective erase address. In addition, the eighth to twelfth subfields SF8 to SF12 also selectively turn off cells that are turned on in the previous subfield without front lighting.

4 is a diagram illustrating a driving waveform according to a general PDP driving method.

Referring to FIG. 4, a reset pulse RP of a ramp-up waveform is supplied to the scan / sustain electrode lines Y at a setup of the reset period, and a reset of the ramp-down waveform at set-down. Pulse (-RP) is supplied sequentially. At this time, the reset pulse (-RP) of the ramp-down waveform drops to the negative scan reference voltage (-Vy). Also, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period APD, while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z, each of the scan / sustain electrode lines Y and the address electrode lines X has a negative polarity (−). ) Scan pulse SP and positive polarity data pulse DP are supplied to be synchronized with each other. The address discharge is performed by the scan pulse SP and the data pulse DP as described above.

Then, in the sustain period SPD, the sustain pulses SUSPy and SSUPz alternate with the scan / sustain electrode lines Y and the common sustain electrode lines Z so that the sustain discharge occurs for the cell turned on by the address discharge. Supplied. At the end of the sustain period SPD, an erase pulse (not shown; EP) is supplied to the scan / sustain electrode lines Y to cause the sustain discharge to be erased.

5 schematically shows a driving apparatus of a general PDP.

Referring to FIG. 5, the PDP driving apparatus drives the Y driver 32 for driving the m scan / sustain electrode lines Y1 to Ym and the m common sustain electrode lines Z1 to Zm. Z driver 34 for driving and X driver 36 for driving n address pole lines X1 to Xn.

The Y driver 32 supplies the setup / down waveforms RP and -RP to initialize the full screen, and transmits the scan pulse SP to the scan / sustain electrode lines Y1 to Ym in a selective write and erase scheme. Supply sequentially. In addition, the Y driver 32 supplies sustain pulses SUSPy to cause sustain discharge.

The Z driver 34 is commonly connected to the common sustain electrode lines Z1 to Zm to set-down waveform (-RP), scan DC voltage, and sustain pulse (SUSPz) to the common sustain electrode lines Z1 to Zm. ) To supply sequentially.

The X driver 36 supplies the data pulse DP to the address electrode lines X1 to Xn to be synchronized with the scan pulse SP.

6 shows the Y driver 32 in detail to explain the configuration and operation of the Y driver 32.

Referring to FIG. 6, the Y driver 32 includes a sixth switch Q6 connected between an energy recovery circuit 41 and a driver integrated circuit (hereinafter, referred to as IC) 42. The scan reference voltage supply unit 46 and the scan voltage supply unit 44 connected between the sixth switch Q6 and the driver IC 42 to generate the scan pulse SP, and the sixth switch Q6 and the scan reference voltage. A set up supply 45 and a set down supply 43 are connected between the supply 46 and the scan voltage supply 44 to generate the setup / down waveforms (RP, -RP). Also connected between the setup voltage source Vsetup and the energy recovery circuit 41, between the first capacitor C1 and the scan voltage source Vsc and the third node n4 for keeping the setup voltage Vsetup constant. A second capacitor C2 connected in series is provided.

The driver IC 42 is connected in a push-pull form and includes twelfth and thirteenth switches Q12 and Q13 to which a voltage signal is input from the energy recovery circuit 41, the scan reference voltage supply 43, and the scan voltage supply 44. It consists of The output line between the twelfth and thirteenth switches Q12 and Q13 is connected to any one of the scan / sustain electrode lines Y1 to Ym.

The energy recovery circuit 41 includes external capacitors CexY for charging the voltage recovered from the scan / sustain electrode lines Y1 to Ym, switches Q1 and Q2 connected in parallel to the external capacitors CexY, An inductor L_y connected between the first node n1 and the second node n2, a third switch Q3 connected between the sustain voltage supply source Vs and the second node n2, and a second The fourth switch Q4 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 41 will be described below. It is assumed that the external capacitor Cex_y is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the external capacitor Cex_y is supplied to the driver IC 42 via the first switch Q1, the first diode D1, and the inductor L_y. And supplied to the scan / sustain electrode lines Y1 to Ym through an internal diode (not shown) of the driver IC 42. At this time, since the inductor L_y forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode lines Y1 to Ym. The third switch Q3 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode lines Y1 to Ym. Then, the voltage level of the scan / sustain electrode lines Y1 to Ym maintains the sustain voltage Vs. After a predetermined time, the first switch Q3 is turned off and the second switch Q2 is turned on. . At this time, the voltages of the scan / sustain electrode lines Y1 to Ym are recovered to the external capacitor Cex_y. Subsequently, when the second switch Q2 is turned off and the fourth switch Q4 is turned on, the voltage of the scan / sustain electrode lines Y1 to Ym maintains the ground potential.

The sixth switch to form a current path between the energy recovery circuit 41 and the driver IC 42 while the voltage of the scan / sustain electrode lines Y1 to Ym is charged and discharged by this energy recovery circuit 41. Q6 remains on.

In this way, the energy recovery circuit 41 recovers the voltage discharged from the scan / sustain electrode lines Y1 to Ym using the external capacitor Cex_y. The energy recovery circuit 41 supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym to reduce excessive power consumption during discharge of the setup period and the sustain period SPD.

The scan reference voltage supply unit 46 includes a tenth switch Q10 connected between the third node n3 and the selective write scan voltage source (-Vyw), and the scan node of the third node n3 and the selective erase (-). 11A and 11B switches Q11A and Q11B connected in series between Vye. The tenth switch Q10 is switched in response to the control signal yw supplied to the address period APD of the selective write subfield WSF, thereby supplying the selective write scan voltage -Vyw to the driver IC 42. It plays a role. The 11A and 11B switches Q11A and Q11B are switched in response to the control signal ye supplied to the address period APD of the selective erasing subfield ESF to thereby convert the selective erasing scan voltage (-Vye) into the driver IC. It serves to supply to (42).

The scan voltage supply 44 is composed of a seventh switch Q7 connected in series between the scan voltage source Vsc and the fourth node n4. The seventh switch Q7 is switched in response to the control signal SC supplied in the address period APD to supply the scan voltage Vsc to the driver IC 42. At this time, the second capacitor C2 connected between the scan voltage source Vsc and the third node n3 charges the scan voltage from the scan voltage source Vsc and maintains the charged voltage at a floating level. Allows different voltage levels to be created in the erase scheme.

The setup supply 45 is composed of a third diode D3, a resistor R and a fifth switch Q5 connected between the setup voltage source Vsetup and the third node n3. The third diode D3 blocks the reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The fifth switch Q5 serves to supply the setup waveform RP. The slope of this setup waveform RP is determined by the RC time constant value of the control terminal of the fifth switch Q5, that is, the RC time constant circuit connected to the gate terminal. Therefore, the slope of the setup waveform RP is adjusted by adjusting the resistance value of the variable resistor R1.

The setdown supply 43 includes a ninth switch Q9 connected between the third node n3 and the selective write scan voltage source -Vyw. The ninth switch Q9 serves to supply the setdown waveform (-RP). The slope of the set-down waveform (-RP) is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the ninth switch Q9, that is, the gate terminal. Therefore, the slope of the set-down waveform (-RP) is adjusted by adjusting the resistance value of the variable resistor (R2).

The Y driver 32 includes an eighth switch Q8 connected to the scan reference voltage supply section 46 and the scan voltage supply section 44 via the third node n3 and the fourth node n4, respectively. The eighth switch Q8 switches the scan voltage Vsc supplied to the driver IC 42 in response to the control signal Dic_updn.

The eleventh switches Q11A and Q11B and the sixth switch Q6 of the scan reference voltage supply unit 46 have the same function of switching in the same pass, but are connected in series with each other and are used in series. This is because voltage is used. In brief, a negative voltage is applied to the third node n3 in the address period APD. At this time, a problem occurs that the ground level is short due to the internal diode of the fourth switch Q4 of the energy recovery circuit 41.

In general, for stable sustain discharge, the discharge must be surely generated by the first sustain pulse SUSPy1. For this purpose, the first sustain pulse SUSPy1 should have a higher voltage than the other sustain pulses SUSPy. However, the prior art has the disadvantage that a voltage and a switch element must be added for this purpose.

Accordingly, an object of the present invention is to provide a driving voltage and a device of a plasma display panel, which can secure a driving margin by increasing the first sustain pulse voltage without adding a switch element and lower the driving voltage for sustain discharge. .

In addition, another object of the present invention is to drive the sustain pulse applied to the scan / sustain electrode line without the addition of a switch element by using a reset pulse applied at the time of setup and to drive the voltage up to the address electrode line corresponding to the sustain pulse. The present invention provides a driving voltage and a device of a plasma display panel to secure driving margin of sustain voltage and to prevent erroneous discharge by applying a spherical pulse of a degree.

1 is a perspective view showing a typical three-electrode alternating surface discharge plasma display panel.

2 is a diagram showing a frame structure of a conventional plasma display panel.

3 is a view showing another configuration of one frame of a conventional plasma display panel.

4 is a view showing a drive waveform of the PDP driving method.

5 is a view schematically showing a driving apparatus of a general PDP.

6 is a view showing in detail the scan / sustain electrode driver according to the prior art;

7 is a driving waveform diagram showing a driving method of the scan sustain electrode line Y of the plasma display panel according to the first embodiment of the present invention.

FIG. 8 is a detailed view of the Y driver 32 in order to explain the configuration and operation of the Y driver 32 in the plasma display panel according to the first embodiment of the present invention.

FIG. 9 is a view for explaining a driving waveform and a switch control signal of the first sustain pulse SUSPy1 of the scan / sustain electrode line according to the driver shown in FIG. 8; FIG.

Fig. 10 is a drive waveform diagram showing a driving method of the scan sustain electrode line Y of the plasma display panel according to the second embodiment of the present invention.

FIG. 11 is a view for explaining the driving waveform and the switch control signal of the first sustain pulse SUSPy1 of the scan / sustain electrode line as shown in FIG. 10 according to the driver shown in FIG.

Fig. 12 is a drive waveform diagram showing a driving method of the scan sustain electrode lines Y and the address electrode lines X of the plasma display panel according to the third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor 30Y: scan / sustain electrode

30Z: common sustain electrode 32: Y drive part

34: Z drive unit 36: X drive unit

41,51: energy recovery circuit 42,52: driver integrated circuit

46,56: scan reference voltage supply 44,54: scan voltage supply

45,55: Setup voltage supply part 43,53: Setdown voltage supply part

In order to achieve the above object, a plasma display panel driving method according to an embodiment of the present invention includes a plurality of first and second sustain electrode lines and a plurality of address electrode lines. Applying a reset pulse to the first sustain electrode line to generate a reset discharge; and controlling voltages applied to the plurality of first and second sustain electrode lines and the plurality of address electrode lines, thereby preventing address discharge in the subfield. And a sustain discharge between the plurality of first sustaining electrode lines and the plurality of second sustaining electrode lines having a high voltage sustain pulse using a reset pulse of a predetermined section having a predetermined rising slope during the reset discharge. It is characterized by including the step of generating.

In the present invention, the reset discharge is generated by supplying the reset pulse to the first sustain electrode of the first subfield, and by increasing the voltage in the form of a lamp when the reset pulse is set up, thereby forming wall charges in the cell and discharging it. Causing the voltage to decrease in the form of a ramp when the reset pulse is set down, thereby partially erasing the unneeded lower voltages by wall charge, and setting a positive direct current to the second sustain electrode when the reset pulse is set down. And supplying a voltage.

The rising slope of the reset pulse applied during the reset discharge in the present invention is characterized in that it has a rising rate of 1 to 4V per ㎲.

The first sustain pulse of the high voltage in the present invention is supplied by the initial predetermined time of the ramp-type reset pulse applied with a predetermined rising slope during the reset discharge.

The first sustain pulse of the high voltage in the present invention is supplied by the next predetermined time after the initial predetermined time of the ramp-type reset pulse applied with a predetermined rising slope during the reset discharge.

The sustain voltage of the high voltage applied to the plurality of first sustain electrode lines in the present invention is characterized in that at least one time.

In the present invention, a predetermined rectangular pulse is applied to the address electrode line so as to correspond to the high voltage sustain pulse of one or more ramp waveforms applied to the plurality of first sustain electrode lines.

A driving apparatus of a plasma display panel according to the present invention is a driving apparatus of a plasma display panel for driving electrodes divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining a discharge of the selected cell. And an energy recovery circuit for recovering energy from the first electrode of the panel, wherein the energy recovery circuit comprises a setup / down pulse in the reset period, a scan pulse corresponding to selective write to select the cell in the address period, and a selective erase. A first electrode driver for supplying a sustain pulse having a scan pulse to the first electrode, the sustain pulse having one or more high voltage lamp-shaped sustain pulses for maintaining the discharge of the selected cell during the sustain period; The first electrode driver is connected in the form of a push-pull to provide a scan driver for applying a voltage signal to the first electrode, a positive waveform setup signal having a ramp waveform in the reset period, and a sustain waveform having a ramp waveform in the sustain period. A setup driver for supplying the first electrode and a set-down driver for supplying a negative waveform signal having a ramp waveform to the first electrode after the positive setup signal is supplied; A first switch connected between the energy recovery circuit and the setup driver and a scan driver for switching a setdown pulse and a sustain pulse; and a sustain pulse of the ramp waveform connected between the first switch and the setup driver and the scan driver. A second switch for switching the sustain pulse and switching the sustain pulse, a scan voltage supply unit connected between the scan driver and a scan voltage source to supply a scan voltage to the scan driver in an address period of a selective write and erase field; And a third switch connected between the scan voltage supply unit and the setdown driver to perform a control operation of supplying a setdown pulse having a voltage level below the ground level and a scan pulse of an address period.

The second switch of the present invention is characterized in that the sustain pulse of the high voltage applied in the sustain period has the same or larger pulse width than the other sustain pulses.

In the present invention, any one of selective write data for selectively turning on the cell and selective erase data for selectively turning off the cell is supplied to a third electrode orthogonal to the first and second electrodes in the address period. When the at least one high voltage lamp-shaped sustain pulse is applied to the first electrode, an address driver for supplying a spherical data pulse of a voltage higher than the normal sustain pulse to the third electrode to correspond to the sustain pulse.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 13.

The driving apparatus of the PDP according to the present invention includes a Y driver 32 for driving m scan / sustain electrode lines Y1 to Ym and m common sustain electrode lines Z1 to Zm as shown in FIG. 5. And a Z driver 34 for driving the N-axis, and an X driver 36 for driving the n address electrode lines X1 to Xn, which will be described based on a selective write and erase method.

The Y driver 32 supplies the setup / down waveforms RP and -RP to initialize the full screen, and sequentially supplies the scan pulse SP to the scan / sustain electrode lines Y1 to Ym. In addition, the Y driver 32 supplies sustain pulses SUSPy in the sustain period to cause sustain discharge.

The Z driver 34 is commonly connected to the common sustain electrode lines Z1 to Zm to apply the setdown waveform (-RPSZ), the scan DC voltage, and the sustain pulse (SUSZ) to the Z electrode lines Z1 to Zm. It serves to supply sequentially.

The X driver 104 supplies the data pulse DP to the address electrode lines X1 to Xn to be synchronized with the scan pulse SP.

7 is a driving waveform diagram showing a method of driving the scan sustain electrode line Y of the plasma display panel according to the first embodiment of the present invention. At this time, the driving method of the common sustain electrode line Z and the address electrode line X is applied in the same manner as the driving waveform shown in the prior art of FIG.

Referring to FIG. 7, a reset pulse RP having a ramp-up waveform is supplied to the scan / sustain electrode lines Y at the time of setup of the reset period, and reset of the ramp-down waveform at set-down. Pulse (-RP) is supplied sequentially. At this time, the reset pulse RP of the ramp-up waveform has a slope of 1 to 4 V / ㎲. This indicates that it can raise 2 to 8V in about 2ms sustain pulse. The reset pulse (-RP) of the ramp-down waveform drops to the base voltage (GND) or the negative scan reference voltage (-Vy). In addition, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period APD, while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z, each of the scan / sustain electrode lines Y and the address electrode lines X has a negative polarity (−). ) Scan pulse SP and positive polarity data pulse DP are supplied to be synchronized with each other. The address discharge is performed by the scan pulse SP and the data pulse DP as described above.

Thereafter, in the sustain period SPD, the sustain pulses SUSPy and SUSPz alternate with the scan / sustain electrode lines Y and the common sustain electrode lines Z in the sustain period SPD so that sustain discharge occurs for the cells turned on by the address discharge. Supplied. In this case, the first sustain pulse SUSPy1 applied to the scan / sustain electrode line Y has a higher sustain voltage than the other sustain pulses SUSPy for stable sustain discharge. At this time, the supplied high sustain voltage Vs + Vra repeatedly uses the reset pulse RP of the ramp-up waveform as it is being set up during the reset period RPD. That is, the initial first sustain pulse SUSPy1 applied to the scan / sustain electrode line Y is formed by applying a ramp-up waveform supplied during the setup of the reset period for a predetermined time t0 to t1. For example, assuming that the ramp slope is 2V / kV and t1 is 3kV, a voltage increase effect of 6V can be obtained in the 3kV sustain period. The resulting voltage rise (2-8V) effect not only increases the drive margin but also allows the drive voltage to be lowered. This is because if only the first sustain discharge is made surely, the discharge voltage of the subsequent sustain pulse SUSPy may be supplied only enough to sustain the discharge. Of course, the voltage increase effect can be varied by adjusting the width of the first sustain pulse (SUSPy1). At the end of the sustain period SPD, an erase pulse (not shown; EP) is supplied to the scan / sustain electrode lines Y to cause the sustain discharge to be erased.

8 illustrates the Y driver 32 in detail to explain the configuration and operation of the Y driver 32 in the plasma display panel according to the first embodiment of the present invention.

Referring to FIG. 8, the Y driver 32 includes a sixth switch Q6 connected between the energy recovery circuit 51 and the driver IC 52, and between the sixth switch Q6 and the driver IC 52. A selective erase scan driver 56 and a scan voltage supply 54 connected to generate a selective erase scan pulse (-SESP), a sixth switch Q6, a selective erase scan driver 56 and a scan voltage supply 54 And a setup supply unit 55 and a set down / selective write scan driver 53 for generating a setup / down waveform (RP, -RP) and generating a selective write scan pulse (-SWSP). A seventh switch Q7 connected between the sixth switch Q6 and the driver IC 52 for supplying the reset pulse and the sustain pulse to the scan / sustain electrode line Y during the setup period and the sustain period SPD. do. Also connected between the setup voltage source Vsetup and the energy recovery circuit 51, between the first capacitor C1 and the scan voltage source Vsc and the third node n4 for keeping the setup voltage Vs constant. A second capacitor C2 connected in series is provided.

The driver IC 52 is connected in a push-pull form, and the fourteenth and fifteenth switches Q14 through which a voltage signal is input from the energy recovery circuit 51, the set-down / selective write scan driver 53, and the scan voltage supply 54. Q15).

The output line between the fourteenth and fifteenth switches Q14 and Q15 is connected to any one of the scan / sustain electrode lines Y1 to Ym.

The energy recovery circuit 51 includes external capacitors CexY for charging the voltage recovered from the scan / sustain electrode lines Y1 to Ym, switches Q1 and Q2 connected in parallel to the external capacitors CexY, An inductor L_y connected between the first node n1 and the second node n2, a third switch Q3 connected between the sustain voltage supply source Vs and the second node n2, and a second The fourth switch Q4 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 51 will be described below. It is assumed that the external capacitor Cex_y is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the external capacitor CexY is supplied to the driver IC 52 via the first switch Q1, the first diode D1, and the inductor L_y. And supplied to the scan / sustain electrode lines Y1 to Ym through an internal diode (not shown) of the driver IC 52. At this time, since the inductor L_y forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode lines Y1 to Ym. The third switch Q3 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode lines Y1 to Ym. Then, the voltage level of the scan / sustain electrode lines Y1 to Ym maintains the sustain voltage Vs. After a predetermined time, the first switch Q3 is turned off and the second switch Q2 is turned on. . At this time, the voltages of the scan / sustain electrode lines Y1 to Ym are recovered to the external capacitor Cex_y. Subsequently, when the second switch Q2 is turned off and the fourth switch Q4 is turned on, the voltage of the scan / sustain electrode lines Y1 to Ym maintains the ground potential.

The sixth switch to form a current path between the energy recovery circuit 51 and the driver IC 52 while the voltage of the scan / sustain electrode lines Y1 to Ym is charged and discharged by this energy recovery circuit 51. Q6 remains on.

In this way, the energy recovery circuit 51 recovers the voltage discharged from the scan / sustain electrode lines Y1 to Ym by using an external capacitor CexY. The energy recovery circuit 51 supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym to reduce excessive power consumption during discharge of the setup period and the sustain period.

The selective erase scan driver 56 includes an eleventh switch Q11 connected between the third node n3 and the selective write scan voltage source -Vyw, and the third node n3 and the selective erase scan voltage source (-). It consists of 12th and 13th switches Q12 and Q13 connected in series between Vye. The eleventh switch Q11 is switched in response to the control signal yw supplied in the address period APD of the selective write subfield WSF, thereby supplying the selective write scan voltage -Vyw to the driver IC 52. It plays a role. The twelfth and thirteenth switches Q12 and Q13 are switched in response to the control signal ye supplied to the address period APD of the selective erasing subfield ESF to thereby convert the selective erasing scan voltage (-Vye) into a driver IC. It serves to supply to (42). Since the applied voltage (-Vw) of the selective write scan pulse SWSP has a lower voltage value than the applied voltage (-Ve) of the selective erase scan pulse SESP, the twelfth and thirteenth switches Q12 and Q13 also have polarities. The two changed field effect transistors are formed in series.

The scan voltage supply unit 54 is composed of an eighth switch Q8 connected in series between the scan voltage source Vsc and the fourth node n4. The eighth switch Q8 is switched in response to the control signal SC supplied in the address periods of the selective write subfield WSF and the selective erase subfield ESF to transfer the scan voltage Vsc to the driver IC 52. It serves to supply. At this time, the second capacitor C2 connected between the scan voltage source Vsc and the third node n3 charges the scan voltage from the scan voltage source Vsc and maintains the charged voltage at a floating level. Allows you to create different voltage levels.

The setup supply 55 is composed of a third diode D3, a resistor R and a fifth switch Q5 connected between the setup voltage source Vsetup and the third node n3. The third diode D3 blocks the reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The fifth switch Q5 serves to supply the setup waveform RP. The slope of this setup waveform RP is determined by the RC time constant value of the control terminal of the fifth switch Q5, that is, the RC time constant circuit connected to the gate terminal. Therefore, the slope of the setup waveform RP is adjusted by adjusting the resistance value of the variable resistor R1.

The set-down driver 53 includes a tenth switch Q10 connected between the third node n3 and the selective write scan voltage source -Vyw. The tenth switch Q10 serves to supply the setdown waveform (-RP). The slope of this set-down waveform (-RP) is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the ninth switch Q9, that is, the gate terminal. Therefore, the slope of the set-down waveform (-RP) is adjusted by adjusting the resistance value of the variable resistor (R2).

The Y driver 32 includes a ninth switch Q9 connected to the selective erase scan driver 56 and the scan voltage supply unit 54 via the third node n3 and the fourth node n4, respectively. The ninth switch Q9 switches the scan voltage Vsc supplied to the driver IC 52 in response to the control signal Dic_updn.

FIG. 9 is a diagram illustrating a driving waveform and a switch control signal of the first sustain pulse SUSPy1 of the scan / sustain electrode line according to the driver shown in FIG. 8.

Referring to FIG. 9 in conjunction with FIGS. 7 and 8, the first sustain pulse SUSPy1 is supplied to the scan / sustain electrode line Y first in the sustain period SPD of one subfield. The first sustain pulse SUSPy1 is supplied to the scan / sustain electrode line Y through the driver IC 52 by turning on the third, fifth, and seventh switches Q3, Q5, and Q7. In detail, the third and fifth switches Q3 and Q5 are turned on for a predetermined time, that is, t0 to t1, and the seventh switch Q7 is continuously turned on for the sustain period SPD. In this case, the sustain voltage source Vs and the setup voltage source Vsetup are supplied to the scan / sustain electrode line Y through the seventh switch Q7 for a predetermined time. As described above, after the first sustain pulse SSUSPy1 is applied to the scan / sustain electrode line Y, the fifth switch Q5 is turned off and the sixth switch Q6 is turned on. This is for normally supplying the remaining sustain pulse SUSPy except the first sustain pulse SUSPy1 by the sustain voltage source Vs of the energy recovery circuit 51 without the influence of the setup voltage source Vsetup. At this time, the third and fourth switches Q3 and Q4 are turned on and turned off whenever the sustain pulse SUSPy is applied to the scan / sustain electrode line Y.

10 is a driving waveform diagram showing a method of driving the scan sustain electrode line Y of the plasma display panel according to the second embodiment of the present invention. At this time, the driving method of the common sustain electrode line Z and the address electrode line X is applied in the same manner as the driving waveform shown in the prior art of FIG.

Referring to FIG. 10, a reset pulse RP of a ramp-up waveform is supplied to the scan / sustain electrode lines Y at a setup of the reset period, and a reset of the ramp-down waveform at set-down. Pulse (-RP) is supplied sequentially. At this time, the reset pulse RP of the ramp-up waveform has a slope of 1 to 4 V / ㎲. This indicates that it can raise 2 to 8V in about 2ms sustain pulse. The reset pulse (-RP) of the ramp-down waveform drops to the base voltage (GND) or the negative scan reference voltage (-Vy). In addition, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period APD, while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z, each of the scan / sustain electrode lines Y and the address electrode lines X has a negative polarity (−). The scan pulse SP of) and the data pulse DP of positive polarity (+) are supplied to be mutually synchronized. The address discharge is performed by the scan pulse SP and the data pulse DP as described above.

Thereafter, in the sustain period SPD, the sustain pulses SUSPy and SUSPz alternate with the scan / sustain electrode lines Y and the common sustain electrode lines Z in the sustain period SPD so that sustain discharge occurs for the cells turned on by the address discharge. Supplied. In this case, the first sustain pulse SUSPy1 applied to the scan / sustain electrode line Y has a higher sustain voltage than the other sustain pulses SUSPy for stable sustain discharge. At this time, the supplied high sustain voltage Vs + Vrb repeatedly uses the ramp-up waveform reset pulse RP as it is during the setup of the reset period RPD. That is, the initial first sustain pulse SUSPy1 applied to the scan / sustain electrode line Y is formed by applying a ramp-up waveform supplied during the setup of the reset period for a predetermined time t1 to t2. In the case of the first embodiment shown in FIG. 7, the driving waveform of the predetermined time (t0 to t1) is used as it is from the time when the reset operation starts. In this case, since the voltage added to Vs is generated in the form of a lamp, a strong sustain is performed. The role may be somewhat weak to generate a discharge. Therefore, in the second embodiment of the present invention, the elevated voltage is operated after a predetermined time t0 to t1 elapses in the setup period as in the Ab region.

For example, suppose that t1 is 3 ms when the ramp slope is 2 V / m and assuming that t1 to t2 time is 3 ms again, the reset pulse RP of the ramp-up waveform is 6 ms for t0 to t2 hours. As a result, a voltage raising effect of 6V is obtained at t1 and a 12V voltage raising effect at t2. In order to obtain such a voltage raising effect, the sustain pulse SSUS is supplied only in the period t0 to t1. That is, the ramp-up operation is performed in the t0 to t1 section, but it is not actually supplied to the panel, but if the sustain pulse is supplied by the switch operation at t1, the square wave of Vs + 6V can be actually supplied to the panel. Of course, the voltage increase effect can be varied by adjusting the width of the first sustain pulse SSUSPy1, that is, the period t1 to t2. At the end of the sustain period SPD, an erase pulse (not shown; EP) is supplied to the scan / sustain electrode lines Y to cause the sustain discharge to be erased.

FIG. 11 is a diagram for explaining a driving waveform and a switch control signal of the first sustain pulse SUSPy1 of the scan / sustain electrode line as shown in FIG. 10 according to the driver shown in FIG. The same applies to the Y driver 32 shown in FIG. 8.

Referring to FIG. 11 in conjunction with FIGS. 8 and 10, the first sustain pulse SUSPy1 is supplied to the scan / sustain electrode line Y first in the sustain period SPD of one subfield. The first sustain pulse SUSPy1 first turns on the third and fifth switches Q3 and Q5 for t0 to t2. Since the fifth switch Q5 is turned on, the reset pulse RP of the ramp-up waveform is applied to the node between the sixth and seventh switches Q6 and Q7. However, since the second switch Q2 is in the turn-off state, the first sustain pulse SUSPy1 is not applied to the scan / sustain electrode line Y yet. When the seventh switch Q7 is turned on after the time t1 has elapsed, the reset pulse RP having the voltage of Vs + Vrb already raised by the rising slope during the setup of the reset period RPD becomes the scan / sustain electrode line ( Is applied to Y). For example, when the slope of the lamp pulse is 2V / ㎲ and the time intervals of t0 to t1 and t1 to t2 are 3㎲, respectively, in the case of the present invention, a voltage increase effect of about 12V can be obtained.

As described above, after the first sustain pulse SSUSPy1 is applied to the scan / sustain electrode line Y, the fifth switch Q5 is turned off and the sixth switch Q6 is turned on. This is for normally supplying the remaining sustain pulse SUSPy except the first sustain pulse SUSPy1 by the sustain voltage source Vs of the energy recovery circuit 51 without the influence of the setup voltage source Vsetup. At this time, the third and fourth switches Q3 and Q4 are turned on and turned off whenever the sustain pulse SUSPy is applied to the scan / sustain electrode line Y.

As described above, the first sustain pulse SUSPy1 having a high voltage is applied to the scan / sustain electrode line Y to generate a strong sustain discharge between the two sustain electrode lines Y and Z. In addition, the sustain pulse voltage can be increased without adding a separate circuit, thereby increasing the sustain voltage margin.

12 is a driving waveform diagram illustrating a method of driving the scan sustain electrode line Y and the address electrode line X of the plasma display panel according to the third embodiment of the present invention. At this time, the driving method of the common sustain electrode line (Z) is applied in the same manner as the driving waveform shown in the prior art of FIG.

Referring to FIG. 12, a ramp-up waveform reset pulse RP is supplied to the scan / sustain electrode lines Y at a setup of a reset period, and a rampdown waveform is reset at a set-down time. Pulse (-RP) is supplied sequentially. At this time, the reset pulse RP of the ramp-up waveform has a slope of 1 to 4 V / ㎲. This indicates that it can raise 2 to 8V in about 2ms sustain pulse. The reset pulse (-RP) of the ramp-down waveform drops to the base voltage (GND) or the negative scan reference voltage (-Vy). In addition, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period APD, while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z, each of the scan / sustain electrode lines Y and the address electrode lines X has a negative polarity (−). ) Scan pulse SP and positive polarity data pulse DP are supplied to be synchronized with each other. The address discharge is performed by the scan pulse SP and the data pulse DP as described above.

Thereafter, in the sustain period SPD, the sustain pulses SUSPy and SUSPz alternate with the scan / sustain electrode lines Y and the common sustain electrode lines Z in the sustain period SPD so that sustain discharge occurs for the cells turned on by the address discharge. Supplied. At this time, the plurality of sustain pulses SUSPy applied to the scan / sustain electrode line Y have a high sustain voltage Vs + Vra for stable sustain discharge. At this time, the supplied high sustain voltage Vs + Vra repeatedly uses the reset pulse RP of the ramp-up waveform as it is being set up during the reset period RPD. That is, the initial first sustain pulse SUSPy1 applied to the scan / sustain electrode line Y is formed by applying a ramp-up waveform supplied during the setup of the reset period for a predetermined time t0 to t1. However, an infinitely elevated voltage cannot be used for sustain pulses. This is because a high sustain pulse may cause an erroneous discharge due to the opposite discharge to the address electrode line (X). As a result, a pulse SUSPx corresponding to the sustain pulse voltage raised to correspond to the sustain pulse SUSPy applied to the scan / sustain electrode line Y is applied to the address electrode line X.

When driving as described above it is possible to ensure a sustain voltage margin and to prevent mis-discharge.

As described above, the method and apparatus for driving a plasma display panel according to the present invention apply a high voltage first sustain pulse to the scan / sustain electrode line using a lamp pulse applied during setup of a reset period without adding a separate circuit. In addition to increasing the sustain voltage driving margin, it is possible to lower the sustain driving voltage.

In addition, the driving method of the other plasma display panel according to the present invention applies a plurality of lamp type high voltage sustain pulses to the scan / sustain electrode lines using the lamp pulses applied during the setup of the reset period without additional circuitry. By applying a predetermined rectangular pulse to the address electrode line so as to correspond to the sustain pulse, it is possible to secure a driving margin of the sustain voltage and to prevent erroneous discharge between the sustain electrode and the address electrode.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

In the plasma display panel driving method comprising a plurality of first and second sustain electrode lines and a plurality of address electrode lines, Applying a reset pulse to the plurality of first sustain electrode lines to generate a reset discharge; Controlling the voltages applied to the plurality of first and second sustain electrode lines and the plurality of address electrode lines to generate an address discharge of a subfield; Generating a sustain discharge between the plurality of first sustaining electrode lines and the plurality of second sustaining electrode lines having a high voltage sustain pulse by using a reset pulse of a predetermined section having a predetermined rising slope during the reset discharge. And a plasma display panel driving method. The method of claim 1, The generating of the reset discharge may include supplying a reset pulse to the first sustain electrode of the first subfield; Increasing the voltage in the form of a lamp when setting up the reset pulse to form and discharge wall charges in the cell; Causing the voltage to decrease in the form of a lamp when the reset pulse is set down so that the unwanted down voltages are partially erased by wall charge; And supplying a positive DC voltage to a second sustain electrode when the reset pulse is set down. The method of claim 2, The rising slope of the reset pulse applied during the reset discharge has a rising rate of 1 to 4V per .. The method of claim 2, And the first sustain pulse of the high voltage is supplied by an initial predetermined time of a lamp type reset pulse applied with a predetermined rising slope during the reset discharge. The method of claim 2, And the first sustain pulse of the high voltage is supplied by a next predetermined time after an initial predetermined time of the ramp type reset pulse applied with a predetermined rising slope during the reset discharge. The method according to any one of claims 4 to 5, And the predetermined time is about 2 to 4 s. The method of claim 1, And a high voltage sustain pulse applied to the plurality of first sustain electrode lines is a first sustain pulse of the electrode line. The method of claim 1, A high voltage sustain pulse applied to a plurality of first sustain electrode lines is one or more times. The method of claim 8, And applying a predetermined rectangular pulse to the address electrode line so as to correspond to a high voltage sustain pulse of one or more ramp waveforms applied to the plurality of first sustain electrode lines. A driving apparatus of a plasma display panel for driving electrodes divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of a selected cell, An energy recovery circuit for recovering energy from the first electrode of the panel, comprising: a setup / down pulse in the reset period, a scan pulse corresponding to selective write and a selective pulse to select the cell in the address period And a first electrode driver for supplying sustain pulses having one or more high voltage lamp-shaped sustain pulses to maintain discharge of the selected cell in the sustain period; A scan driver connected to the first electrode driver in a push-pull form to apply a voltage signal to the first electrode; A setup driver for supplying a ramp waveform positive setup signal in the reset period and a sustain waveform in the ramp waveform to the first electrode in the sustain period; A set-down driver configured to supply a negative waveform signal having a ramp waveform to the first electrode after the positive setup signal is supplied; A first switch connected between the energy recovery circuit and the setup driver and the scan driver for switching a setdown pulse and a sustain pulse; A second switch connected between the first switch and the setup driver and the scan driver to apply sustain pulses of the ramp waveform and to switch sustain pulses; A scan voltage supply unit connected between the scan driver and a scan voltage source to supply a scan voltage to the scan driver in an address period of a selective write and erase field; And a third switch connected between the scan voltage supply unit and the setdown driver to perform a control operation of supplying a setdown pulse having a voltage level below ground level and a scan pulse of an address period. . The method of claim 10, And an energy recovery circuit for recovering energy from the second electrode of the panel, alternating with the first electrode driver, and having a second electrode driver for supplying a DC voltage to the second electrode during selective writing and selective erasing. Driving device for a plasma display panel, characterized in that. The method of claim 10, And wherein the second switch is configured such that a high voltage sustain pulse applied in the sustain period has a pulse width equal to or greater than that of other sustain pulses. The method of claim 10, A first capacitor connected between the energy recovery circuit and a setup voltage source to maintain a constant lamp pulse voltage level and to generate a lamp pulse; And a second capacitor connected between the scan voltage source and the scan driver to maintain a constant scan pulse voltage level and to adjust a voltage supplied to the scan driver. The method of claim 10, In the address period, one of the selective write data for selectively turning on the cell and the selective erase data for selectively turning off the cell is supplied to a third electrode orthogonal to the first and second electrodes, and to the first electrode. And an address driver for supplying a third electrode with a data pulse whose voltage is higher than a normal sustain pulse to correspond to the sustain pulse when one or more high voltage lamp type sustain pulses are applied to the third electrode. Device.