KR100421670B1 - Driving Apparatus of Plasma Display Panel - Google Patents

Abstract

The present invention relates to a device for driving a plasma display panel that can increase driving efficiency.

The driving apparatus of the plasma display panel according to the present invention includes a reset voltage generator for generating a reset voltage, a sustain voltage generator connected to the reset voltage generator for generating a sustain voltage, the reset voltage generator and the sustain. It is connected between a voltage generator and a scan voltage generator for generating a scan voltage, an electrode driver for supplying the reset voltage, the sustain voltage and the scan voltage to a drive electrode, and between the both ends of the output terminal of the sustain voltage generator; And forming a signal transmission path between the reset voltage generator and the electrode driver, and switching the signal transmission path between the sustain voltage generator and the electrode driver.

Description

Driving device for plasma display panel {Driving Apparatus of Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a plasma display panel, and more particularly to a driving device of a plasma display panel which can increase driving efficiency.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, the discharge cells of the three-electrode AC surface discharge type PDP are formed on the scan / sustain electrode 30Y and the common sustain electrode 30Z formed on the upper substrate 10, and the lower substrate 18. An address electrode 20X is provided. Each of the scan / sustain electrode 30Y and the common sustain electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and is provided at one edge of the transparent electrodes 12Y and 12Z. Metal bus electrodes 13Y and 13Z formed. The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Referring to FIG. 2, in the method of driving a three-electrode AC surface discharge type PDP, one frame includes subfields SF1 to SF6 of selective writing and subfields SF7 to SF12 of selective erasing. The first subfield SF1 is divided into a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustaining discharge for the discharge cell selected by the address discharge, and an erasing period for canceling the sustain discharge. . Each of the second to fifth subfields SF2 to SF5 is divided into an optional write address period, a sustain period, and an erase period. The sixth subfield SF6 is divided into an optional write address period and a sustain period. In the first to sixth subfields SF1 to SF6, the selective write address period and the erase period are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3, 4,5). The seventh to twelfth subfields SF7 to SF12 sustain sustain discharge of discharge cells other than the discharge cells selected by the address discharge and the selective erase address period for turning off the selected discharge cells without the entire surface-writing period. Divided into periods. In the seventh to twelfth subfields SF7 to SF12, not only the selective erasure address period but also the sustain period are set equally. The sustain period of the seventh to twelfth subfields SF7 to SF12 is set to a luminance relative ratio of 2 ⁵ to have the same luminance relative ratio as that of the sixth subfield SF6.

Each of the seventh to twelfth subfields SF7 to SF12 driven by the selective erasing method must have the previous subfield turned on to turn off unnecessary discharge cells whenever the subfields are consecutive. For example, in order for the seventh subfield SF7 to be turned on, the sixth subfield SF6 driven by the selective write method, which is the previous subfield, must be turned on. After the sixth subfield SF6 is turned on, the unnecessary discharge cells are turned off in the seventh to twelfth subfields SF7 to SF12. To this end, the cells turned on in the sixth subfield WSF, which is the last selective write subfield WSF, must be turned on by the sustain discharge in order for the selective erase subfield ESF to be used. Therefore, the seventh subfield SF7 does not need a separate writing discharge for the selective erase address. In addition, the eighth to twelfth subfields SF8 to SF12 also selectively turn off cells that are turned on in the previous subfield without front lighting.

FIG. 3 is a waveform diagram illustrating a PDP driving waveform shown in FIG. 1.

Referring to FIG. 3, in the reset period or the setup period of the first selective write subfield SW1, the set-down waveform (-RPSY), which is a ramp waveform of a falling slope following the setup waveform RPSY in the scan / sustain electrode lines Y, is set. ) Are supplied sequentially. This set-down waveform (-RPSY) drops to the negative scan reference voltage. In addition, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period of the first selective write subfield SW1, the scan / sustain electrode lines Y and the address electrode lines X while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z. Negative polarity selective write scan pulse (-SWSCN) and positive polarity selective write data pulse (SWD) are supplied to each other in synchronization with each other. The sustain pulses SUSY and SUSZ are applied to the scan / sustain electrode lines Y and the common sustain electrode lines Z so that sustain discharge occurs for the cells turned on by the address discharge of the first selective write subfield SW. Alternately supplied. At the end of the second selective write subfield SW2, the erase pulse ERSPY is supplied to the scan / sustain electrode lines Y for the sustain discharge to be erased.

The reset period or the setup period of the selective erase subfield SE is omitted. In the address period of the selective erase subfield SE, a negative selective erase scan pulse (-SESCN) and a positive selective erase to turn off a cell in each of the scan / sustain electrode lines Y and the address electrode lines X, respectively. The data pulses SED are supplied to be synchronized with each other. The selective erase scan pulse (-SESCN) drops to the selective erase scan voltage (-Ve) higher than the scan reference voltage (-Vw). Sustain pulses SUSY and SUSZ alternate between scan / sustain electrode lines Y and common sustain electrode lines Z so that sustain discharge occurs for cells that are not turned off by the address discharge in the selective erase subfield SE. Supplied as In the case where the next subsequent subfield is the selective erasing field SE, a sustain pulse SSUSY having a relatively large pulse width is supplied to the scan / sustain electrode lines Y at the end of the current selective erasing subfield SE. . In the last selective erase subfield in which the next subfield is the selective write subfield SW, the erase pulse ERSPY and the ramp signal RAMP are applied to the scan / sustain electrode lines Y and the common sustain electrode lines Z. It erases the sustain discharge of the supplied and turned on cells.

Referring to FIG. 4, a driving circuit of a conventional PDP includes fifth and sixth switches Q5 connected between an energy recovery circuit 41 and a driver integrated circuit (hereinafter, referred to as an “IC”) 42. Q6 and a scan reference voltage supply unit 43 and a scan voltage supply unit connected between the fifth and sixth switches Q5 and Q6 and the driver IC 42 to generate scan pulses (-SWSCN and -SESCN). 44 and a setup supply unit connected between the fifth and sixth switches Q5 and Q6 and the scan reference voltage supply unit 43 and the scan voltage supply unit 44 to generate the setup / down waveforms RPSY and -RPSY. 45 and set down supply 46.

The driver IC 42 is connected in a push-pull form and includes thirteenth and fourteenth switches Q13 and Q14 to which a voltage signal is input from the energy recovery circuit 41, the scan reference voltage supply 43, and the scan voltage supply 44. It is composed of The output line between the thirteenth and fourteenth switches Q13 and Q14 is connected to one of the scan / sustain electrode lines Y and applied to the panel.

The energy recovery circuit 41 includes a first capacitor C1 for charging a voltage recovered from the scan / sustain electrode line Y, switches Q1 and Q2 connected in parallel to the first capacitor C1, An inductor L connected between the first node n1 and the second node n2, a third switch Q3 connected between the sustain voltage supply Vs and the second node n2, and a second The fourth switch Q4 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 41 will be described below. It is assumed that the first capacitor C1 is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the first capacitor C1 is transferred to the driver IC 42 via the first switch Q1, the first diode D1, and the inductor L. And is supplied to the scan / sustain electrode line (Y) through an internal diode of the driver IC (42). At this time, since the inductor L constitutes a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode line Y. The third switch Q3 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode line Y. Then, the voltage level of the scan / sustain electrode line Y maintains the sustain voltage Vs. After a predetermined time, the third switch Q3 is turned off and the second switch Q2 is turned on. At this time, the voltage of the scan / sustain electrode line Y is recovered to the first capacitor C1. Subsequently, when the second switch Q2 is turned off and the fourth switch Q4 is turned on, the voltage of the scan / sustain electrode line Y maintains the base potential. While the voltage of the scan / sustain electrode line Y is charged and discharged by the energy recovery circuit 41, the fifth and sixth elements are formed to form a current path between the energy recovery circuit 41 and the driver IC 42. The switch Q5 remains on.

In this way, the energy recovery circuit 41 recovers the voltage discharged from the scan / sustain electrode line Y by using the first capacitor C1, and then supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym. This reduces excessive power consumption during discharging during the setup and sustain periods.

The scan reference voltage supply 43 includes a tenth switch Q10 connected between the third node n3 and the selective write scan voltage source (-Vw), and the erase voltage scan voltage source for the third node n3 and the selective erase. It consists of eleventh and twelfth switches Q11 and Q12 connected in series between (-Ve). The tenth switch Q10 is switched in response to the control signal yw supplied in the address period of the selective write subfield SW, thereby supplying the selective write scan voltage (-Vw) to the driver IC 42. do.

The eleventh and twelfth switches Q11 and Q12 are switched in response to the control signal ye supplied in the address period of the selective erasing subfield SE to thereby convert the selective erasing scan voltage -Ve to the driver IC 42. To serve.

The eleventh and twelfth switches Q11 and Q12 use a switch element having a polarity. The eleventh and twelfth switches Q11 and Q12 switch in the same path as the fifth and sixth switches Q5 and Q6. Since the switches are at the negative voltage level at the third node n3 in the address period to which the selective write scan voltage source (-Vw) and the selective erase scan voltage source (-Ve) are supplied, the switches are arranged within the fourth energy recovery circuit 41. In order to solve the problem of short-circuit with the ground potential by the diode component of the switch Q4, the polarity is formed in each of them. Further, since the selective write scan voltage source (-Vw) has a lower potential than the selective erase scan voltage source (-Ve), the polarity of the eleventh and twelfth switches Q11 and Q12 is formed.

The scan voltage supply unit 44 includes a third diode D3 and an eighth switch Q8 connected between the scan voltage source Vsc and the fourth node n4. The third diode D3 blocks the reverse current flowing from the fourth node n4 toward the scan voltage source Vsc. The eighth switch Q8 may charge different voltages by charging the voltage charged in the third capacitor C3 and making the floating level. For example, assuming that the scan voltage source Vsc is 80V for the selective write voltage (-Vw) and the selective write voltage (-Vw) is -80V, the drive IC when the tenth switch Q10 is turned on. Both ends of 42 apply voltages of 0V and -80V. When the selective erase scan voltage (−Vye) is −40 V and the eleventh switch Q11 and the twelfth switch Q12 are turned on, −40 V and +40 V are applied across the drive IC 42. That is, while maintaining the 80V potential charged in the third capacitor C3 at the floating level, different voltage levels may be made in the selective write method and the selective erase method.

The setup supply part 45 is composed of a fifth diode D4 and a fifteenth switch Q15 connected between the setup voltage source Vsetup and the third node n3. The fourth diode D4 blocks the reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The fifteenth switch Q15 serves to supply the setup waveform RPSY. The slope of the setup waveform RPSY is determined by the control terminal of the second capacitor C2 and the fifteenth switch Q15, that is, the RC time constant of the RC time constant circuit connected to the gate terminal. The RC time constant value is adjusted by adjusting the resistance value.

The set down supply section 46 is composed of a ninth switch Q9 connected between the third node n3 and the selective write scan voltage source -Vw. The ninth switch Q9 serves to supply the setdown waveform -RPSY. The slope of the set-down waveform (-RPSY) is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the ninth switch Q9, that is, the gate terminal, and RC is controlled by adjusting the resistance value of the variable resistor R2. The time constant value is adjusted.

In addition, a seventh switch Q7 connected to the scan reference voltage supply unit 43 and the scan voltage supply unit 44 via the third node n3 and the fourth node n4 is provided. The seventh switch Q7 switches the scan voltage Vsc supplied to the driver IC 42 in response to the control signal Dic_updn.

The driving efficiency of this PDP is determined by the sustain pulse that consumes the most power. This sustain pulse is formed by the fifth to seventh switches Q5 to Q7 and supplied to the panel through the drive IC 42. That is, since the fifth to seventh switches Q5 to Q7 illustrated in FIG. 5 serve as a passage through which a high voltage sustain pulse passes, one or more switches are configured in parallel in an actual circuit configuration. In addition, these switch elements must use twice that part again by using negative voltage. This causes a problem that occupies a large area in the printed circuit board.

Accordingly, an object of the present invention is to provide a driving device of a plasma display panel which can increase driving efficiency.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram showing a frame structure of a conventional plasma display panel.

3 is a driving waveform diagram of a conventional plasma display panel.

4 is a circuit diagram showing a driving apparatus of a conventional plasma display panel.

Fig. 5 is a circuit diagram showing a driving device of the plasma display panel according to the first embodiment of the present invention.

FIG. 6 is a waveform diagram showing a switching operation of a reset block of the plasma display panel shown in FIG.

FIG. 7 is a waveform diagram illustrating a switching operation of a scan block of the plasma display panel shown in FIG. 5.

FIG. 8 is a waveform diagram showing a switching operation of a sustain block of the plasma display panel shown in FIG.

9 is a circuit diagram illustrating a driving apparatus of a plasma display panel according to a second embodiment of the present invention.

FIG. 10 is a waveform diagram illustrating a scan block switching operation of the plasma display panel shown in FIG. 9; FIG.

11 is a circuit diagram illustrating a driving apparatus of a plasma display panel according to a third embodiment of the present invention.

FIG. 12 is a waveform diagram showing driving waveforms of the plasma display panel shown in FIG. 11; FIG.

13 is a circuit diagram illustrating a driving apparatus of a plasma display panel according to a fourth embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor 30Y: scan / sustain electrode

30Z: common sustain electrode 41,71: energy recovery circuit

42,72: Driver Integrated Circuits

In order to achieve the above objects, a driving apparatus of a PDP according to the present invention includes a reset voltage generator for generating a reset voltage, a sustain voltage generator for generating a sustain voltage connected to the reset voltage generator, and the reset voltage. A scan voltage generator connected to the generator and the sustain voltage generator to generate a scan voltage, an electrode driver for supplying the reset voltage, the sustain voltage, and the scan voltage to a driving electrode, and the sustain voltage generator; It is provided between the both ends of the output terminal to form a signal transmission path between the reset voltage generator and the electrode driver, and a switching element for switching the signal transmission path between the sustain voltage generator and the electrode driver.

The sustain voltage generator includes a first capacitor for charging a voltage recovered from the electrode driver, first and third switches connected in parallel to the first capacitor, and a series connection between the first switch and the switching element. A first diode and a first inductor, a second diode and a second inductor connected in series between the third switch and the switching element, a third diode and a second switch connected in series between the switching element and the ground terminal; And a fourth diode and a fourth switch connected in series between the switching element and the sustain voltage supply source.

The driving apparatus of the plasma display panel according to the present invention is located at the output terminal of the sustain voltage generator and the reset pulse generator to form a signal transmission path between the reset voltage generator and the electrode driver, and to maintain the sustain voltage generator. It is provided with a switching element for switching the signal transmission path between the electrode driver.

The sustain voltage generator includes a capacitor for charging a voltage recovered from the electrode driver, first and third switches connected in parallel to the capacitor, an inductor connected between a second node and a third node, and the third And a fourth switch connected between the node and the sustain voltage supply source, and a second switch connected between the third node and the ground terminal.

The reset driver includes a reset voltage driver for supplying a positive waveform reset signal of a ramp waveform to the driving electrode during a reset period, and a negative waveform signal of the ramp waveform to the driving electrode after the positive polarity reset signal is supplied. It has a set-down driving part.

A driving apparatus of a plasma display panel according to the present invention for achieving the above object is a reset voltage generator for generating a reset voltage, a sustain voltage generator for being connected to the reset voltage generator for generating a sustain voltage, and the reset And a scan voltage generator connected to a voltage generator and the sustain voltage generator to generate a scan voltage, and a switching device for supplying the sustain voltage, the scan voltage, and the reset voltage to a driving electrode in response to a control signal. The switching device controls the reset voltage in response to the control signal supplied in the reset period.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 13.

Referring to FIG. 5, the PDP driving circuit according to the first embodiment of the present invention may include a fourteenth switch S14 connected between both ends of the energy recovery circuit 71, and a fourteenth switch S14 and the driver IC 72. A scan reference voltage supply unit 73 and a scan voltage supply unit 74, a fourteenth switch S14, a scan reference voltage supply unit 73, and a scan voltage supply unit for generating scan pulses (-SWSCN and -SESCN) Connected between 74 and set-up supply 75 and set-down supply 76 for generating the setup / down waveform (RPSY,-RPSY).

The driver IC 72 is connected in a push-pull form and a voltage signal is inputted from the energy recovery circuit 71, the scan reference voltage supply 73, the scan voltage supply 74, the setup supply 75 and the set-down supply 76. Consisting of sixth and seventh switches S6 and S7. The output line between the sixth and seventh switches S6 and S7 is connected to any one of the scan / sustain electrode lines Y and applied to the panel.

The energy recovery circuit 71 includes a first capacitor C1 for charging a voltage recovered from the scan / sustain electrode line Y, and first and third switches S1 connected in parallel to the first capacitor C1. S3, the first and second inductors L1 and L2 connected in series to the first and third switches, respectively, and the fourth diode connected between the sustain voltage supply Vs and the second node n2. (D4) and the fourth switch S4, and the third diode D3 and the second switch S2 connected between the third node n3 and the ground terminal GND.

Since the potential of the fourth and fifth nodes n4 and n5 drops to the selective write voltage (-Vw), the third diode D3 prevents disconnection due to the diode component inside the second switch S2. In addition, since the potentials of the fourth and fifth nodes n4 and n5 rise to the selective erasing voltage Ve, the fourth diode D4 prevents disconnection due to the diode component inside the fourth switch S4. Do it.

The first inductor L1 is used in the falling pulse section, and the second inductor L2 is used in the falling pulse section. That is, the driving efficiency can be improved because the first and second inductors L1 and L2 have different rising and falling periods set.

The scan reference voltage supply 73 includes an eighth switch S8 connected between the fourth node n4 and the selective write scan voltage source (-Vw), and the fourth node n4 and the selective erase scan voltage source (−). It consists of a ninth switch S9 connected between Ve). The eighth switch S8 serves to supply the selective write scan voltage (-Vw) to the driver IC 72. The ninth switch S9 serves to supply the selective erasing scan voltage −Ve to the driver IC 72.

The scan voltage supply unit 74 includes a fifth switch S5 connected between the scan voltage source Vsc and the fifth node n5. The fifth switch S5 serves to supply the scan voltage Vsc to the driver IC 72.

The setup supply unit 75 includes a fifth diode D5 and tenth and eleventh switches S10 and S11 connected between the reset voltage source Vreset and the fourth node n4. The fifth diode D5 blocks the reverse current flowing from the fourth node n4 toward the reset voltage source Vreset. The tenth and eleventh switches S10 and S11 serve to supply the setup waveform RPSY. The setup waveform is formed by turning on the tenth and eleventh switches S10 and S11 and adding the reset voltage Vreset charged to the third capacitor C3 to the reference voltage Vb. At this time, the slope of the setup waveform RPSY is determined by the eleventh switch S11, which is a ramp type switch that gradually increases with the ramp slope.

The set-down supply unit 76 is composed of twelfth and thirteenth switches S12 and S13 connected between the fourth node n4 and the selective write scan voltage source -Vw. The twelfth and thirteenth switches S12 and S13 serve to supply a setdown waveform (-RPSY). At this time, the slope of the set-down waveform is determined by the thirteenth switch S13, which is a ramp-type switch that gradually decreases with a ramp slope.

In addition, the fourteenth switch S14 connects the fourth and fifth nodes n4 and n5 of the drive IC to enable smooth operation when the ramp waveform rises and falls.

6 to 8 are waveform diagrams showing driving waveforms of the PDP according to the first embodiment of the present invention.

Referring to FIG. 6, in the reset period of the selective write subfield SW, the setup waveform RPSY and the setdown waveform −RPSY are successively supplied to the scan / sustain electrode line Y. To this end, the tenth to fourteenth switches S10 to S14 are sequentially turned on to supply the positive reset voltage Vreset and the negative scan reference voltage −Vw to the driver IC 42. The setup waveform RPSY rises to the reset voltage Vreset when the tenth and eleventh switches S10 and S11 are turned on for t1. The reference voltage is maintained for a predetermined period between t1 and t2 at the turn-off time of the tenth and eleventh switch elements S10 and S11 and at the turn-on time of the twelfth and thirteenth switch elements S12 and S13. Then, at t2, the thirteenth switch S13 is turned on so that the set-down waveform -RPSY drops to the negative scan reference voltage -Vw. At this time, the twelfth switch S12 is turned on and the reset voltage is charged in the third capacitor C3. As such, since the setup waveform RPSY rises to the reset voltage Vreset by a predetermined slope, the setup waveform RPSY is generated in the cell while the wall charge necessary for the scan is generated without causing a large discharge in the cell. The energy recovery circuit 71 operates in the falling section of the setup waveform RPSY, and the inclination thereof is gently adjusted by turning on the fourteenth switch S14 during the reset period. Since the falling slope of the setup waveform (RPSY) is gentle, the cells are not self-erased and the voltage margin of the set-down waveform (-RPSZ) supplied to the common sustain electrode line (Z) can be widened.

The reset period is omitted in the selective erase subfield SE. This means that if the next subfield is the selective erase subfield SE, the last sustain pulse SUSY generated at the end of the current selective write subfield SW or the selective erase subfield SE is the next selective erase subfield SE. ) To turn on the cell.

Referring to FIG. 7, when the selective write scan voltage (-Vw) is about -80V, the selective erase scan voltage (-Ve) is -40V, and the voltage required for the scan period is 80V, the selective write subfield In the address period of SW, the fifth switch S5 is turned on so that the potential of the fifth node n5 becomes the scan voltage Vsc, and the voltage Vsc is supplied to the driver IC 72. The eighth switch S8 is turned on so that the potential of the fourth node n4 becomes the selective write scan voltage (-Vw), and the voltage (-80V) is supplied to the driver IC 42. Then, the scan pulse (-SWSCN) is sequentially supplied to the scan / sustain electrode lines (Y) and at the same time the scan voltage (80V) is charged to the second capacitor (C2).

In the address period of the selective erasing subfield SE, the ninth switch S9 is turned on so that the selective erasing scan voltage (-Ve = -40V), which is the potential of the fourth node, is supplied to the driver IC 42. At the same time, the fifth switch S5 is turned on to maintain 40V by the voltage 80V charged by the second capacitor C2. Since the 40V is higher than the scan voltage Vsc, the 40V is cut off by the sixth diode D6 and supplied to the drive IC. The scan pulse (-SESCN) is then sequentially supplied to the scan / sustain electrode line (Y).

Referring to FIG. 8, it is assumed that the first capacitor C1 is charged with the voltage Vs / 2 in the sustain period of the selective write subfield SW and the selective erase subfield SE. When the third switch S3 is turned on, the voltage charged in the first capacitor C1 is the third switch S3, the second diode D2, the second inductor L2, and the fourth node n4. Is supplied to the driver IC 72 via and is supplied to the scan / sustain electrode line Y through the internal diode of the driver IC 72. At this time, since the second inductor L2 forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode line Y. The fourth switch S4 is turned on at the resonance point of the resonant waveform via the fourth node n4 to supply the sustain voltage Vs to the scan / sustain electrode line Y. Then, the voltage level of the scan / sustain electrode line Y maintains the sustain voltage Vs. After a predetermined time, the fourth switch S4 is turned off and the first switch S1 is turned on. At this time, the voltage of the scan / sustain electrode line Y is recovered to the first capacitor C1 via the fifth node n5. Subsequently, when the first switch S1 is turned off and the second switch S2 is turned on, the voltage of the scan / sustain electrode line Y maintains a base potential.

The energy recovery circuit 71 recovers the voltage discharged from the scan / sustain electrode line Y by using the first capacitor C1 and then supplies the recovered voltage to the scan / sustain electrode line Y. Excessive power consumption is reduced during discharge of the period and the sustain period.

As described above, the fourteenth switch S14 of the driving circuit of the PDP according to the first embodiment of the present invention is formed as one switch instead of the fifth to seventh switches S5 to S7 that are formed of several dozen conventional ones. The fourteenth switch S14 is turned on to supply the reset pulse to the driver IC 72. The fourteenth switch S14 may be driven by one switch since only three to six are used during one frame.

When the sustain pulse is supplied, the fourteenth switch S14 is turned off to supply the sustain pulse to the driver IC 72. For this reason, the drive efficiency can be improved by reducing the switch supplied with the sustain pulse to the drive IC 72 and supplying the sustain pulse to the panel in the shortest distance.

Referring to FIG. 9, the PDP driving circuit according to the second embodiment of the present invention may have other configurations and features except for the connection position of the energy recovery circuit 71 and the fourteenth switch S14. Same as the circuit.

The energy recovery circuit 71 has a first capacitor C1 for charging a voltage recovered from the scan / sustain electrode lines Y1 to Ym and switches connected in parallel to the first capacitor C1 as in the related art. S1, S3, the inductor L connected between the second node n2 and the third node n3, and the fourth switch connected between the sustain voltage supply source Vs and the third node n3 ( S4 and the second switch S2 connected between the third node n3 and the ground terminal GND.

The fourteenth switch S14 is connected to the energy recovery circuit 71, the setup supply unit 75, and the setdown supply unit 76 through the first node n1. The reset pulse and the sustain pulse passing through the first node n1 are supplied to the drive IC 72 through the fourth node n4. That is, the fourteenth switch S14 serves to supply the sustain pulse to the drive IC 72 and may be driven by one fourteenth switch S14 instead of a plurality of conventional eighth switches. In addition, the fourteenth switch S14 is turned on in the sustain period and the reset period, and the sustain pulse is supplied to the drive IC 72 through the fourteenth switch S14. In addition, the fourteenth switch S14 is driven by driving the sustain pulse and the reset pulse to the fourth and fifth nodes n4 and n5 of the drive IC 72. Furthermore, the fourteenth switch S14 may be separated and replaced at the fourth and fifth nodes n4 and n5, respectively, to allow flexible circuit design.

Referring to FIG. 10, the PDP driving method according to the second embodiment of the present invention includes the same driving method except for the sustain period in comparison with the PDP driving method shown in FIG. 7.

In the sustain period of the selective write subfield SW and the selective erase subfield SE according to the second embodiment of the present invention, it is assumed that the first capacitor C1 is charged with the voltage Vs / 2. When the third switch S3 and the fourteenth switch S14 are turned on, the voltage charged in the first capacitor C1 may be the third switch S3, the second diode D2, the inductor L, and the first switch S14. 14 is supplied to the driver IC 72 via the switch S14, and is supplied to the scan / sustain electrode line Y through the internal diode of the driver IC 72. At this time, since the inductor L constitutes a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode line Y. The fourth switch S4 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode line Y. Then, the voltage level of the scan / sustain electrode line Y maintains the sustain voltage Vs. After a predetermined time, the fourth switch S4 is turned off and the first switch S1 is turned on. At this time, the voltage of the scan / sustain electrode line Y is recovered to the first capacitor C1. Subsequently, when the first switch S1 is turned off and the second switch S2 is turned on, the voltage of the scan / sustain electrode line Y maintains a ground potential.

The energy recovery circuit 71 recovers the voltage discharged from the scan / sustain electrode line Y by using the first capacitor C1 and then supplies the recovered voltage to the scan / sustain electrode line Y. Excessive power consumption is reduced during discharge of the period and the sustain period. In addition, the number of inductors L in the energy recovery circuit 71 is reduced from two conventional ones. As a result, the transmission path of the sustain pulse is shortened, thereby increasing the energy recovery efficiency.

11 and 12, the PDP driving circuit according to the third embodiment of the present invention has the same components except that the 14th switch is removed in comparison with the PDP circuit shown in FIG.

The fourteenth switch S14 illustrated in FIG. 5 serves to pass the reset pulse, and the fourteenth switch S14 illustrated in FIG. 9 serves to pass the sustain pulse. Instead of the fourteenth switch S14, the seventh switch S7 inside the drive IC 72 is operated in response to a control signal. The seventh switch S7 is switched in response to the control signal on supplied in the reset period, thereby lowering the voltage of the setup waveform. Alternatively, since the floating operation is possible using the driver IC 72 photocoupler and the output can be unilaterally adjusted by the driver IC 72 itself control function, the seventh switch S7 is turned on in the reset period so that the reset voltage Vreset is turned off. The voltage drops down.

Since the potential at the fourth node n4 is not lowered to the selective write voltage -Vw by the seventh switch S7 controlling the reset pulse, the third diode D3 may be removed.

Referring to FIG. 13, the PDP driving circuit according to the fourth embodiment of the present invention has the same configuration and features as the PDP circuit of FIG. 6 except for the position of the set-down supply unit.

The set-down supply unit 76 is composed of twelfth and thirteenth switches S12 and S13 connected between the fourth and fifth nodes n4 and n5 and the selective write scan voltage source -Vw. The twelfth and thirteenth switches S12 and S13 serve to supply a setdown waveform (-RPSY). The slope of this set-down waveform is determined by the thirteenth switch S13, which is a ramp-type switch that gradually decreases with a ramp slope.

The thirteenth switch S13 may be connected to at least one of the (−) node of the fourth node n4, the fifth node n5, and the third capacitor C3. For this purpose, when the thirteenth switch S13 is turned on, the twelfth switch S12 should also be turned on.

As described above, the driving apparatus of the PDP according to the present invention can eliminate a large amount of high voltage switch elements used to pass the reset pulse and the sustain pulse, thereby simplifying the circuit configuration. The simple circuit configuration can lower the cost. In addition, since the sustain pulse is supplied to the panel in the shortest path, the inductance on the circuit can be reduced to increase driving efficiency.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

A reset voltage generator for generating a reset voltage; A sustain voltage generator connected to the reset voltage generator to generate a sustain voltage; A scan voltage generator connected to the reset voltage generator and the sustain voltage generator to generate a scan voltage; An electrode driver for supplying the reset voltage, the sustain voltage, and the scan voltage to a driving electrode; Switching elements positioned between both ends of the output terminal of the sustain voltage generator to form a signal transmission path between the reset voltage generator and the electrode driver, and to switch the signal transmission path between the sustain voltage generator and the electrode driver. And a driving apparatus of the plasma display panel. The method of claim 1, The sustain voltage generator is A first capacitor for charging a voltage recovered from the electrode driver; First and third switches connected in parallel to the first capacitor, A first diode and a first inductor connected in series between the first switch and the switching element; A second diode and a second inductor connected in series between the third switch and the switching element; A third diode and a second switch connected in series between the switching element and the ground terminal; And a fourth diode and a fourth switch connected in series between the switching element and the sustain voltage supply source. The method of claim 1, Located at the output terminal of the sustain voltage generator and the reset pulse generator to form a signal transmission path between the reset voltage generator and the electrode driver, the signal transfer path between the sustain voltage generator and the electrode driver is switched. And a switching device for driving the plasma display panel. The method of claim 3, wherein The sustain voltage generator is A capacitor for charging a voltage recovered from the electrode driver; First and third switches connected in parallel to the capacitor; An inductor connected between the second node and the third node, A fourth switch connected between the third node and a sustain voltage supply source, And a second switch connected between the third node and the ground terminal. The method of claim 3, wherein The reset driving unit A reset voltage driver for supplying a positive waveform reset signal of a ramp waveform to the driving electrode in a reset period; And a set-down driver for supplying a negative waveform signal of a ramp waveform to the driving electrode after the positive reset signal is supplied. A reset voltage generator for generating a reset voltage; A sustain voltage generator connected to the reset voltage generator to generate a sustain voltage; A scan voltage generator connected to the reset voltage generator and the sustain voltage generator to generate a scan voltage; And a switching device for supplying the sustain voltage, the scan voltage, and the reset voltage to a driving electrode in response to a control signal. And the switching device controls the reset voltage in response to the control signal supplied during a reset period.