KR100433234B1 - Method of Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel which can reduce mis-writing while reducing power consumption.

The driving method of the plasma display panel includes detecting a data pattern with high power consumption in an input image, and charging / discharging the energy recovery circuit by omitting at least one of a plurality of subfields preset in the data pattern. And extending the holding period of the reduced reference data pulse.

Description

Driving Method of Plasma Display Panel {Method of Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel that can reduce miswriting while reducing power consumption.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 11, and a lower substrate 16. An address electrode 17X is provided.

Each of the scan / sustain electrode 12Y and the common sustain electrode 12Z is formed of a transparent electrode, for example, Indium-Tin-Oxide (ITO).

Each of the scan / sustain electrode 12Y and the common sustain electrode 12Z is provided with a metal bus electrode 13 for reducing resistance.

An upper dielectric layer 14 and a passivation layer 15 are stacked on the upper substrate 11 on which the scan / sustain electrode 12Y and the common sustain electrode 12Z are formed. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The passivation layer 15 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 15, magnesium oxide (MgO) is usually used.

The lower dielectric layer 18 and the partition wall 19 are formed on the lower substrate 16 on which the address electrode 17X is formed, and the phosphor layer 20 is coated on the surfaces of the lower dielectric layer 18 and the partition wall 19.

The address electrode 17X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 13Z. The partition wall 19 is formed in parallel with the address electrode 17X to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 20 is excited by the ultraviolet rays generated during the plasma discharge. The visible light of red, green or blue is generated.

An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 11 and 16 and the partition wall 19.

The PDP is driven by dividing one frame into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

An integrated circuit (hereinafter, referred to as IC) for driving the electrodes 12Y, 12Z, and 17X of the PDP has a high voltage applied to the electrodes 12Y, 12Z, and 17X to cause a discharge. There is a disadvantage that the power consumption is large and expensive because it must be supplied. For example, each of the data drive ICs for driving the address electrodes 17X drives dozens of address electrode lines X and supplies data voltages of tens to hundreds of volts to each address electrode line X, thereby reducing power consumption. Big. The data drive IC 21 is mounted on the film 22 as shown in FIG. 2 so that the input terminal and the output terminal are bonded to the system board 23 and the PDP 20, that is, a chip on film (hereinafter referred to as "COF"). It is installed in the form of.

In order to reduce the cost of the data drive IC 21, it is necessary to increase the low voltage driving and increase the output port of the IC or reduce the size (or die size) of the IC. In the case of the PDP whose resolution is VGA, the number of address electrode lines X on the PDP 20 is 640 x 3 (RGB), which is a total of 1920.

In this VGA resolution PDP, assuming that there are 96 output pins of each of the data drive ICs 21, 20 data drive ICs 21 are required. When four 96-pin data drive ICs 21 are mounted on one film 22, one COF has 384 output ports. Therefore, five data driving COFs are required for the above-described VGA resolution PDP. Do.

If the output pins of each of the data drive ICs 21 are increased to 192, the number of data drive ICs 21 required for the PDP of VGA resolution is reduced to ten. In this case, if five data drive ICs 21 can be mounted on the film 22, the COF required for the PDP of VGA resolution is reduced to two. Therefore, as the number of COFs decreases, the costs of the PDP and data drive IC 21 can be lowered.

In order to drive the low voltage of the data drive IC 21 and increase the number of output pins, the power consumption of the data drive IC 21 should be considered. The 96- / 64-pin data drive ICs 21 allow for 2.5W / 2.1W power consumption, respectively. In order to reduce the power consumption of the data drive IC 21, low voltage driving and low current must be realized, but it is difficult to reduce the power consumption of the data drive IC 21 due to the overcurrent flowing in the PDP. For example, if a low-voltage drive of 40V is possible, the power consumption when 2A of current is consumed in a 40 ″ PDP is 80W since voltage (V) x current (I). Assuming that the number of data drive ICs required for this PDP is 20, the power consumption of each of the data drive ICs 21 is 4W, which exceeds the allowable power consumption of 2.5W of the 96-pin data drive IC.

In order to reduce the power consumption of such a data drive IC, the data drive IC employs an energy recovery circuit.

3 and 4 show a unit driver of a data drive IC employing an energy recovery circuit and its driving waveform.

Referring to FIG. 3, the unit driving unit of the conventional data drive IC uses an energy recovery circuit 31 for supplying a voltage to the address electrode line X using the voltage recovered from the PDP, and recovers energy depending on the presence or absence of data. And a data driver 32 for switching the voltage supplied from the circuit.

The energy recovery circuit 31 includes an external capacitor Cs for charging the voltage recovered from the PDP, first and third switches S1 and S3 connected in parallel to the external capacitor Cs, and first and third electrodes. An inductor L connected between the node between the switches S1 and S3 and the data driver 32, a second switch S2 connected between the external sustain voltage source Vs and the inductor L, and a base voltage source. A fourth switch S4 connected between the GND and the inductor L is provided.

The first switch S1 is turned on before data is supplied to form a current path between the external capacitor Cs and the address electrode line X of the PDP.

The second switch S2 is turned on at the time when the address electrode line X is charged to the sustain voltage level in the turn-on period of the first switch S1, so that the sustain voltage Vs is changed to the address electrode line of the PDP. X).

The third switch S3 is turned on immediately after the address discharge occurs in the PDP to form a discharge path between the address electrode line X and the external capacitor Cs. In the period when the third switch S3 is turned on, the external capacitor Cs charges the voltage recovered from the PDP.

The fourth switch S4 is turned on after charging of the external capacitor Cs is completed to maintain the voltage on the address electrode line X of the PDP at a base potential.

The inductor L forms an LC series resonant circuit together with the equivalent capacitance Cp of the PDP so that the address electrode line X of the PDP is charged with the resonance voltage during the first switch S1 is turned on. .

The data driver 32 includes a fifth switch S5 connected to the output terminal of the energy recovery circuit 31 and a sixth switch S6 connected between the fifth switch S5 and the ground voltage source GND. . The address electrode line X is connected to the output terminal between the fifth switch S5 and the sixth switch S6.

The fifth switch S5 is turned on during the data input period under the control of a control unit (not shown) to supply a voltage from the energy recovery circuit 31 to the address electrode line X of the PDP. . In addition, the fifth switch S5 is turned off in the absence of data to switch the voltage path between the energy recovery circuit 31 and the PDP.

The sixth switch S6 is turned on in the absence of data under the control of a controller (not shown) so that the voltage on the address electrode line X maintains the base voltage, while the sixth switch S6 is turned on in the period in which data is input. Is off.

When the energy recovery circuit 31 is employed in this way, the peak current recovered from the PDP is reduced and power consumption can be lowered because the voltage required for address discharge is supplied to the PDP using reactive power. In fact, the data drive IC employing the energy recovery circuit reduces the power consumption by up to 50% due to the peak current reduction than without the energy recovery circuit. However, when the energy recovery circuit 31 is employed, there is a problem that the time required for the address discharge becomes short as much as the charge / discharge period required for energy recovery. As can be seen from FIG. 4, when there is no energy recovery circuit, the rising time and the falling time of the data pulse are fast. When the energy recovery circuit is employed, the rising period T1 during which the address electrode line X of the PDP is charged to the data sustain voltage by the energy recovery circuit and the falling period during which the external capacitor is charged by the reactive power recovered from the PDP ( T3) is included in the data pulse. Here, the rising period T1 and the falling period T3 are about 200 to 300 ns. When the energy recovery circuit is employed during this rising period T1 and the falling period T3, the data sustain voltage holding period T2 contributing to the address discharge becomes shorter than when there is no energy recovery circuit.

In a single scan method in which the PDP is not dividedly driven at a panel size of 60 ″ requiring high-speed driving, data pulses required for address discharge are set to 1.4 microseconds or less. In this case, when the energy recovery circuit is employed in the data drive IC, as described above, the data sustain voltage holding period T2 is shortened, which causes a problem of erroneous discharge, that is, miswriting.

Accordingly, an object of the present invention is to provide a method of driving a PDP that can reduce miswriting while reducing power consumption.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a partially cut perspective view illustrating a chip on film bonded to the plasma display panel shown in FIG. 1.

3 is a circuit diagram showing a unit driver of a data drive integrated circuit employing a conventional energy recovery circuit;

4 is a waveform diagram showing a data pulse depending on whether an energy recovery circuit is employed.

5 is a waveform diagram of a data pulse and a scan pulse for explaining a method of driving a plasma display panel according to a first embodiment of the present invention.

6 is a flowchart showing step by step a control procedure of a method of driving a plasma display panel according to a second embodiment of the present invention;

7 is a plan view illustrating a data pattern in which power consumption is large.

8 is an equivalent circuit diagram of adjacent unit drive drivers.

<Description of Symbols for Main Parts of Drawings>

11: upper substrate 12Y: scan / sustain electrode

12Z: common sustain electrode 13: metal bus electrode

14 upper dielectric layer 15 protective film

16: lower substrate 17X: address electrode

18 lower dielectric layer 19 partition wall

20: fluorescent layer 31: energy recovery lightning

32: data driver

In order to achieve the above objects, a method of driving a PDP according to an embodiment of the present invention includes detecting a data pattern with high power consumption in an input image, and omitting at least one of a plurality of preset subfields in the data pattern. Thereby extending the retention period of the reference data pulse reduced by charging / discharging of the energy recovery circuit.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 8.

Referring to FIG. 5, the driving method of the PDP according to the present invention employs an energy recovery circuit to reduce power consumption of the data drive IC, and maintains the power period by the rising period T1 and the falling period T3 by the energy recovery circuit. In consideration of the decrease in (T2), increase the amplitude in the reference data pulse.

The data pulses typically rise to about 60 to 80 V at a reference potential of 0 V. Therefore, the data pulse has an amplitude of 60 to 80 volts. Compared with such a data pulse, the driving method of the PDP according to the present invention increases the amplitude of the data pulse to 70 to 90 V by adding an amplitude increase ΔA of about 10 V to the data pulse. When the amplitude A of the data pulse is increased in this manner, the voltage difference between the scan pulse and the data pulse becomes larger, so that the data pulse is divided by the rising period T1 and the falling period T3 added to the data pulse by the energy recovery circuit. Even if the holding period T2 is shortened, no false discharge occurs.

On the other hand, the scan pulse is generally lowered to 0V at 70 to 80V. Therefore, the amplitude of the scan pulse is 70 to 80 V. For low voltage driving of the data drive IC, instead of reducing the amplitude rise ΔA of the data pulses, the potential difference required for the address discharge can be made larger even when the amplitude of the scan pulse is further lowered to around -10 V. In this case, since the scan pulse is lowered to about -10 V at 70 to 80 V, the amplitude becomes larger as about 80 to 90 V.

6 to 8 illustrate a method of driving a PDP according to a second embodiment of the present invention.

Referring to FIG. 6, the driving method of the PDP according to the present invention includes a rising period T1 and a falling period T3 added by the adoption of an energy recovery circuit by reducing the number of subfields in a data pattern in which current is consumed. The retention period T3 of the data is reduced.

Steps S1 to S5 are processes for determining a pattern in which a large current is consumed in the PDP. Among the data patterns displayed on the PDP panel, the most current-consuming pattern is a pattern in which cells on and off are alternated between adjacent cells in the horizontal direction H and the vertical direction V as shown in FIG. 7. In detail, the unit driving unit of the data drive IC for driving one address electrode line X may include a push-pull between the data D1 and D2 and the base voltage source GND or the low potential common voltage, respectively, as shown in FIG. 8. It consists of two switch elements Q1, Q2 or Q3, Q4 connected in a push-pull form. When data D1 is supplied to the cell to be turned on and data D2 is not supplied to the cell to be turned off adjacent thereto, the data D1 of the cell to be turned on is passed through the first switch element Q1 and the cell Cp of the PDP. It is supplied to the cell Cp of the PDP along the current path. The data D1 leaks to the base voltage source GND via the fourth switch element Q4 of the adjacent unit driver. Therefore, when the cells turned on and the cells turned off in the horizontal direction H and the vertical direction V alternately, the leakage current increases in the data driver IC, so that the power consumption of the data drive IC increases.

If it is determined in step S5 that the count value is a data pattern in which current is consumed more than the threshold value, the number of subfields included in one frame is reduced. (Step S6) When the number of subfields is reduced, the subfields are removed. The number of switching in the data drive IC is reduced, which reduces the switching loss of the data drive IC. The subfield to be removed is preferably selected as a subfield of low luminance relative ratio. This means that as the number of subfields is reduced, the range of gradation expression to be expressed may be reduced, but when the subfields with low luminance relative ratio which are hardly detected by the user due to the observer's visual perception are removed, the gradation expression and the deterioration of luminance level are reduced. Because it is small, there is little effect on the image quality.

In addition, the address period can be further increased by the subfield period omitted from one frame period (16.67 ms). Therefore, in the driving method of the PDP according to the present invention, the sustain period T2 of the data pulse is increased by the increased address period, whereby the writing operation can be stably performed.

Assuming that one frame includes 10 subfields in a high definition (HD) class PDP, the total address period required in one frame is 1008 since the address period required in one subfield is 1.4 μs × 720 lines = 1008 μs. 10 subfields = 0.08 ms. For a stable writing operation, when the pulse width of the data pulse is increased by 200 ns, the total address period required in one frame is 1.6 mu x 720 lines x 10 subfield = 11.5. When one subfield is reduced in the specific pattern of the above data, the number of switching of the data drive IC is reduced to reduce power consumption, and one subfield period is 400 μs (reset period) + 1008 μs (address period). ) + 100 μs (remaining period including sustain period, rest period, etc.) ≒ 1.5 ms, so the width of data pulse can be increased by 200 ns, which enables stable writing. If the sustain period T2 of the data pulse is increased by 400 ns, two subfields are reduced.

If it is determined in step S5 that the count value is smaller than the threshold value and the current consumption is determined to be a relatively small data pattern, the number of preset subfields is maintained (step S7).

As described above, the driving method of the PDP according to the present invention is to adjust the amplitude of the data pulses in a specific pattern or to adjust the amplitude of the data pulses large in order to prevent miswriting due to the reduction of the sustain period of the data pulses in the data drive IC employing the energy recovery circuit. Reducing the number of subfields increases the duration of data pulses. Therefore, the driving method of the PDP according to the present invention can minimize miswriting while reducing power consumption of the data drive IC.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (3)

In a driving method of a plasma display panel including an energy recovery circuit, Detecting a data pattern with high power consumption in the input image; Omitting at least one of a plurality of preset subfields from the data pattern to extend a sustain period of a reference data pulse reduced by charging / discharging of the energy recovery circuit. Driving method. The method of claim 1, And wherein the omitted subfields have low luminance relative ratios. The method of claim 1, And the maintenance period of the reference data pulse is extended by at least 200 ns compared to the reference data pulse whose retention period is reduced by the adoption of the maintenance pulse.