KR100489876B1 - Plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel which can lower the power consumption and improve the brightness by adjusting the pulse width of the sustain waveform variably according to the load of the panel.

The plasma display panel is a plasma display panel driven by a sustain waveform generated using an energy recovery circuit, the plasma display panel comprising: a subfield mapping unit for mapping video data to subfields, and the video data mapped to the subfields; Load detection means for detecting the load of the panel for each subfield by using a signal, and outputting a switching signal having a wider width as the detected load is larger, and controlling the switching time of the energy recovery circuit by the time of the switching signal. A waveform generator is provided for setting the rising period of the sustain waveform.

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel and a method of driving the same. More particularly, the present invention relates to a plasma display panel capable of lowering power consumption and improving luminance by controlling sustain in accordance with the load of the panel.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a first electrode 30Y and a second electrode 30Z formed on the upper substrate 10, and an address formed on the lower substrate 18. An electrode 20X is provided. Each of the first electrode 30Y and the second electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and is formed on one edge of the transparent electrode. 13Y, 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the first electrode 30Y and the second electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in a direction crossing the first electrode 30Y and the second electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a plurality of setup periods in which the rising ramp waveform is supplied and a set-down period in which the falling ramp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

The sustain discharge of the AC surface discharge PDP thus driven requires a high voltage of several hundred volts or more. Therefore, an energy recovery apparatus is used to minimize the driving power required for the sustain discharge. The energy recovery apparatus recovers the voltage between the first electrode 30Y and the second electrode 30Z and uses the voltage recovered as the driving voltage at the next discharge.

3 is a view showing an energy recovery circuit formed on the first electrode to recover the sustain discharge voltage.

Referring to FIG. 3, the energy recovery circuit includes an inductor L connected between the panel capacitor Cp and the source capacitor Cs, and a first connected in parallel between the source capacitor Cs and the inductor L. FIG. And second and fourth switches S2 and S4 connected in parallel between the third switches S1 and S3 and the panel capacitor Cp and the inductor L. FIG.

The panel capacitor Cp equivalently represents the capacitance formed between the first electrode 30Y and the second electrode 30Z. The second switch S2 is connected to the reference voltage source Vs, and the fourth switch S4 is connected to the ground voltage source GND. The source capacitor Cs recovers and charges the voltage charged to the panel capacitor Cp during the sustain discharge, and supplies the charged voltage to the panel capacitor Cp again.

The source capacitor Cs has a capacitance value capable of charging a voltage of Vs / 2 corresponding to half of the reference voltage source Vs. The inductor L forms a resonance circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 control the flow of current. The energy recovery device formed on the second electrode 30Z is formed symmetrically with the energy recovery device formed on the first electrode 30Y around the panel capacitor Cp. Meanwhile, the first and second diodes D1 and D2 respectively installed between the first and second switches S1 and S2 and the inductor L prevent current from flowing in the reverse direction.

4 is a timing diagram and waveform diagrams illustrating on / off timing of the switches illustrated in FIG. 3 and output waveforms of the panel capacitor.

The operation process will be described in detail assuming that the panel capacitor Cp is charged with a voltage of 0 volts and the source capacitor Cs is charged with a voltage of Vs / 2 before the T1 period.

In the T1 period, the first switch S1 is turned on to form a current path from the source capacitor Cs to the first switch S1, the inductor L, and the panel capacitor Cp. When the current path is formed, the voltage of Vs / 2 charged in the source capacitor Cs is supplied to the panel capacitor Cp. At this time, since the inductor L and the panel capacitor Cp form a series resonant circuit, the panel capacitor Cp is charged with a Vs voltage that is twice the voltage of the source capacitor Cs.

In the T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, the voltage of the reference voltage source Vs is supplied to the first electrode Y (that is, the panel capacitor Cp). The voltage of the reference voltage source Vs supplied to the first electrode Y prevents the voltage of the panel capacitor Cp from falling below the reference voltage source Vs so that sustain discharge occurs normally. On the other hand, since the voltage of the panel capacitor Cp has risen to Vs in the period T1, the driving power supplied from the outside to minimize the sustain discharge is minimized.

In the T3 period, the first switch S1 is turned off. At this time, the first electrode Y maintains the voltage of the reference voltage source Vs for the period of T3. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the source capacitor Cs through the inductor L and the third switch S3 to charge the panel capacitor Cp. The voltage is recovered to the source capacitor Cs. At this time, the source capacitor Cs is charged with a voltage of Vs / 2.

In the T5 period, the third switch S3 is turned off and the fourth switch S4 is turned on. When the fourth switch S4 is turned on, a current path is formed between the panel capacitor Cp and the base voltage source GND, so that the voltage of the panel capacitor Cp drops to zero volts. In the T6 period, the state of T5 is maintained for a certain time. In fact, the AC driving pulses supplied to the first electrode Y and the second electrode Z are obtained by periodically repeating the periods T1 to T6.

However, in such a conventional energy recovery circuit, the voltage slope of the period T1, that is, the period in which the current is supplied to the panel capacitor Cp, varies depending on the load of the panel. In other words, when the load of the panel is large, that is, when many discharge cells are discharged, the voltage slope supplied to the panel capacitor Cp is lowered as shown in FIG. 5A. Therefore, the voltage of Vs is not supplied to the panel capacitor Cp during the period of T1 when the charged voltage is supplied to the source capacitor Cs, thereby increasing power consumption.

On the other hand, when the load of the panel is small, that is, when few discharge cells are discharged, the voltage slope supplied to the panel capacitor Cp becomes large as shown in FIG. 5B. Therefore, the voltage charged in the source capacitor Cs may rise to the voltage Vs during the period T1. However, when the switch timing of the energy recovery circuit is set to a case where the load of the panel is small, the luminance of the panel is lowered in the discharge pattern in which many discharge cells such as full white emit light.

Accordingly, an object of the present invention is to provide a PDP capable of lowering power consumption and improving luminance by controlling the sustain waveform in accordance with the load of the panel.

In order to achieve the above object, a PDP according to an embodiment of the present invention is a plasma display panel driven by a sustain waveform generated by using an energy recovery circuit, comprising: a subfield mapping unit for mapping video data to subfields; Load detection means for detecting a load of the panel for each subfield by using the video data mapped to the subfields, and outputting a switching signal having a wider width as the detected load is larger; And a waveform generator configured to control the switching time of the energy recovery circuit to set the rising period of the sustain waveform. The load detecting means detects a load of the panel using the video data mapped to the subfields, and outputs any one of n control signals in response to the detected load; and a ROM table for storing n switching signals and outputting a switching signal corresponding to the input control signal when any one of the n control signals is input. The load detecting means detects a load of a panel by using the video data mapped to the subfields, and outputs any one of n control signals corresponding to the detected load, and a predetermined value. A ROM table storing a switching signal having a width, n waveform parts for generating the n switching signals using the switching signal stored in the ROM table, and the n switching parts connected to the n waveform parts A multiplexer for outputting any one of the signals is provided. The multiplexer outputs a switching signal corresponding to the input control signal of the n switching signals when any one of the n control signals is input. The PDP according to another embodiment of the present invention uses an energy recovery circuit. A PDP driven by a generated sustain waveform, comprising: an average image value portion for generating an N (N is a natural number) signal for adjusting the number of pulses of a sustain waveform corresponding to video data, and J (J) in response to the N-stage signal; Is a waveform means for outputting any one of the number of switching signals, and receives any one of the J switching signals, and controls the switching time of the energy recovery circuit by the time of the input switching signal. A waveform generator for setting the rising period is provided. The waveform means outputs a first switching signal when the N-stage signal output from the average image value unit is the first stage signal, and has a stage where the N-stage signal output from the average image value unit is higher than the first stage. When the signal of the second stage is a second switching signal having a wider width than the first switching signal is output. The waveform means is a ROM table for storing any of the J switching signals and outputting any one of the J switching signals in response to a step of the input image signal. The waveform means includes: a ROM table in which a switching signal having a predetermined width is stored, J waveform portions for generating the J switching signals using the switching signals stored in the ROM table, and the J waveform portions. And a multiplexer for outputting any one of the J switching signals. The multiplexer receives the video signal and outputs any one of the J switching signals in response to a step of the received video signal. A driving method of a PDP according to an embodiment of the present invention is a method of driving a PDP driven by a sustain waveform generated using an energy recovery circuit, the method comprising: mapping video data to subfields and mapping to the subfields; Detecting a load of a panel for each subfield by using the received video data, outputting any one of n (n is a natural number) switching signals having different widths corresponding to the detected load; and controlling the switching time of the energy recovery circuit by the time of any one of the n switching signals to set the rising period of the sustain waveform. The greater the load of the panel, the wider the rising period of the sustain waveform. A driving method of a PDP according to another embodiment of the present invention is a driving method of a PDP driven by a sustain waveform generated using an energy recovery circuit, wherein the number of pulses of the sustain waveform corresponding to the video data is adjusted to N (N Is a natural number) signal, and outputs any one of J (J is a natural number) switching signals in response to the N-stage signal, and for the time of any one of the J switching signals. Controlling the switching time of the energy recovery circuit to set the rising period of the sustain waveform. The higher the N-stage signal, the wider the rising period of the sustain waveform.

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Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 9.

Fig. 6 is a diagram showing a driving device of a PDP according to the first embodiment of the present invention.

Referring to FIG. 6, the driving apparatus of the PDP according to the first embodiment of the present invention includes a first reverse gamma correction unit 42A, a gain control unit 44, connected between the input line 1 and the panel 56. An error diffusion unit 46, a subfield mapping unit 48, and a data alignment unit 50, a second inverse gamma correction unit 42B and an APL (Average) connected between the input line 1 and the panel 56; Picture Level: Average image value) unit 52 and waveform generator 54, subfield load detector 58 and ROM table 60 connected between subfield mapping unit 48 and waveform generator 54. FIG. ).

The first and second inverse gamma correction units 42A and 42B linearly convert the luminance value according to the gray value of the image signal by performing inverse gamma correction on the gamma corrected video signal.

The APL unit 52 receives the video data corrected by the second inverse gamma correction unit 42B and generates an N-stage signal for adjusting the number of sustain pulses. The gain control section 44 amplifies the video data corrected by the first inverse gamma correction section 42A by the effective gain.

The error diffusion unit 46 finely adjusts the luminance value by diffusing an error component of the cell into adjacent cells. The subfield mapping unit 48 maps the video data corrected by the error diffusion unit 46 for each subfield.

The data aligning unit 50 converts the video data input from the subfield mapping unit 48 in accordance with the resolution format of the panel 56 to form an address driving integrated circuit (IC) of the panel 56. Supply).

The subfield load detector 58 detects the load of the panel 56 by using the data mapped to each subfield in the subfield mapping unit 48. At this time, the subfield load detector 58 generates an n (n is a natural number) control signal in response to the detected load of the panel 56. The ROM table 60 supplies one of the n switching signals stored therein to the waveform generator 54 in response to an n-stage control signal input from the subfield load detector 58.

The waveform generator 54 generates a timing control signal based on the N-stage signal input from the APL unit 52 and the switching signal supplied from the ROM table 60, and generates the timing control signal into the address of the panel 56. Supply to driver IC, scan driver IC and sustain driver IC.

The operation of the subfield load detector 58 according to the first embodiment of the present invention will be described in detail as follows.

The subfield load detector 58 detects a load to be applied to the panel 56 by using data mapped to each subfield in the subfield mapping unit 48. In other words, when a lot of data is allocated for each subfield, the panel 56 has a high load. If less data is allocated for each subfield, the panel 56 has a low load. The subfield load detector 58 determines the load of the panel 56 using the data allocated for each subfield.

The subfield load detector 58 supplies one control signal of the n control signals to the ROM table 60 so as to correspond to the load of the panel 56 detected by the subfield load detector 58.

The ROM table 60 stores n switching signals so as to correspond to n control signals. For example, the ROM table 60 stores switching signals having a wide period from a narrow period, and transmits one switching signal to the waveform generator 54 in response to a control signal supplied from the subfield load detector 58. To supply.

In detail, the subfield load detector 58 supplies an i (i is a natural number) control signal to the ROM table 60 when the load of the panel 56 is large. The ROM table 60 supplied with the i control signal supplies the i switching signal corresponding to the i control signal to the waveform generator 54. At this time, the i switching signal has a wide period. On the other hand, the subfield load detector 58 supplies j (j is a natural number) control signal to the ROM table 60 when the load of the panel 56 is small. The ROM table 60 supplied with the j control signal supplies the j switching signal corresponding to the j control signal to the waveform generator 54. At this time, the period of the j switching signal has a period narrower than the period of the i switching signal. The switching signals supplied from the ROM table 60 to the waveform generator 54 are used as turn-on switching signals of the first switch S1 of the energy recovery circuit shown in FIG. 3.

The waveform generator 54 uses the switching signal supplied from the ROM table 60 as a turn-on switching signal of the first switch S1. Therefore, in the present invention, when the load of the panel 56 is high, a sufficient sustain pulse width is allocated so that the voltage supplied to the panel capacitor in the energy recovery circuit can rise to Vs, thereby reducing the power consumption of the PDP. In addition, the sustain pulse width is set narrow only when the load of the panel 56 is low, so that the luminance of the panel 56 is not reduced.

7 is a view showing a driving apparatus of a PDP according to a second embodiment of the present invention.

Referring to FIG. 7, the driving apparatus of the PDP according to the second embodiment of the present invention includes a first inverse gamma correcting unit 62A, a gain control unit 64, connected between the input line 1 and the panel 76; An error diffusion unit 66, a subfield mapping unit 68, and a data alignment unit 70, a second inverse gamma correction unit 62B and an APL (Average) connected between the input line 1 and the panel 76; Picture Level: Average image value) unit 72 and waveform generator 74, subfield load detector 78 and waveform units 82 connected between subfield mapping unit 68 and waveform generator 74 And 83 and 84, and the ROM table 80 connected to the corrugations 82, 83 and 84.

The first and second inverse gamma correction units 62A and 62B inversely gamma correct the gamma-corrected video signal to linearly convert luminance values according to grayscale values of the video signal.

The APL unit 72 receives the video data corrected by the second inverse gamma correction unit 62B and generates an N-stage signal for adjusting the number of sustain pulses. The gain control unit 64 amplifies the video data corrected by the first inverse gamma correction unit 62A by the effective gain.

The error diffusion unit 66 finely adjusts the luminance value by diffusing an error component of a cell into adjacent cells. The subfield mapping unit 68 maps the video data corrected by the error diffusion unit 66 for each subfield.

The data aligning unit 70 converts the video data input from the subfield mapping unit 68 according to the resolution format of the panel 76 to form an address driving integrated circuit (IC) of the panel 76. Supply).

The subfield load detector 78 detects the load of the panel 76 by using data mapped to each subfield in the subfield mapping unit 68. At this time, the subfield load detector 78 supplies a control signal of any one of the n control signals to the multiplexer 85 in accordance with the detected panel load.

The ROM table 80 stores one switching signal having a predetermined period. The first to nth waveform units 82 to 84 generate n switching signals having different periods using the switching signals stored in the ROM table 80. The MUX 85 supplies the waveform generator 74 with the output of any one of the outputs of the first to nth waveforms 82 to 84 using the control signal input from the subfield load detector 78.

The waveform generator 74 generates a timing control signal based on the N-stage signal input from the APL unit 52 and the switching signal supplied from the MUX 85, and drives the address of the panel 76 to generate the timing control signal. Supply to IC, scan driver IC and sustain driver IC.

The operation of the subfield load detector 78 according to the second embodiment of the present invention will be described in detail as follows.

The subfield load detector 78 detects a load to be applied to the panel 76 by using data mapped to each subfield in the subfield mapping unit 68. In other words, the panel 76 has a high load when a lot of data is allocated for each subfield, and the panel 76 has a low load when a little data is allocated for each subfield. The subfield load detector 78 determines the load of the panel 76 using the data allocated for each subfield. The subfield load detector 78 supplies the control signal of any one of the n control signals to the MUX 85 so as to correspond to the load of the panel 56 detected by the subfield load detector 78.

The ROM table 80 stores one switching signal having a predetermined period. The first to nth waveform units 82, 83, and 84 generate switching signals having different periods, respectively, by using one switching signal stored in the ROM table 80. Accordingly, n switching signals having different periods are generated in the first to nth waveform units 82, 83, and 84.

The MUX 85 supplies one of the n switching signals to the waveform generator 74 using the control signal supplied from the subfield load detector 78.

In detail, the subfield load detector 78 supplies an i (i is a natural number) control signal to the MUX 85 when the load of the panel 76 is large. The MUX 85 supplied with the i control signal supplies an i switching signal corresponding to the i control signal among the outputs of the first to nth waveforms 82, 83, and 84 to the waveform generator 74. At this time, the i switching signal has a wide period.

On the other hand, the subfield load detector 78 supplies the j (j is a natural number) control signal to the MUX 85 when the load of the panel 76 is small. The MUX 85 supplied with the j control signal supplies the j switching signal corresponding to the j control signal to the waveform generator 74. At this time, the period of the j switching signal has a period narrower than the period of the i switching signal. The switching signals supplied from the MUX 85 to the waveform generator 74 are used as turn-on switching signals of the first switch S1 of the energy recovery circuit shown in FIG. 3.

The waveform generator 74 uses the switching signal supplied from the MUX 85 as the turn-on switching signal of the first switch S1. Therefore, in the present invention, when the load of the panel 76 is high, a sufficient sustain pulse width is allocated so that the voltage supplied to the panel capacitor in the energy recovery circuit can rise to Vs, thereby reducing the power consumption of the PDP. In addition, the sustain pulse width is set narrow only when the load of the panel 76 is low, so that the luminance of the panel 76 is not reduced.

8 is a diagram showing a driving apparatus of a PDP according to a third embodiment of the present invention.

Referring to FIG. 8, the driving apparatus of the PDP according to the third embodiment of the present invention includes a first reverse gamma correction unit 92A, a gain control unit 94, connected between the input line 1 and the panel 106; An error diffusion unit 96, a subfield mapping unit 98, and a data alignment unit 100, a second inverse gamma correction unit 92B and an APL (Average) connected between the input line 1 and the panel 106; Picture Level: Average image value) section 102, ROM table 108, and waveform generation section 104.

The first and second inverse gamma correction units 92A and 92B inversely gamma correct the gamma corrected video signal to linearly convert luminance values according to grayscale values of the video signal.

The APL unit 102 receives the video data corrected by the second inverse gamma correction unit 92B and generates an N-stage signal for adjusting the number of sustain pulses.

The gain control unit 94 amplifies the video data corrected by the first inverse gamma correction unit 92A by the effective gain.

The error diffusion unit 96 finely adjusts the luminance value by diffusing an error component of a cell into adjacent cells. The subfield mapping unit 98 maps the video data corrected by the error diffusion unit 96 for each subfield.

The data aligning unit 100 converts the video data input from the subfield mapping unit 98 according to the resolution format of the panel 106 to convert the address data into an integrated circuit (IC) of the panel 106. Supply).

The ROM table 108 supplies the waveform generator 104 with one of the switching signals having n different periods corresponding to the APL stage input from the APL unit 102.

The waveform generator 104 generates a timing control signal based on the N-stage signal input from the APL unit 102 and the switching signal supplied from the ROM table 108, and generates the timing control signal into the address of the panel 106. Supply to driver IC, scan driver IC and sustain driver IC.

The operation of the ROM table 108 according to the third embodiment of the present invention will be described in detail as follows. First, the APL unit 102 calculates an APL stage by using video data input from the second inverse gamma correction unit 92B. At this time, as the APL step increases, the number of sustain pulses decreases, and as the step decreases, the number of sustain pulses increases so that the power consumption consumed by the panel 106 is kept constant. In addition, the higher the APL step, the more discharge cells are turned on, and the lower the APL step, the fewer discharge cells are turned on.

In other words, the higher the APL step, the higher the load of the panel 106, and the lower the APL step, the lower the load of the panel 106. For example, when the APL step is divided into 256 steps, when the APL step of 256 steps is supplied to the waveform generator 104, full white is represented on the panel 106.

The ROM table 108 supplies a switching signal of any one of n step switching signals to the waveform generator 104 in response to the APL step input from the APL unit 102. Here, the ROM table 108 supplies a switching signal having a wide period as the APL step is higher to the waveform generator 104, and supplies a switching signal having a narrow period as the APL step is low to the waveform generator 104. do. The switching signals supplied from the ROM table 108 to the waveform generator 104 are used as turn-on switching signals of the first switch S1 of the energy recovery circuit shown in FIG. 3.

That is, in the third embodiment of the present invention, when the load of the panel 106 is high, a sufficient sustain pulse width is allocated so that the voltage supplied to the panel capacitor in the energy recovery circuit can be increased to Vs, and thus power consumption of the PDP. This is reduced. In addition, the sustain pulse width is set narrow only when the load of the panel 106 is low, so that the luminance of the panel 106 is not reduced.

9 is a diagram showing a driving apparatus of a PDP according to a fourth embodiment of the present invention.

Referring to FIG. 9, the driving apparatus of the PDP according to the fourth embodiment of the present invention includes a first reverse gamma correction unit 112A, a gain control unit 114, and a connection between the input line 1 and the panel 126. The error diffusion unit 116, the subfield mapping unit 118, and the data alignment unit 120, the second inverse gamma correction unit 112B and the APL (Average) connected between the input line 1 and the panel 126. Picture Level: Average image value) 122, ROM table 128, waveforms (129 to 131), MUX 132 and waveform generator 124 is provided.

The first and second inverse gamma correction units 112A and 112B linearly convert the luminance value according to the gray value of the image signal by performing inverse gamma correction on the gamma corrected video signal.

The APL unit 122 receives the video data corrected by the second inverse gamma correction unit 112B and generates an N-stage signal for adjusting the number of sustain pulses.

The gain controller 114 amplifies the video data corrected by the first inverse gamma correction unit 112A by the effective gain.

The error diffusion unit 116 finely adjusts the luminance value by diffusing an error component of a cell into adjacent cells. The subfield mapping unit 118 maps the video data corrected by the error diffusion unit 116 for each subfield.

The data aligning unit 120 converts the video data input from the subfield mapping unit 118 according to the resolution format of the panel 126 to convert the address data into an integrated circuit (IC) of the panel 126. Supply).

The ROM table 128 stores one switching signal having a predetermined period. The first to nth waveform units 129 to 131 generate n switching signals having different periods using the switching signals stored in the ROM table 128. The MUX 132 supplies an output of any one of the outputs of the first to nth waveform units 129 to 131 to the waveform generator 124 using the N-stage signal input from the APL unit 122.

The waveform generator 124 generates a timing control signal using the N-stage signal input from the APL unit 122 and the switching signal input from the MUX 132, and generates the timing control signal into the address of the panel 126. Supply to driver IC, scan driver IC and sustain driver IC.

Referring to the operation of the fourth embodiment of the present invention in detail as follows. First, the APL unit 122 calculates an APL step by using video data input from the second inverse gamma correction unit 112B. At this time, as the APL step increases, the number of sustain pulses decreases, and as the step decreases, the number of sustain pulses increases so that the power consumption of the panel 126 is kept constant. In addition, the higher the APL step, the more discharge cells are turned on, and the lower the APL step, the fewer discharge cells are turned on.

In other words, the higher the APL step, the higher the load of the panel 126, and the lower the APL step, the lower the load of the panel 126. For example, when the APL step is divided into 256 steps, when the APL step of 256 steps is supplied to the waveform generator 104, full white is represented on the panel 106. The N-phase signal output from the APL unit 122 is supplied to the waveform generator 124 and the MUX 132.

The ROM table 128 stores one switching signal having a predetermined period. The first to nth waveform units 129, 130, and 131 generate switching signals having different periods from each other using one switching signal stored in the ROM table 128. Accordingly, n switching signals having different periods are generated in the first to nth waveform units 129, 130, and 131.

The MUX 132 receives an N-stage signal input from the APL unit 122 and supplies one of the n switching signals to the waveform generator 124.

In detail, the APL unit 122 supplies the i-th signal of the N step to the MUX 132 and the waveform generator 124. The MUX 132 receiving the i th signal supplies the i switching signal corresponding to the i th signal among the outputs of the first to n th waveform units 129, 130, and 131 to the waveform generator 124. At this time, the i switching signal has a wide period.

Meanwhile, the APL unit 122 supplies the j-th signal, which is a lower signal than the i-th signal, to the MUX 85. The MUX 132 receiving the j th signal supplies the j switching signal corresponding to the j th signal to the waveform generator 124. At this time, the period of the j switching signal has a period narrower than the period of the i switching signal. The switching signals supplied from the MUX 132 to the waveform generator 124 are used as turn-on switching signals of the first switch S1 of the energy recovery circuit shown in FIG. 3.

The waveform generator 124 uses the switching signal supplied from the MUX 132 as a turn-on switching signal of the first switch S1. Therefore, in the present invention, when the load of the panel 126 is high, a sufficient sustain pulse width is allocated so that the voltage supplied to the panel capacitor in the energy recovery circuit can rise to Vs, thereby reducing the power consumption of the PDP. In addition, the sustain pulse width is set narrow only when the load of the panel 76 is low, so that the luminance of the panel 126 is not reduced.

As described above, according to the PDP and the driving method thereof, the rising time of the sustain waveform supplied to the panel capacitor equivalently formed by the first electrode and the second electrode according to the load of the panel is variably set. It is possible to reduce the power consumption of the plasma display panel and to improve luminance.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram showing a frame configuration of an 8 bit default code for implementing 256 gray levels.

3 is a circuit diagram showing an energy recovery circuit;

FIG. 4 is a diagram showing an operation timing diagram of the energy recovery circuit shown in FIG. 3 and a driving waveform applied thereto by the panel capacitor. FIG.

5A and 5B are waveform diagrams showing rise periods of sustain waveforms differently depending on the load of the panel;

Fig. 6 is a block diagram showing a driving device of the plasma display panel according to the first embodiment of the present invention.

Fig. 7 is a block diagram showing a driving device of a plasma display panel according to a second embodiment of the present invention.

8 is a block diagram showing an apparatus for driving a plasma display panel according to a third embodiment of the present invention.

9 is a block diagram showing a driving apparatus of a plasma display panel according to a fourth embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor layer 44, 64, 94, 114: gain control unit

42A, 42B, 62A, 62B, 92A, 92B, 112A, 112B: Inverse gamma correction unit

46,66,96,116: Error diffusion unit 48,68,98,118: Subfield mapping unit

50,70,100,120: Data alignment unit 52,72,102,122: APL unit

54,74,104,124: Waveform generator 56,76,106,126: Panel

58,78: subfield load detector 60,80: ROM table

82,128: high load waveform portion 84,130: low load waveform portion

108: waveform portion

Claims (14)

In a plasma display panel driven by a sustain waveform generated using an energy recovery circuit, A subfield mapping unit for mapping video data to subfields; Load detection means for detecting a load of the panel for each subfield by using the video data mapped to the subfields, and outputting a switching signal having a wider width as the detected load is larger; And a waveform generator configured to set the rising period of the sustain waveform by controlling the switching time of the energy recovery circuit by the time of the switching signal. delete The method of claim 1, The rod detecting means, A subfield load detector for detecting a load of the panel using the video data mapped to the subfields, and outputting any one of n control signals in response to the detected load; and a ROM table for storing n switching signals and outputting a switching signal corresponding to the input control signal when any one of the n control signals is input. The method of claim 1, The rod detecting means, A subfield load detector for detecting a load of the panel using the video data mapped to the subfields, and outputting any one of n control signals in response to the detected load; A ROM table storing a switching signal having a predetermined width; N waveform parts for generating the n switching signals using the switching signals stored in the ROM table; And a multiplexer connected to the n waveform parts for outputting any one of the n switching signals. The method of claim 4, wherein And the multiplexer outputs a switching signal corresponding to an input control signal of the n switching signals when any one of the n control signals is input. delete delete delete delete delete delete delete delete delete