KR20060021235A - Apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a driving device of a plasma display panel.

In the driving apparatus of the plasma display panel operating through an initialization period divided into a setup period and a setdown period, and an address and sustain period,

A scan driver for driving the scan electrodes including a first selector and a second selector, an energy recovery circuit for supplying a sustain voltage to the scan driver, and supplying a ramp waveform to the scan driver during the setup period A setup supply for supplying a falling ramp waveform to the scan driver during the set down period; The first selector selects the set down supply, and the second selector selects the setup supply.

In the present invention, the first and second selection units are used instead of the expensive and high breakdown voltage switching device of the plasma display panel. As a result, cost was reduced by omission of switching elements and reduction of board size, and the output waveform characteristics and circuit reliability were eliminated by distributing the load on each node point, eliminating errors in operating characteristics and optimizing the circuit configuration. Can have

Description

Apparatus for Driving Plasma Display Panel             

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 shows one frame of a conventional plasma display panel.

3 is a view showing a driving apparatus of a conventional plasma display panel.

4 is a view illustrating a process of supplying a reset waveform in the driving device shown in FIG. 3.

5 is a view showing a driving device of a plasma display panel according to an embodiment of the present invention;

5A illustrates a circuit operation of a driving apparatus of a plasma display panel according to an embodiment of the present invention.

5B illustrates a circuit operation of a driving apparatus of a plasma display panel according to an embodiment of the present invention.

5C illustrates a circuit operation of a driving apparatus of a plasma display panel according to an embodiment of the present invention.

5D illustrates a circuit operation of a driving apparatus of a plasma display panel according to an embodiment of the present invention.

FIG. 6 is a view illustrating a process of supplying a reset waveform in the driving device shown in FIG. 5.

The present invention relates to a driving device of a plasma display panel, and more particularly, to a driving device of a plasma display panel that can improve a heat generation problem by optimizing a set down circuit of a driving circuit.

Plasma Display Panels (hereinafter referred to as "PDPs") display an image including characters or graphics by emitting phosphors by ultraviolet rays of 147 nm generated upon discharge of He + Xe or Ne + Xe gas. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel. As shown in FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 30Y and a sustain electrode 30Z formed on the upper substrate 10, and an address formed on the lower substrate 18. An electrode 20X is provided.

Each of the scan electrode 30Y and the sustain electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrodes 13Y and 13Y are formed at one edge of the transparent electrode. 13Z). The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 on which the scan electrode 30Y and the sustain electrode 30Z are formed. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 protects the upper dielectric layer 14 from sputtering generated during plasma discharge and increases the emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The address electrode 20X is formed in the direction crossing the scan electrode 30Y and the sustain electrode 30Z. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed. The phosphor layer 26 is formed on the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 is formed to be parallel to the address electrode 20X to physically distinguish the discharge cells, and prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24. The image implementation method of the PDP having such a structure will be described in more detail with reference to FIG. 2.                         

2 is a view showing one frame of a conventional plasma display panel. As shown in FIG. 2, the three-electrode alternating surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. When the image is to be displayed in 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. Each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ in each subfield (where n = 0,1,2,3,4,5,6, 7) is increased in proportion. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized. Referring to FIG. 3, a driving device for implementing the image gray scale is described.

3 is a view showing a driving apparatus of a conventional plasma display panel. As shown in FIG. 3, a conventional scan electrode driving apparatus of a PDP includes a scan driver 52 for driving scan electrodes, an energy recovery circuit 40 for supplying a sustain voltage to the scan driver, and the setup period during the setup period. A setup supply 42 for supplying the rising ramp waveform to the scan driver and a setdown supply 47 for supplying the falling ramp waveform to the scan driver during the set down period. Further, a seventh switch Q7 connected between the first and second negative scan voltage supply parts 46 and 48, the scan reference voltage supply part 50, the setup supply part 42, and the scan driver 52, and A sixth switch Q6 connected between the setup supply unit 42 and the energy recovery circuit unit 40 is provided. Here, look at the process of supplying the reset waveform from the drive device as shown in FIG.

4 is a diagram illustrating a process of supplying a reset waveform in the driving apparatus shown in FIG. 3. As shown in FIG. 4, in the process of generating the setup and setdown voltages during the reset period, it is assumed that the voltage of the setup voltage source Vst is charged in the second capacitor C2. It is assumed that the sustain voltage Vs is supplied from the energy recovery circuit unit 40 to the first node point n1 at the turn-on time of the fifth switch Q5.

First, the fifth switch Q5 and the seventh switch Q7 are turned on during the setup period. At this time, the sustain voltage Vs is supplied from the energy recovery circuit unit 40. The sustain voltage Vs supplied from the energy recovery circuit unit 40 is transferred to the scan electrode lines Y1 to Ym via the internal diode of the sixth switch Q6, the seventh switch Q7, and the scan driver 52. Supplied. Therefore, the voltages of the scan electrode lines Y1 to Ym rise rapidly to Vs.

In addition, since the voltage of Vs is supplied to the negative terminal of the second capacitor C2, the second capacitor C2 supplies the voltage of Vs + Vst to the fifth switch Q5. The fifth switch Q5 supplies the voltage supplied from the second capacitor C2 to the first node point n1 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. do. The voltage applied to the first node point n1 with a predetermined slope is supplied to the scan electrode lines Y1 to Ym via the seventh switch Q7 and the scan driver 52. At this time, the rising ramp waveform Ramp-up is supplied to the scan electrode lines Y1 to Ym.

After the rising ramp waveform Ramp-up is supplied to the scan electrode lines Y1 to Ym, the fifth switch Q5 is turned off. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the energy recovery circuit unit 40 is applied to the first node point n1, so that the voltages of the scan electrode lines Y1 to Ym are Vs. Descends sharply.

Thereafter, the seventh switch Q7 is turned off and the tenth switch Q10 is turned on in the set-down period. The tenth switch Q10 controls the channel width by the second variable resistor VR2 installed at the front end thereof, and converts the voltage of the second node n2 into the write scan voltage -Vw (or the setdown voltage source). Descend with a slope. At this time, the ramp ramp down (Ramp-down) is supplied to the scan electrode lines (Y1 to Ym).

On the other hand, in the driving apparatus of the plasma display panel as described above, in the conventional technique, the voltage difference applied to the first node n1 and the second node n2 is largely generated. For this reason, the load on the seventh switch Q7 may be increased, which may cause an error in operation, and the manufacturing cost may be increased by using the seventh switch Q7 having a high breakdown voltage.

Accordingly, an object of the present invention is to solve the above problems, and to reduce the board by omitting a large breakdown voltage switching element, to provide an overall cost reduction. In addition, while making the same driving waveform as conventional, the purpose is to eliminate the errors caused by the operating characteristics of the switching element and to optimize the driving circuit.

The present invention provides a driving apparatus for a plasma display panel operating through an initialization period divided into a setup period and a setdown period, and an address and sustain period, comprising: a scan driver including a first selector and a second selector to drive scan electrodes; Energy recovery circuitry for supplying sustain voltage to scan driver; setup supply for supplying ramp ramp to scan driver during setup; setdown supply for supplying ramp ramp to scan driver during setdown And a first selector to select a set down supply, and a second selector to select the setup supply.

One end of the first selector and the other end of the second selector are connected to the scan electrode.

The first selector is turned on when the sustain voltage is maintained, and is connected to the other end of the first selector and the other end of the sustain voltage switch.

The first selection unit is turned on when the falling ramp waveform is supplied, and is connected to the other end of the first selection unit and one end of the set-down switch.

The second selector is turned on when the rising ramp waveform is supplied, and is connected to one end of the second selector and the other end of the setup switch.

The second selector is turned on during energy recovery and is connected to one end of the second selector and the other end of the second inductor.

The second selector is turned on when the ground is maintained and is connected to one end of the second selector and the other end of the ground switch.

One more inductor is installed in the energy recovery circuit, and is located between the second diode of the energy recovery circuit and the setup switch.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5 shows a driving apparatus of a plasma display panel according to the present invention.

As shown in FIG. 5, the driving apparatus of the plasma display panel according to the present invention includes a scan driver 90, an energy recovery circuit unit 60, a setup supply unit 70, and a setdown supply unit 80.

In more detail, the scan driver 90 includes a first selector 92 and a second selector 94, and one end of the first selector 92 and the second selector 94 are provided. The other end is connected to the scan electrodes to drive the scan electrodes.

The energy recovery circuit unit 60 supplies a sustain voltage Vs to the scan driver 90. A second inductor 67 is installed in the energy recovery circuit unit 60 and is located between the second diode 65 and the setup switch 75.

The setup supply unit 70 supplies the rising ramp waveform to the scan driver 90 during the setup period, and the setdown supply unit 80 supplies the ramp ramp waveform to the scan driver 90 during the setdown period.

The first selector 92 is connected to the other end of the first selector 92, the other end of the sustain voltage switch 68, and one end of the set-down switch 82.

The second selector 94 includes one end of the second selector 94 and the other end of the setup switch 75, the other end of the second inductor 67, and the other end of the ground switch 76. Is connected to.

Here, the process of supplying the reset waveform from the driving device is as shown in FIG. 6.

FIG. 6 is a diagram illustrating a process of supplying a reset waveform in the driving device shown in FIG. 5. As shown in FIG. 5, the process of generating the setup voltage Vst and the setdown voltage −Vy during the reset period assumes that the second capacitor 73 is charged with the sustain voltage Vst. It is assumed that the sustain voltage Vs is supplied from the energy recovery circuit unit 60 at the turn-on time of the setup switch 75.

First, as shown in FIG. 5A, the setup switch 75 and the second selector 94 are turned on during the setup period. At this time, the sustain voltage Vs is supplied from the energy recovery circuit unit 60. The sustain voltage Vs supplied from the energy recovery circuit unit 60 is supplied to the scan electrode lines Y1 to Ym via the switch 68 for the sustain voltage and the first selector 92 of the scan driver 90. do. Therefore, the voltages of the scan electrode lines Y1 to Ym rise rapidly to Vs.

In addition, since the sustain voltage Vs is supplied to the negative terminal of the second capacitor 73, the second capacitor 73 supplies a voltage of Vs + Vst to the setup switch 75. The setup switch 75 supplies the voltage supplied from the second capacitor 73 to the second node point 77 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. do. The voltage applied to the second node point 77 with a predetermined slope is supplied to the scan electrode lines Y1 to Ym via the second selector 94 of the scan driver 90. At this time, the rising ramp waveform Ramp-up is supplied to the scan electrode lines Y1 to Ym.

As shown in FIG. 5B, after the rising ramp waveform Ramp-up is supplied to the scan electrode lines Y1 to Ym, the setup switch 75 is turned off. When the setup switch () is turned off, only the voltage of Vs supplied from the energy recovery circuit unit 60 is applied to the first node point 69, so that the voltage of the scan electrode lines Y1 to Ym is set to Vs. Descends sharply

Thereafter, as shown in FIG. 5C, the second selector is turned off and the first selector 92 and the set-down switch 82 are turned on in the setdown period. The set-down switch 82 adjusts the channel width by the second variable resistor VR2 installed at its front end, and writes the voltage at the point of the third node 87 to the scan voltage (-Vy) (or the set-down voltage source). It descends with a predetermined inclination. At this time, the ramp ramp down (Ramp-down) is supplied to the scan electrode lines (Y1 to Ym).

Thereafter, as shown in FIG. 5D, energy recovery is performed while the switch 64 for energy recovery and ground maintenance are turned on with the second selector 94 of the scan driver 90 turned on.

In the prior art, since a specific switching element located between the node points is used, a specific switching element may be heavily loaded, which may cause an error in operation, and a manufacturing cost increases by using a specific element having a high breakdown voltage. .

However, the present invention saves cost by omitting expensive and high breakdown voltage switching elements, thereby reducing the board size. In addition, by distributing the load applied to each node point, the switching element can be eliminated, thereby optimizing the driving circuit.

As described above, it will be understood by those skilled in the art that the technical configuration of the present invention may be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the present invention uses the first and second selection units of the driving apparatus of the plasma display panel. This replaces the role of a switching device having a high breakdown voltage. Cost savings are avoided by eliminating expensive and high breakdown voltage switching elements, thereby reducing the board size. In addition, by distributing the load applied to each node point, the switching element can be eliminated, thereby optimizing the driving circuit.

Claims (8)

In the driving apparatus of the plasma display panel operating through an initialization period divided into a setup period and a setdown period, and an address and sustain period, A scan driver including a first selector and a second selector to drive the scan electrodes; An energy recovery circuit unit for supplying a sustain voltage to the scan driver; A setup supply unit for supplying a ramp ramp waveform to the scan driver during the setup period; A set down supply for supplying a falling ramp waveform to the scan driver during the set down period; Wherein the first selector selects the setdown supply and the second selector selects the setup supply. Driving device for a plasma display panel, characterized in that. The method of claim 1, One end of the first selector and the other end of the second selector are connected to the scan electrode. The method of claim 1, And the first selector is turned on when the sustain voltage is maintained and is connected to the other end of the first selector and the other end of the switch for sustain voltage. The method of claim 1, And the first selector is turned on when the falling ramp waveform is supplied and is connected to the other end of the first selector and one end of a set-down switch. The method of claim 1, And the second selector is turned on when the rising ramp waveform is supplied, and is connected to one end of the second selector and the other end of the setup switch. The method of claim 1, And the second selector is turned on when energy is recovered and is connected to one end of the second selector and the other end of the second inductor. The method of claim 1, And the second selector is turned on when the ground is maintained, and is connected to one end of the second selector and the other end of the ground switch. The method of claim 1, An inductor is installed in the energy recovery circuit, and is located between the second diode of the energy recovery circuit and the setup switch.

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