KR20060109558A - Driving apparatus for plasma display panel and method thereof - Google Patents

Abstract

A driving device of a plasma display panel and a driving method thereof are provided to reduce the manufacturing cost by using a scan driver IC(Integrated Circuit) for low voltage without using a scan driver IC for high voltage by decreasing rated voltage of the driver IC of a scan driving device. A driving device of a plasma display panel includes an energy recovery circuit(501) supplying or recovering energy to/from a scan electrode(Y) of a panel capacitor(C5); a setup voltage supply unit(502) feeding setup voltage to the scan electrode of the panel capacitor; a scan reference voltage supply unit(503) supplying scan reference voltage to the scan electrode of the panel capacitor by using the capacitor; a scan driver IC(520) connected among the scan reference voltage supply unit, the setup voltage supply unit, and the scan electrode of the panel capacitor to selectively supply the setup voltage and scan reference voltage to the scan electrode of the panel capacitor; a first switch(Q1) connected between the capacitor and a first common node, which is connected with the energy recovery circuit and the setup voltage supply unit in common; and a second switch(Q2) connected between the scan driver IC and a second common node, which is connected with the capacitor and the first switch in common.

Description

Driving apparatus for plasma display panel and driving method thereof {Driving Apparatus for Plasma Display Panel and Method

1 is an internal structure diagram of a discharge cell of a conventional three-electrode AC surface discharge PDP.

2 is a frame configuration diagram for driving a conventional plasma display panel.

3 is a conventional AC PDP driving waveform diagram.

4 is a waveform diagram of a scan driver and a sustain driver and a scan signal and a sustain signal of the present invention.

5 shows a waveform diagram of a scan driver and a sustain driver and a scan signal and a sustain signal of the present invention and a switch waveform diagram.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (hereinafter referred to as a 'PDP'), and more particularly, to a driving apparatus and a method of driving the same, which reduce manufacturing pressure by reducing the internal voltage of a drive integrated circuit of a scan driving circuit. It is about.

The PDP emits phosphors by 147 nm ultraviolet rays generated when the inert mixed gas such as He + Xe, Ne + Xe or He + Ne + Xe discharges to display images containing characters or graphics. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 shows the internal structure of a discharge cell of a three-electrode alternating surface discharge PDP. The lower substrate is rotated 90 degrees. The discharge cell includes a common electrode 103 and a scan electrode 104 formed on the upper substrate 101 and an address electrode 105 formed on the lower substrate 102. do. Here, the common electrode 103 and the scan electrode 104 are composed of the transparent electrodes 103a and 104a and the bus electrodes 103b and 104b. An upper dielectric layer 106a and a passivation layer 107 are formed on the upper substrate 10 on which the common electrode and the scan electrode are formed. The upper dielectric layer 106a accumulates wall charges generated during plasma discharge, and the protective film 107 prevents damage of the upper dielectric layer 106a due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 107, magnesium oxide (MgO) is usually used.

The lower dielectric layer 106b for wall charge accumulation is formed on the lower substrate 102 on which the address electrode 105 is formed. The partition 108 is formed on the lower dielectric layer 106b, and the phosphor 109 is applied to the surfaces of the lower dielectric layer 106b and the partition 108. The partition 108 prevents ultraviolet rays and visible rays generated by the discharge from leaking into adjacent discharge cells. The phosphor 109 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 101 and 102 and the partition 108.

The discharge cell of this structure is selected by the counter discharge between the address electrode 105 and the scan electrode 104, and then maintains the discharge by the surface discharge between the scan electrode and the common electrode 104,103. In such a discharge cell, the fluorescent material 109 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted to the outside of the cell. As a result, the discharge cells adjust the period during which the discharge is maintained to implement gray scale, and the PDP in which the discharge cells are arranged in a matrix form displays an image.

2 is a view showing one frame of a conventional plasma display panel. As shown in FIG. 2, when a picture is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges thereof are 2n in each subfield (where n = 0,1,2,3,4,5,6,7). Is increased by the ratio. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

3 is a conventional AC PDP driving waveform. Resetting the sustain period to make the same condition before the address discharge, the scan period for addressing the selected image data, and the cell that has undergone the address discharge and the undiscovered cell according to the image data. Each time is applied, a sustain section that generates a discharge and an erase section for erasing wall charges accumulated in the scan-sustain electrode of a cell that has undergone an address discharge during the sustain section are configured. The reset section is divided into a setup section and a setdown section.

In order to solve the above problems, the present invention provides a plasma display panel driving apparatus and a driving method thereof capable of reducing the breakdown voltage of a drive integrated circuit of a scan driving apparatus.

The present invention provides a driving device of a plasma display panel for solving the above problems is an energy recovery circuit for supplying or recovering energy to the scan electrode of the panel capacitor, a setup voltage supply unit for supplying a setup voltage to the scan electrode of the panel capacitor, capacitor A scan reference voltage supply unit supplying a scan reference voltage to the scan electrode of the panel capacitor using the scan capacitor, the scan reference voltage supply unit and the setup to selectively supply the setup voltage and the scan reference voltage to the scan electrode of the panel capacitor A scan drive integrated circuit connected between a voltage supply unit and a scan electrode of the panel capacitor, a first switch connected between the first common node and the capacitor connected in common with the energy recovery circuit and the setup voltage supply unit, and the capacitor and the first switch 2nd switch connected in common And a second switch connected between the common node and the scan drive integrated circuit.

In the plasma display panel, the scan drive integrated circuit may include a third switch and a second switch connected between a scan electrode of the panel capacitor and a third common node to which the setup voltage supply unit and the scan reference voltage supply unit are commonly connected. And a fourth switch connected between the scan electrodes of the panel capacitor.

In the plasma display panel, the second switch and the third switch are turned off when the setup voltage is supplied to the scan electrode of the panel capacitor.

The method for driving a plasma display panel according to the present invention comprises a first switch, a second switch, and a third switch connected in series on a first current path between a sustain voltage source and a scan electrode of a panel capacitor during a first period during a setup period. Simultaneously supplying a sustain voltage to the scan electrode of the panel capacitor and simultaneously turning off the second switch and the third switch during a second period of the set-up period, so that the second switch and the third switch Supplying a sustain voltage to a scan electrode of the panel capacitor through a body diode and supplying a setup voltage to the scan electrode of the panel capacitor through a second current path different from the first current path during a third period of the setup period. It includes a step.

The second switch and the third switch may be turned off when the setup voltage is supplied to the scan electrode of the panel capacitor.

Hereinafter, with reference to the drawings will be described in detail with respect to the present invention.

4 illustrates a driving device and a driving waveform of the plasma display panel according to an exemplary embodiment of the present invention.

The driving apparatus of the plasma display panel includes a scan driver 418 for driving the scan electrode Y and a sustain driver 407 for driving the sustain electrode Z.

The scan driver 418 supplies the setup voltage, the base voltage, the scan reference voltage, and the 1/2 sustain voltage Vs / 2 to the scan electrode Y of the panel capacitor C5, and the 1/2 sustain voltage Vs. / 2) is supplied to the sustain electrode Z of the panel capacitor C5, and -1/2 sustain voltage (-Vs / 2) is controlled to be supplied to the scan electrode Y of the panel capacitor C5. The scan driver 418 includes a first energy recovery circuit 401, a 1/2 sustain voltage supply unit 410, a first base voltage supply unit 411, a setup voltage supply unit 402, and a scan reference voltage supply unit 403. The scan drive integrated circuit 420 includes a scan voltage supply control unit 404, a set down voltage supply unit 405, and a first switch Q1. Here, the first energy recovery circuit 401, the 1/2 sustain voltage supply unit 410, the first base voltage supply unit 411, the capacitor C2 of the setup voltage supply unit 402, the first switch Q1, and 1. / 2, the sustain voltage supply controlling unit 416 is a first common node (N1) are commonly connected to a capacitor (C4) of the scan reference voltage supply unit 403, a scan voltage supply controlling unit 404, the set-down voltage supply unit 405 The scan driver integrated circuit 420 is commonly connected to the second common node N2.

The first energy recovery circuit 401 is composed of a capacitor C1, an inductor L1, third and fourth switches Q3 and Q4 and diodes D5 and D6, and the panel capacitor (C1) is used. In C5), the energy of the reactive power not contributing to the discharge is recovered, and the recovered energy is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor C5.

The setup voltage supply unit 402 includes a capacitor C2, a seventh switch Q7, and a variable resistor R7. In this case, the seventh switch Q7 is connected to the scan driver integrated circuit 420 and the ninth switch Q9 of the scan reference voltage supply unit 403. Such, The set-up voltage supply unit 402 uses a capacitor C2 to increase the ramp ramp with a predetermined slope from the 1/2 sustain voltage Vs / 2 to the peak voltage Vs / 2 + Vsetup during the setup period during the reset period. To supply.

The 1/2 sustain voltage supply unit 410 is composed of a diode D5 and a fifth switch Q5. The half sustain voltage supply unit 410 supplies a half sustain voltage (Vs / 2) to the scan electrode (Y) of the panel capacitor (C5) during the setup period during the reset period and the panel capacitor (S) during the sustain period. The half sustain voltage Vs / 2 is alternately supplied to the scan electrode Y and the sustain electrode Z of C5).

The scan reference voltage supply unit 403 includes eighth and ninth switches Q8 and Q9 and a capacitor C4 and scans the scan electrode Y of the panel capacitor C5 during the address period using the capacitor C4. The reference voltage Vsc is supplied.

The scan voltage supply control unit 404 is composed of a tenth switch Q10, and scan pulses having a -1/2 sustain voltage level (-Vs / 2) during the address period are scanned electrodes Y of the panel capacitor C5. In addition, the sustain voltage (-Vs / 2) is supplied to the scan electrode (Y) of the panel capacitor (C5) during the sustain period.

The setdown voltage supply unit 405 includes an eleventh switch Q11 and a variable resistor R11, and the setdown voltage is lowered to -1/2 sustain voltage (-Vs / 2) during the setdown period during the reset period. Control to be supplied to the scan electrode (Y) of C5).

The first base voltage supply unit 411 includes a sixth switch Q6 and supplies a base voltage to the scan electrode Y during the sustain period.

The first switch Q1 forms an energy supply path for supplying energy to the panel capacitor C5 and forms an energy recovery path for transferring energy from the panel capacitor C5 to the first energy recovery circuit 401.

The sustain driver 407 supplies a -1/2 sustain voltage (-Vs / 2) and a base voltage to the sustain electrode Z of the panel capacitor C5 during the sustain period, and the 1 / s supplied from the scan driver 418. The second sustain voltage Vs / 2 is controlled to be supplied to the sustain electrode Z of the panel capacitor C5. In addition, the sustain driver 407 supplies a -1/2 sustain voltage (-Vs) to the scan electrode Y of the panel capacitor C5 during the set down period, the address period, and the sustain period during the reset period. Such a sustain drive unit 407 is The second energy recovery circuit 413, the first-1/2 sustain voltage supply unit 414, the second-1/2 sustain voltage supply unit 419, the sustain bias supply unit 412, and the second base voltage supply unit 415. And -1/2 sustain voltage supply control unit 417 and 1/2 sustain voltage supply unit 416. Here, the second energy recovery circuit 413, the first-1/2 sustain voltage supply unit 414, the second base voltage supply unit 415, the -1/2 sustain voltage supply control unit 417, and the set-down voltage supply unit 405. ) And the scan voltage supply control unit 404 to the fourth common node N4. The second-1/2 sustain voltage supply unit 419, the sustain bias supply unit 412, the half sustain voltage supply control unit 416, the sustain electrode of the panel capacitor C5, and -1/2 sustain are connected in common. The voltage supply controller 417 is commonly connected to the fifth common node N5.

The second energy recovery circuit 413 is composed of a capacitor C3, an inductor L3, 22nd and 23nd switches Q22 and Q23, and diodes D3 and D4. In C5), the energy of the reactive power not contributing to the discharge is recovered, and the recovered energy is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor C5.

The sustain bias supply unit 412 includes eighteenth and nineteenth switches Q18 and Q19 and supplies a bias voltage to the sustain electrode Z to the panel capacitor C5 during the setdown period and the address period during the reset period.

The second 1/2 sustain voltage supply unit 419 includes a twenty-fourth switch Q24 and a variable resistor R24. When a voltage of -1 / 2Vs is applied at the beginning of the set-up period during the reset period, the variable resistor R24 is supplied to maintain the falling curve.

The first -1/2 sustain voltage supply unit 414 is constituted by the twenty-first switch Q21, and -1 / to the scan electrode Y of the panel capacitor C5 during the set down period, the address period and the sustain period during the reset period. 2 The sustain voltage (-Vs / 2) is supplied, and the -1/2 sustain voltage (-Vs / 2) is supplied to the sustain electrode Z of the panel capacitor C5 during the sustain period.

The second base voltage supply unit 415 is composed of a twentieth switch Q20 and supplies a base voltage to the scan electrode Z during the sustain period.

The 1/2 sustain voltage supply control unit 416 is configured of the sixteenth switch Q16 and controls the 1/2 sustain voltage Vs / 2 to be supplied to the sustain electrode Z of the panel capacitor C5.

The 1/2 sustain voltage supply control unit 417 is composed of a seventeenth switch Q17 so that the −1/2 sustain voltage (−Vs / 2) is supplied to the sustain electrode Z of the panel capacitor C5. To control.

The scan drive integrated circuit 420 includes an upper switch Q14 and a lower switch Q15, and controls a signal applied to the scan electrode Y.

Like this The switches are controlled by a control signal of a timing controller not shown in the figure.

The PDP driving apparatus in FIG. 4 supplies a setup voltage and a scan reference voltage to the scan electrodes of the panel capacitor C5, and alternately supplies 1/2 sustain voltage to the scan electrodes and the sustain electrodes of the panel capacitor. In addition to providing a 1/2 sustain voltage alternately to the scan driver for controlling the sustain voltage to be supplied to the scan electrode of the panel capacitor C5, and to the scan electrode and the sustain electrode of the panel capacitor C5. It is operated by a sustain driver which controls the sustain voltage to be supplied to the sustain electrode of the panel capacitor C5.

The drive of the AC PDP is divided into a reset section, an address section, a sustain section, and an erase section as in the driving waveform of FIG. At this time, the reset section is a section for initializing the entire state of the PDP panel to facilitate display.

The setup voltage of the reset section is usually a high voltage of 220V or more above the sustain DC voltage with the sustain voltage as the bias voltage. This high voltage is applied to the panel electrode via the scan driver integrated circuit.

The path 409 in which the setup voltage is applied to the electrode when the driving waveform of the reset period is applied is the scan electrode of the panel capacitor via the seventh switch Q7 and the fourteenth switch Q14 of the scan driver integrated circuit. Is applied to. In the path 408 in which the 1/2 sustain voltage is applied when the setup voltage is applied, the scan driver integrated circuit has a 1/2 sustain voltage via the diode D5, the fifth switch Q5, and the first switch Q1. Is applied to the source terminal of the fifteenth switch Q15. In FIG. 4, the rounded section shows that the setup voltage is divided by the fifteenth switch Q15.

As shown in FIG. 4, when the setup voltage is applied, the setup voltage is applied to the panel electrode C5 based on the source terminal of the first switch Q1. The entire setup voltage is applied to the lower end of the scan driver integrated circuit 406. As it all takes place, the lower switch Q15 rating of the scan driver integrated circuit 406 must be above the set-up voltage. As the rated voltage of the scan driver integrated circuit 406 increases, the device price also increases proportionally, resulting in an increase in the production cost of the driving circuit.

5 illustrates a driving apparatus of a plasma display panel and driving waveforms thereof and on / off timings of switches according to another exemplary embodiment of the present invention. Here, the rounded part shows that the setup voltage is divided.

As shown in FIG. 5, the driving apparatus of the PDP includes a scan driver 518 and a sustain driver 507. Since the sustain driver 507 is the same as the sustain driver 407 of FIG. 4, the detailed description will be replaced with the above description.

The scan driver 518 supplies the setup voltage, the base voltage, the scan reference voltage, and the 1/2 sustain voltage (Vs / 2) to the scan electrode Y of the panel capacitor C5, and the 1/2 sustain voltage ( Vs / 2) is supplied to the sustain electrode Z of the panel capacitor C5, and -1/2 sustain voltage (-Vs / 2) is controlled to be supplied to the scan electrode Y of the panel capacitor C5. The scan driver 518 includes a first energy recovery circuit 501, a 1/2 sustain voltage supply unit 510, a first base voltage supply unit 511, a setup voltage supply unit 502, and a scan reference voltage supply unit 503. The scan drive integrated circuit 520 includes a scan voltage supply control unit 504, a set down voltage supply unit 505, a first switch Q1, and a second switch Q2.

Here, the remaining components except for the second switch Q2 are the same as the driving apparatus of the plasma display panel according to the exemplary embodiment of the present invention illustrated in FIG. 4, and thus, the detailed description will be replaced with the above description.

The second switch Q2 includes a second common node N2, a scan driver integrated circuit 520, and a scan voltage supply control unit to which the first switch Q1 and the capacitor C4 of the scan reference voltage supply unit 503 are commonly connected. 504 and the set-down voltage supply unit 505 are connected between the third common node N3 connected in common. This second switch Q2 is turned off when the setup voltage is applied and turns off when the application of the setup voltage is complete.

The path 509 in which the setup power is applied to the scan electrode Y of the panel panel capacitor C5 during the setup period among the reset periods is the same as the path 409 in FIG. 4.

FIG. 5 illustrates a path 508 in which 1/2 sustain power is applied in the setup section during the reset section. The half sustain power is applied to the source terminal of the first switch Q1 via the diode D5 and the fifth switch Q5 in the setup period during the reset period. At this time, the fifth switch Q5 and the first switch Q1 are turned on, and the second switch Q2 and the fifteenth switch Q15 are turned off.

 In order to maintain this path, when the setup voltage is applied in the reset section, the switch Q14 of the upper end of the scan driver integrated circuit 506 is turned on, and the switch Q15 of the lower end of the scan driver integrated circuit 506 is turned on. At the same time, the second switch Q7 is turned off. In this case, a setup voltage is applied between the source terminal of the second switch Q2 and the source terminal of the upper end of the scan driver integrated circuit 506, so that the setup voltage is set up at the switch of the second switch Q2 and the lower end of the scan driver integrated circuit 506. The voltage is divided evenly. Accordingly, the scan driver integrated circuit 506 can use switches having a breakdown voltage lower than the setup voltage, thereby reducing the cost of the driving circuit.

In other words, since the second switch Q2 uses a voltage of Vs / 2, the price increase effect is not great, and the cost of the second switch Q2 is reduced due to the reduced voltage resistance of the scan driver integrated circuit 506. In addition, since the breakdown voltage rating of the first switch Q1 of the path 508 to which 1/2 sustain power is applied due to the second switch Q2 is reduced by half from Vs to Vs / 2 of the existing circuit, low-cost performance The use of a good device has the effect of operating the scan drive circuit more stably.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Accordingly, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

According to the present invention, by reducing the rated voltage of the drive integrated circuit of the scan driving device in the plasma display panel, it is possible to use a low voltage scan driver integrated circuit as compared to the conventional driving device, thereby reducing the production cost.

Claims (5)

An energy recovery circuit for supplying or recovering energy to the scan electrode of the panel capacitor; A setup voltage supply unit supplying a setup voltage to the scan electrode of the panel capacitor; A scan reference voltage supply unit supplying a scan reference voltage to the scan electrode of the panel capacitor using a capacitor; A scan drive integrated circuit connected between the scan reference voltage supply unit, the setup voltage supply unit, and the scan electrode of the panel capacitor to selectively supply the setup voltage and the scan reference voltage to the scan electrode of the panel capacitor; A first switch connected between the capacitor and the first common node to which the energy recovery circuit and the setup voltage supply unit are commonly connected; And And a second switch connected between the second common node and the scan drive integrated circuit to which the capacitor and the first switch are connected in common. The method of claim 1, The scan drive integrated circuit A third switch connected between a third common node to which the setup voltage supply unit and the scan reference voltage supply unit are commonly connected, and a scan electrode of the panel capacitor; And And a fourth switch connected between the second switch and the scan electrode of the panel capacitor. The method of claim 1, And the second switch and the third switch are turned off when the setup voltage is supplied to the scan electrode of the panel capacitor. During the first period of the setup period, the first switch, the second switch, and the third switch connected in series on the first current path between the sustain voltage source and the scan electrode of the panel capacitor are simultaneously turned on to scan electrodes of the panel capacitor. Supplying a sustain voltage to the battery; Simultaneously turning off the second switch and the third switch during a second period of the set-up period, and supplying a sustain voltage to the scan electrode of the panel capacitor through the body diodes of the second and third switches; And And supplying a setup voltage to a scan electrode of the panel capacitor through a second current path different from the first current path during a third period of the setup period. The method of claim 4, wherein And the second switch and the third switch are turned off when the setup voltage is supplied to the scan electrode of the panel capacitor.

Images