KR100746256B1 - Driving apparatus and method for plasma display panel - Google Patents

Abstract

An apparatus and a method for driving a PDP are provided to reduce manufacturing cost of the PDP by integrating a sustain voltage source for generating a voltage for sustain discharge with an address voltage source for generating an address pulse voltage. An apparatus for driving a PDP(Plasma Display Panel) includes a source voltage supply unit(41) and a boosting circuit(45). The source voltage supply unit supplies a first voltage(Vs/4) to scan and sustain electrode drivers so as to supply a voltage required for sustain discharge of the PDP. The boosting circuit supplies a second voltage having a voltage different from the first voltage to an address electrode driver using the first voltage from the source voltage supply unit in order to supply an address pulse type voltage to the PDP.

Description

Driving apparatus and driving method of plasma display panel {Driving Apparatus and Method for Plasma Display Panel}

1 is an exploded perspective view showing the structure of a conventional three-electrode AC surface discharge type plasma display panel.

2A is a view showing an example of a drive waveform according to the PDP driving method according to the prior art.

FIG. 2B is an overall schematic diagram of a power supply unit for supplying various voltages of the drive waveform as shown in FIG. 2A.

FIG. 2C is a diagram schematically showing a PDP driving apparatus including the above-described power supply unit and plasma display panel.

3A to 3C are schematic diagrams of a sustain pulse applying circuit, a sustain pulse waveform, and a PDP driving apparatus according to the prior art using a Vs / 4 power supply.

4 is a view schematically showing a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 5 is an example of the circuit which shows the detailed structure of the boosting circuit shown in FIG.

6A and 6B illustrate the operation of the boost circuit shown in FIG. 5 in detail.

The present invention relates to a driving apparatus and a driving method of a plasma display panel. More particularly, the present invention relates to a power supply for supplying a voltage for generating a voltage waveform required for sustain discharge and a power supply for supplying a voltage for generating an address pulse voltage waveform. The present invention relates to a driving apparatus and a driving method of a plasma display panel that can solve the address voltage margin problem in a simple manner when integrated.

Plasma Display Pane (hereinafter, also referred to as 'PDP') is a display device using a phenomenon in which visible light is generated when ultraviolet rays generated by gas discharge excite phosphors. PDP has the advantages of being thinner and lighter than the cathode ray tube (CRT) and capable of realizing a high definition large screen. In general, the PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell corresponds to one subpixel of the screen.

1 is an exploded perspective view showing the structure of a conventional three-electrode AC surface discharge type plasma display panel. Referring to FIG. 1, each discharge cell has a scan electrode Y formed on the upper substrate 1, a sustain electrode Z, and an address electrode X formed on the lower substrate 9. The scan electrode (Y) and the sustain electrode (Z) are usually made of transparent indium-tin oxide (hereinafter referred to as 'ITO'), and in order to reduce the voltage drop due to their high resistance characteristics, Bus electrodes 3 made of at least one of metals such as Ag, Cu, Cr, and the like are respectively formed thereon.

The upper dielectric layer 4 and the passivation layer 5 are stacked on the upper substrate 1 having the scan electrode Y and the sustain electrode Z side by side. The protective film 5 is usually made of magnesium oxide (MgO) in order to prevent damage to the upper dielectric layer 4 by sputtering generated during plasma discharge and to improve emission efficiency of secondary electrons.

The lower dielectric layer 8 and the partition wall 6 are formed on the lower substrate 9 on which the address electrode X is formed, and the phosphor 7 is coated on the surfaces of the lower dielectric layer 8 and the partition wall 6. The address electrode X is formed in a direction perpendicular to the scan electrode Y and the sustain electrode Z, and the partition wall 6 is formed in a direction parallel to the address electrode X to generate ultraviolet and visible light generated by discharge. This prevents leakage to adjacent discharge cells. The phosphor 7 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red (R), green (G), and blue (B). In the discharge space provided by the upper substrate 1, the lower substrate 9, and the partition wall 6, Ne + Xe, a penning gas, and the like for gas discharge are sealed.

In the PDP having the above-described structure, the discharge cell is selected by the counter discharge between the address electrode X and the scan electrode Y, and then the discharge of the selected discharge cell is maintained by the surface discharge between the scan electrode Y and the sustain electrode Z. To be. In such a discharge cell, visible light is emitted to the outside of the cell by emitting the phosphor 7 by ultraviolet rays generated during the sustain discharge. As a result, the discharge cells adjust the period during which the discharge is maintained to implement gray scale, and the PDP in which the discharge cells are arranged in a matrix form can display an image.

2A is a view showing an example of a drive waveform according to the PDP driving method according to the prior art.

Referring to FIG. 2A, in the setup period SU of the reset period, a rising ramp waveform Ramp-up rising from approximately the sustain pulse voltage Vs to the setup voltage Vsetup is simultaneously supplied to all scan electrodes Y. do. At the same time, the ground voltage GND is supplied to the sustain electrode Z and the address electrode X. Due to the rising ramp waveform Ramp-up, a setup discharge occurs in a weak discharge between the scan electrode Y, the sustain electrode Z, and the address electrode X in the discharge cells of the full screen. As a result, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

In the setdown period SD of the reset period, a falling ramp waveform Ramp-down, which falls from approximately the sustain pulse voltage Vs to the base voltage or the negative setdown voltage (-Vsetdown), is simultaneously supplied to the scan electrodes Y. do. While the falling ramp waveform Ramp-down is supplied, the sustain electrode Z is supplied with a positive DC voltage Vdc (generally having the same magnitude as the sustain pulse voltage Vs), and the address electrode X ) Is supplied with a ground voltage GND. Due to the ramp ramp down, a setdown discharge occurs between the scan electrode Y, the sustain electrode Z, and the address electrode X with weak discharge, and the wall charges formed during the setup discharge by the setdown discharge. Excessive wall charges unnecessary for the address discharge are erased.

In the address period, the scan reference voltage Vsc is supplied, and generally, the base voltage or the negative scan pulse voltage -Vy is sequentially supplied to the scan electrodes Y, and the scan pulse voltage -Vy In synchronism with the application, the positive address pulse voltage Va is supplied to the address electrode X. As the voltage difference between the scan pulse voltage -Vy and the address pulse voltage Va and the wall voltage generated in the reset period are added, address discharge is generated in the cell to which the address pulse voltage Va is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain pulse voltage Vs is supplied in the sustain discharge period. The sustain electrode Z is continuously supplied with a positive DC voltage Vdc during the address period. Although the setdown voltage (-Vsetdown) and the scan pulse voltage (-Vy) are shown to have the same value in this drawing, in this case, an erase operation for uniformly leaving wall charges of the upper substrate necessary for address discharge for all discharge cells is performed. The setdown voltage (-Vsetdown) may be a voltage having a value different from the scan pulse voltage (-Vy) in some cases because it is difficult to achieve properly.

In the sustain discharge period, the sustain pulse voltage Vs is alternately supplied to the scan electrode Y and the sustain electrode Z. Each time the sustain pulse is applied, the cells selected by the address discharge are added with the wall voltage and the sustain pulse voltage Vs in the cell, and a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrode Z. do.

After the sustain discharge is completed, the erasing period may follow. In the erase period, an erase ramp waveform Ramp-er having a small pulse width and a low voltage level is supplied to, for example, the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

FIG. 2B is an overall schematic diagram of a power supply unit for supplying various voltages of the drive waveform as shown in FIG. 2A. FIG. 2B shows a power supply unit in the case where the setdown voltage (-Vsetdown) and the scan pulse voltage (-Vy) are the base voltages. The sustain pulse voltage Vs, the setup voltage Vsetup, the address pulse voltage Va, A plurality of stable DC voltages such as the scan reference voltage Vsc and the like are supplied to each drive device using the AC / DC converter 21 and the plurality of DC / DC converters 22, 23, 24, and 25. In addition, according to the conventional power supply unit, a standby voltage, 5V, 15V, or the like for use in a FET gate driving voltage for driving a transistor in a PDP logic block or a circuit of a PDP driving device through a separate DC / DC converter 26 is used. It also supplies voltage to the PDP.

FIG. 2C is a diagram schematically showing a PDP device including the above-described power supply unit and plasma display panel. For the sake of simplicity, only the case of supplying the sustain pulse voltage Vs and the address pulse voltage Va is shown in FIG.

As can be seen in FIG. 2C, a sustain pulse voltage Vs of about 180 to 200 V is supplied from the power supply unit 27 directly to the scan electrode driver or the sustain electrode driver 27, and the address electrode driver is conventionally provided. An address pulse voltage Va of about 50 to 60 V was supplied to (29). However, when the power supply for supplying the address pulse voltage Va is designed to have a smaller capacity than the power supply for sustain pulse voltage Vs, a dot pattern is turned on or off on the plasma display screen. In the case of displaying a real heavy pattern such as a pattern being turned on and off, the instantaneous peak power increases rapidly, which increases the cost of the power supply unit.

Therefore, in recent years, in order to reduce such a burden, a sustain pulse application circuit for alternately applying a sustain pulse to the scan electrode and the sustain electrode by using a voltage of Vs / 4 as shown in FIG. 3A is constructed. As shown in the drawing, a method of outputting a pulse having a voltage waveform required for sustain discharge to be composed of Vs / 2 and -Vs / 2 to the scan electrode and the sustain electrode has been proposed. Although the voltage (Vs) required for discharge in the actual sustain is formed at about 200 Vdc, the scan electrode and the sustain electrode driving device 32 for outputting the voltage of the pulse waveform composed of Vs / 2 and -Vs / 2 as described above are Since driving is possible only at 50V, the address pulse voltage Va can also be supplied by using the power supply unit 31 for supplying a voltage for generating the voltage Vs necessary for sustain discharge. That is, even if the PDP driving module is designed to remove the power supply terminal for supplying the address pulse voltage Va in the conventional power supply unit, as shown in FIG. 3C, only a single power is supplied from the power supply unit to scan electrode and sustain. The electrode driving device 32 and the address electrode driving device 33 can be driven. In this case, the power consumption required for the addressing discharge becomes small when the sustain discharge is maximum, as in the case of the full color pattern, and the power required for the sustained discharge becomes smaller when the power required for the addressing discharge is maximum. Even though the power supply is integrated, the power supply capacity can be realized at the level of conventional power supply capacity. Therefore, when the plasma display driving device is designed as shown in FIG. Removal is possible.

However, normally the address voltage Va is determined by the voltage resistance of the address driver IC (not shown) which performs the address margin and the addressing operation. Since it is usually used at about 50 to 60 V, the plasma display driving apparatus as shown in FIG. 3C is actually used. When applied to a PDP, there is a problem that address discharge becomes unstable if an address voltage margin is not sufficiently secured, which may adversely affect the performance and reliability of a product including a plasma display panel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and when the power supply for supplying a voltage for generating a voltage for sustain discharge and the power supply for supplying a voltage for generating a voltage of an address pulse waveform are integrated. It is an object of the present invention to provide a driving apparatus and a driving method of a plasma display panel in which performance and reliability are improved by adding a boosting circuit so as to solve an address voltage margin problem that may occur in itself.

The driving apparatus of the plasma display panel according to the first aspect of the present invention for achieving the above object is the first to the scan electrode driving device or the sustain electrode driving device in order to supply the voltage of the waveform required for sustain discharge to the plasma display panel. A power supply unit for supplying a voltage; And a boosting circuit for supplying a second voltage having a different magnitude from the first voltage to the address electrode driving device by using the first voltage from the power supply unit to supply a voltage of an address pulse waveform to the panel. Characterized in that made.

The boost circuit may further include a capacitor; A first switch supplied with the first voltage to one terminal and connected to one terminal of the capacitor; And a second switch having one terminal connected to a connection point of the first switch and the one terminal of the capacitor and the other terminal being grounded, more preferably, a difference between the second voltage and the first voltage. And a diode comprising an anode supplied with a third voltage having a size and a cathode connected to the other terminal of the capacitor.

In addition, the boosting circuit may include the first switch turned off and the second switch turned on to charge the capacitor to the third voltage during the sustain discharge period or the reset period, and the first switch turned on during the address period. And the second switch is turned off so that the second voltage is supplied from the other terminal of the capacitor to the address electrode driving device.

In addition, according to a second aspect of the present invention, there is provided a method of driving a plasma display panel, wherein the first switch is turned off and the second switch is turned on during a sustain discharge period or a reset period to turn on the capacitor. Charging to the third voltage; And turning on the first switch and turning off the second switch during an address period to supply the second voltage to the address electrode driving circuit from the other terminal of the capacitor.

In the driving device and method of driving the plasma display panel, the first voltage has a magnitude of 1/4 of a voltage required for sustain discharge, and the second voltage is 0V to 20V greater than the first voltage. Preferably, it has a large value of 5V or 15V, and the third voltage is supplied from the power supply unit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a view schematically showing a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention. In FIG. 4, only the case of supplying the voltage Vs and the address pulse voltage Va required for the sustain discharge to the plasma display panel is shown for convenience.

Referring to FIG. 4, a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention includes a power supply unit 41 and a scan electrode for supplying a voltage for generating various voltages for driving the plasma display panel 44. Or a scan electrode driver or sustain electrode driver 42 for supplying a voltage waveform necessary for sustain discharge to the sustain electrode, an address electrode driver 43 for supplying a voltage of an address pulse waveform to the address electrode, and the power supply Step-up circuit 45 for supplying the address pulse voltage Va to the address electrode driver 43 using the voltage Vs / 4 supplied from the unit to the scan electrode driver or the sustain electrode driver 42. It is made, including.

The power supply unit 41 scans a voltage Vs / 4 having a magnitude of 1/4 of the voltage Vs required for sustain discharge, that is, a voltage of 45 to 50 V. The scan electrode drive device or the sustain electrode drive device 42 And the scan electrode driving device or the sustain electrode driving device 42 are supplied to the plasma display panel 34 using the voltage Vs / 4 supplied from the power supply unit 41 as shown in FIG. 3B. Supply the voltage of the waveform required for sustain discharge consisting of / 2 and -Vs / 2.

The voltage booster circuit 45 boosts the voltage Vs / 4 supplied from the power supply unit 41 to the scan electrode drive device or the sustain electrode drive device 42 up to a maximum of 20V, and thus the address electrode drive device 43 ) To supply an address pulse voltage Va of about 50 to 65V.

FIG. 5 is an example of the circuit which shows the detailed structure of the boost circuit 45 shown in FIG.

4 and 5, according to the present invention, the boosting circuit 45 for supplying the address pulse voltage Va to the plasma display panel 44 receives a voltage of Vs / 4 from the power supply unit 41. A first switch Q1 to which one terminal is connected to a terminal to be supplied, a second switch Q2 to which one terminal is connected to the other terminal of the first switch Q1 and the other terminal is grounded, and the first It includes a capacitor (Cer) that one terminal is connected to the connection point of the switch (Q1) and the second switch (Q2).

In addition, the booster circuit 45 has an anode connected to the booster power supply 50 for boosting the voltage of Vs / 4 supplied from the power supply unit 41 by a constant booster voltage Ver, and the capacitor Cer And a diode (D) having a cathode connected to the other terminal of. The address pulse voltage (Va) is supplied to the address electrode driving device at the connection point of the capacitor (Cer) and the diode (D).

The operation of the boosting circuit having the configuration as described above will be described in detail below with reference to FIGS. 6A and 6B.

First, during the reset period or the sustain discharge period, as illustrated in FIG. 6A, the first switch Q1 is turned off and the second switch Q2 is turned on. When the first switch Q1 is turned off and the second switch Q2 is turned on, a current path is formed from the boosted power supply 50 through the diode D, the capacitor Ce, and the second switch Q2. The capacitor Cer is charged with a voltage having a magnitude corresponding to the boosted voltage Ver.

Thereafter, during the address period, as shown in FIG. 6B, the first switch Q1 is turned on and the second switch Q2 is turned off. When the first switch Q1 is turned on and the second switch Q2 is turned off, the current passes through the first switch Q1 and the capacitor Ce from the power supply unit 41 that supplies a voltage of Vs / 4. The path is formed, and in this case, since the booster voltage Ver is precharged in the capacitor Ce, the booster voltage Ver and the voltage of Vs / 4 are the address electrode driver 43 as the address pulse voltage Va. Is added, that is, a voltage of Ver + Vs / 4 is supplied.

As described above, if the driving device of the plasma display panel is configured to include the boosting circuit according to the present invention, the cost of the PDP device can be reduced by removing the address power supply terminal of the power supply unit, and the conventional Vs / Since the voltage can be boosted by a predetermined voltage and supplied to the address electrode driver, the address voltage margin problem can be solved. In addition, if the voltage (Vs / 4) for supplying the voltage (Vs) necessary for sustain discharge rises and the magnitude of the address pulse voltage (Va) is sufficient, the step-up operation may be stopped. Freedom is also secured.

Here, the magnitude of the boosted voltage Ver is sufficient to solve the address voltage margin problem, and as shown in FIG. 2B, a voltage of 5 V used in the PDP logic block from the power supply unit or plasma is used. A voltage of 15 V, which is the FET gate driving voltage in the driving circuit of the display panel, may be used. Therefore, in this case, it is possible to solve the address voltage margin problem by using a conventional power supply unit without requiring a separate power supply design for supplying a boosted voltage Ver.

According to the present invention, the address power stage of the power supply unit is eliminated by integrating a power supply for supplying a voltage for generating a voltage waveform required for sustain discharge and a power supply for supplying a voltage for generating an address pulse voltage waveform. Not only can the cost be reduced, but there is an effect that the address discharge can be stabilized by simply solving the address voltage margin problem that may occur when the driving device of the plasma display panel is configured in this manner.

Claims (16)

A power supply unit for supplying a first voltage to the scan electrode driving device or the sustain electrode driving device in order to supply a voltage of a waveform necessary for sustain discharge to the plasma display panel; And And a boosting circuit for supplying a second voltage having a different magnitude from the first voltage to the address electrode driving device by using the first voltage from the power supply unit to supply a voltage of an address pulse waveform to the panel. A driving apparatus of the plasma display panel, characterized in that made. The method of claim 1, And the first voltage has a size equal to 1/4 of a voltage required for sustain discharge. The method of claim 1, And the second voltage has a value of 0V to 20V greater than the first voltage. The method of claim 1, And wherein the second voltage has a value of 5 V greater than the first voltage. The method of claim 1, And the second voltage has a value of 15V greater than the first voltage. The method of claim 1, The boost circuit, Capacitors; A first switch supplied with the first voltage to one terminal and connected to one terminal of the capacitor; And And a second switch having one terminal connected to a connection point between the first switch and the one terminal of the capacitor and the other terminal being grounded. The method of claim 6, The boost circuit, And a diode comprising an anode supplied with a third voltage having a magnitude equal to the difference between the second voltage and the first voltage and a cathode connected to the other terminal of the capacitor. Drive of the panel. The method of claim 7, wherein And wherein the first switch is turned off and the second switch is turned on during the sustain discharge period or during the reset period, so that the capacitor is charged to the third voltage. The method of claim 7, wherein And the first switch is turned on during the address period, and the second switch is turned off so that the second voltage is supplied from the other terminal of the capacitor to the address electrode driving device. The method of claim 6, And the third voltage is supplied from the power supply unit. A method of driving a plasma display panel by using the driving apparatus of the plasma display panel according to claim 7, Charging the capacitor to the third voltage by turning off the first switch and turning on the second switch during a sustain discharge period or a reset period; And Turning on the first switch and turning off the second switch during an address period to supply the second voltage to the address electrode driving circuit from the other terminal of the capacitor. Driving method. The method of claim 11, And the first voltage has a size equal to 1/4 of a voltage required for sustain discharge. The method of claim 11, And the third voltage has a size of 0V to 20V. The method of claim 11, And the second voltage has a value of 5V greater than that of the first voltage. The method of claim 11, And wherein the second voltage has a value of 15V greater than that of the first voltage. The method of claim 11, And the third voltage is supplied from the power supply unit.

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