KR100421669B1 - Driving Method of Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel which can improve driving efficiency by dividing and driving a data electrode in a sustain period.

A driving method of a plasma display panel according to the present invention is a method of driving a plasma display panel in which one subfield is divided into a reset period, an address period, and a sustain period, wherein the data electrode is floated during the sustain period; It is characterized in that the driving is divided into a period for supplying a predetermined bias voltage to the data electrode.

According to this driving method, the driving method of the plasma display panel according to the present invention is operated by dividing the data electrode in the sustain period into a period in which the data electrode is floated and a period in which the bias voltage including the ground potential is supplied. The operating margin for addressing can be improved.

Description

Driving method of plasma display panel {Driving Method of Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel which can improve driving efficiency by dividing a data electrode in a sustain period.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when vacuum ultraviolet rays generated by gas discharge excite the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP includes scan electrodes 12Y and sustain electrodes 12Z formed on an upper substrate 10, and data formed on a lower substrate 18. An electrode 20X is provided.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases discharge efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the data electrode 20X is formed, and the phosphor layer 26 is coated on the lower dielectric layer 22 and the partition wall 24. The data electrode 20X is formed in the direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the data electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper substrate 10 / lower substrate 18 and the partition wall 24.

The PDP cell of this structure is selected by the counter discharge between the data electrode 20X and the scan electrode 12Y, and then maintains the discharge by the surface discharge between the scan electrode 12Y and the sustain electrode 12Z. In the PDP cell, the fluorescent substance 28 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted outside the cell. As a result, the PDP having cells displays an image. In this case, the PDP implements a gray scale required for displaying an image by adjusting the discharge sustain period of the cell, that is, the number of sustain discharges, according to the video data.

The PDP is driven by an ADS (Address and Display Preiod Separated) method in which one frame is divided into several subfields having a different number of discharge times in order to express gray levels of an image.

Each subfield is further divided into a reset period for uniformly causing discharge, an address period for selecting a discharge cell, and a sustain period for expressing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. Each of the eight subfields is further divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased. In this way, since the sustain period is different in each subfield, the gray level of the image can be expressed.

FIG. 2 is a driving waveform diagram for driving the PDP shown in FIG. 1.

Referring to FIG. 2, a driving waveform of a conventional PDP is largely expressed in four periods, and a reset period for uniformizing the initial condition of the panel to a desired state, an address period for selecting a discharge cell, and a gray scale according to the number of discharges. Is divided into a sustain period and an erase period for erasing the discharge.

The reset period is divided into a set-up period and a set-down period. In the setup period, the rising ramp waveform ramp1 is supplied to the scan electrode 12Y, and in the set down period, the ramp ramp waveform ram2 is supplied.

In the setup period, a weak reset discharge occurs due to the rising ramp waveform ramp1, and wall charges are accumulated in the cell.

In the set-down period, the wall ramp in the cell is appropriately erased by the falling ramp waveform ramp2 so that the wall charge is reduced to assist the next address discharge without causing an erroneous discharge. In addition, in order to reduce the wall charge, a positive DC voltage Vs is supplied to the sustain electrode 12Z in the set down period. When the scanning electrode 12Y supplied with the falling ramp waveform ramp2 becomes relative to the sustain electrode 12Z supplied with the positive DC voltage Vs, the negative electrode becomes relatively negative, that is, the polarity is reversed. The wall charges generated during the setup period are reduced.

In the address period, the negative scan voltage Vscan is supplied to the scan electrode 12Y, and the positive data pulse data is supplied to the data electrode 20X. This negative scan voltage Vscan has a form of falling from the positive voltage (+) to the ground potential. Then, in the cell to which the data pulse (data) is supplied, the address discharge occurs as the voltage corresponding to the voltage difference between the data pulse (data) and the scan voltage (Vscan) and the wall charge in the cell are added. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

In the sustain period, the sustain discharge is started in the discharge cells in which the triggering pulse TP is supplied to the scan electrode 12Y at the beginning to sufficiently wall charge in the address period. Subsequently, a sustain pulse SSUS having a width of about 2 to 3 kHz is alternately supplied to the scan electrode 12Y and the sustain electrode 12Z to maintain sustain discharge during the sustain period, thereby maintaining a desired gray scale. Is displayed.

In the erase period, the discharge pulse EP is supplied to the sustain electrode 12Z to stop the discharge. The erasing pulse EP has a ramp wave shape in which the light emission size is small and has a short pulse width for discharging the discharge. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

In the conventional PDP driving method, the voltage of the ground potential is supplied to the data electrode 20X from the data electrode driver 30 as shown in FIG. 3 during the sustain period.

3 is a circuit diagram illustrating a conventional data electrode driver 30.

Referring to FIG. 3, the data electrode driver 30 includes a first switch Q _H and a second switch connected in parallel to each of the data electrodes 20X in order to supply a data voltage to each of the data electrodes 20X. Q _L ).

The first switch Q _H and the second switch Q _L are turned on and off by receiving a driving signal from a controller (not shown). The first switch Q _H is connected to the data voltage source Va and the second switch Q _L is connected to the base voltage source GND.

During the sustain period, the gate terminal of the first switch Q _H receives a low driving signal from the controller, and the gate terminal of the second switch Q _L receives a high driving signal from the controller. The first switch is applied to the (Q _H) is a drive signal of a low state the first switch (Q _H) is turned off, the second switch when the drive signal of the high state applied to the (Q _L) a second switch (Q _L ) is turned on. Accordingly, the data electrode 20X is connected to the ground voltage source GND through the second switch Q _L to be at the ground potential and the bias state.

As described above, in the conventional PDP driving method, the data electrode 20X maintains the ground potential state during the sustain period. Since a high voltage pulse of about 200 V is alternately applied between the scan electrode 12Y and the sustain electrode 12Z, a predetermined amount is formed on the data electrode 20X formed at an interval of about 100 μm in height of the partition wall 24. Wall charges accumulate. At this time, half the wall voltage of the sustain voltage is accumulated on the data electrode 20X in the cell. This is because the scan electrodes 12Y and the sustain electrodes 12Z are alternately applied with the sustain voltage and the voltage of the ground potential. As a result, the reason why the wall voltage is formed on the data electrode 20X during the sustain period is because a ground potential is applied to the data electrode 20X itself.

Thus, when wall charge is formed on the data electrode 20X, there is a problem that the sustain discharge does not sufficiently occur and the discharge efficiency is lowered.

In order to solve this problem, a driving method for increasing the driving efficiency of the PDP by floating the data electrode 20X during the sustain period has been proposed. This is because sustain discharge is more efficiently generated when the data electrode 20X is not floated and the wall voltage is not accumulated rather than maintaining the ground potential at the data electrode 20X to accumulate wall charges.

On the other hand, in order to lower the stable address voltage, positive wall charges must be accumulated in the data electrode 20X before the address discharge is caused. For this purpose, it is preferable that a predetermined wall charge is accumulated on the data electrode 20X by maintaining the ground potential during the sustain period. Therefore, the sustain period needs a PDP driving method capable of satisfying opposite driving conditions.

Accordingly, an object of the present invention is to provide a driving method of a plasma display panel which can improve driving efficiency by dividing and driving a data electrode in a sustain period.

Another object of the present invention is to provide a method of driving a plasma display panel which can cause stable address discharge.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.

FIG. 2 is a drive waveform diagram for driving the PDP shown in FIG.

3 is a circuit diagram showing a conventional data electrode driver.

4 is a driving waveform diagram for driving a PDP according to an embodiment of the present invention;

5 is a circuit diagram illustrating a data electrode driver according to the present invention.

6 is a graph comparing changes in luminance between a driving method of a PDP and a conventional driving method according to an embodiment of the present invention.

7 is a graph comparing luminance according to time change of the present invention and a conventional driving method.

<Explanation of symbols for main parts of drawing>

10: upper substrate 12Y: scanning electrode

12Z: Sustain electrode 14: Dielectric layer

16: protective film 18: lower substrate

20X: Data electrode 24: Bulkhead

26: phosphor layer 30, 40: data electrode driver

In order to achieve the above object, a method of driving a plasma display panel according to the present invention is a method of driving a plasma display panel in which one subfield is divided into a reset period, an address period, and a sustain period. Driving is divided into a period for plotting and a period for supplying a predetermined bias voltage to the data electrode.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7.

4 is a driving waveform diagram for driving one subfield of a PDP according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the driving waveform of the PDP according to the present invention is largely four periods, and a reset period for uniformizing the initial condition of the panel to a desired state, an address period for selecting a discharge cell, and a gray scale according to the number of discharges. Is divided into a sustain period for expressing and an erase period for erasing the discharge.

The reset period is divided into a set-up period and a set-down period. In the set-up period, the rising ramp waveform ramp1 is supplied to the scan electrode 12Y, and in the set-down period, the rising ramp waveform ram2 is supplied.

In the setup period, a weak reset discharge occurs due to the rising ramp waveform ramp1, and wall charges are accumulated in the cell.

In the set-down period, the wall ramp in the cell is appropriately erased by the falling ramp waveform ramp2 so that the wall charge is reduced to assist the next address discharge without causing an erroneous discharge. In addition, in order to reduce the wall charge, a positive DC voltage Vs is supplied to the sustain electrode 12Z in the set down period. When the scanning electrode 12Y supplied with the falling ramp waveform ramp2 becomes relative to the sustain electrode 12Z supplied with the positive DC voltage Vs, the negative electrode becomes relatively negative, that is, the polarity is reversed. The wall charges generated during the setup period are reduced.

In the address period, the negative scan voltage Vscan is supplied to the scan electrode 12Y, and the positive data pulse data is supplied to the data electrode 20X. This negative scan voltage Vscan has a form of falling from the positive voltage (+) to the ground potential. Then, in the cell to which the data pulse (data) is supplied, the address discharge occurs as the voltage corresponding to the voltage difference between the data pulse (data) and the scan voltage (Vscan) and the wall charge in the cell are added. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

In the sustain period, the triggering pulse TP is supplied to the scan electrode 12Y at the start so that the sustain discharge starts in the discharge cells in which the wall charges are sufficiently formed in the address period. Subsequently, a sustain pulse SUSP having a width of about 2 to 3 kHz is supplied to the scan electrode 12Y and the sustain electrode 12Z to maintain the sustain discharge during the sustain period. At this time, the data electrode 20X is dividedly driven in the first half and the second half in order to increase the discharge efficiency in the cell.

5 is a circuit diagram showing the data electrode driver 40 for floating the data electrode 20X and supplying a voltage in a bias state during the sustain period according to the present invention.

Referring to FIG. 5, the data electrode driver 40 may include a first switch Q _H and a second switch connected in parallel to each of the data electrodes 20X in order to supply a data voltage to each of the data electrodes 20X. Q _L ).

The first switch Q _H and the second switch Q _L are turned on and off by receiving a driving signal from a controller (not shown). The first switch Q _H is connected to the data voltage source Va and the second switch Q _L is connected to the base voltage source GND.

In the first half of the sustain period, the gate terminal of the first switch Q _H and the second switch Q _L is supplied with a low driving signal from the control unit. A first switch (Q _H) and a second switch when the driving signal of low level applied to the (Q _L) of the first switch (Q _H) and a second switch (Q _L) is turned off. Therefore, the data electrode 20X is not connected to the data voltage Va and the ground voltage source GND. In other words, the data electrode 20X in the first half of the sustain period is in a floating state.

Subsequently, the driving terminal of the high state is supplied to the gate terminal of the second switch Q _L in the second half. The second switch when the drive signal of the high state on the (Q _L) is a second switch (Q _L) is turned on. At this time, the first switch Q _H maintains a turn-off state. Therefore, the data electrode 20X is connected to the ground voltage source GND. In other words, the data electrode 20X in the latter half of the sustain period is in a ground potential state.

The reason why the data electrode 20X is floated in the first half of the sustain period is to cause sufficient sustain discharge due to the floating state of the data electrode 20X while the scan electrode 12Y and the sustain electrode 12Z generate a discharge. . In other words, since the wall voltage is not accumulated by floating the data electrode 20X, the sustain discharge between the scan electrode 12Y and the sustain electrode 12Z occurs more efficiently.

In the second half of the following, the ground potential is maintained in the data electrode 20X because a positive wall voltage is accumulated on the data electrode 20X in advance before the address discharge is generated in conjunction with the reset period following the sustain period. This can be caused or lower the address voltage. In other words, in the second half, the ground potential is maintained to form a positive wall voltage on the surface of the data electrode 20X, which can help address discharge as in the prior art, and then finish the sustain discharge.

As the period in which the data electrode 20X is floated continues as in the first half of the sustain period, the discharge efficiency in the cell increases, and as the sustain time of the data electrode 20X at the ground potential continues in the second half, the data electrode ( The voltage accumulated at 20X) is stably accumulated. Therefore, the time t1 at which the floating state is switched to the ground potential can be adjusted to an appropriate time after driving a system not shown. In detail, after the sustain discharge (SUSP) of about 5 to 10 is applied to the scan electrode 12Y and the sustain electrode 12Z, the wall voltage is stably accumulated and at the data electrode 20X. Wall voltage also builds up stably.

Thus, the effect of dividing the sustain period is assured in the upper bit subfield to which a relatively long time is allocated. This is because the bias state including the floating period and the ground potential can be sufficiently driven. Therefore, a period in which 5 to 10 sustain pulses (SUSP) are supplied in the second half is sufficient.

In the lower bit sustain period, the division driving time may be insufficient. However, since the subfield period itself has little influence on the sustain driving efficiency, the sustain discharge efficiency can be improved by performing the division driving only in the upper bit sustain period.

In detail, the number of sustain pulses (SUSP) of the high bit subfield in the sustain period becomes thousands or more. This is enough time for the first half to be floated if it is the time when 5 to 10 sustain pulses (SUSP) are applied in the second half to maintain the ground potential. As a result, the data electrodes 20X may be floated to increase discharge efficiency, and stable discharge may be generated in subsequent reset periods and address periods.

In the erase period, the discharge pulse EP is supplied to the sustain electrode 12Z to stop the discharge. The erasing pulse EP has a lamp wave shape with a small light emission size and a short pulse width for erasing the discharge. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

6 is a graph illustrating a change in luminance according to a bias condition of a data electrode, for comparing luminance according to a driving method of the present invention and a driving method of the related art.

In FIG. 6, the luminance is higher when the data electrode 20X is floated as in the present invention than when the ground potential and the bias state are supplied to the data electrode 20X as in the prior art. In addition, it can be seen that it is higher than the case of supplying the bias voltage of Vs, Vs / 2, 0 to the data electrode 20X.

FIG. 7 is a graph illustrating a change in luminance with time, for comparing the luminance according to the driving method of the PDP and the conventional driving method according to an embodiment of the present invention.

In Fig. 7, it can be seen that the luminance when the data electrode 20X is floated as in the present invention is higher than the luminance when the ground potential is supplied to the data electrode 20 as in the prior art. In addition, it can be seen that the luminance decrease when the data electrode 20X is floated is lower than that when the voltage of the ground potential is supplied to the data electrode 20X.

As described above, the method of driving the plasma display panel according to the present invention is operated by dividing the data electrode in the sustain period into a period in which the data electrode is floated and a period in which the bias voltage including the ground potential is supplied, thereby increasing sustain discharge efficiency and providing stable addressing. It can improve the operating margin for.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

In a driving method of a plasma display panel which is driven by dividing one subfield into a reset period, an address period, and a sustain period, A period of floating the data electrode during the sustain period; And driving by dividing the data electrode into a period for supplying a predetermined bias voltage to the data electrode. The method of claim 1, And the predetermined bias voltage comprises a positive voltage and a ground voltage. The method of claim 1, And driving the data electrode by dividing the data electrode into a period for supplying a bias voltage and a period for supplying a bias voltage for each sustain period of the subfield. The method of claim 1, And driving the data electrode by dividing the data electrode into a period of floating the data electrode and a period of supplying a bias voltage only in the sustain period of an upper bit subfield. The method of claim 1, The period of supplying the bias voltage is set to supply about 5 to 10 sustain pulses for sustain discharge. The method of claim 1, And the period of floating the data electrode is longer than a period of supplying a predetermined bias voltage.