KR100351464B1 - Method of Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel to improve contrast in a selective erasing method.

The method for driving a plasma display panel according to the present invention is maintained for an initialization period for initializing a full screen, an address period for selectively turning off a discharge cell turned on in an initialization period, and discharge cells for which no address discharge has occurred. In the selective erasing driving method of a plasma display panel which displays an image divided by a sustain period for discharging, an initializing discharge is provided by supplying a lamp wave type initializing signal having a large pulse width and voltage level to the discharge cells once in an initializing period. It is characterized by performing.

According to the present invention, in the selective erasing method capable of high speed driving, the light emission during the reset period is minimized to improve the contrast.

Description

Driving Method of Plasma Display Panel {Method of Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to improve contrast in a selective erasing method.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. The PDP displays an image by adjusting the discharge period of each pixel. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 shows an AC PDP in which discharge cells are arranged in a matrix form. The pixel of the AC PDP includes a scan / sustain electrode 12a, a common sustain electrode 12b, metal bus electrodes 13a and 13b, an upper dielectric layer 14, and a protective film 16 formed on the upper substrate 10. And a lower plate having an address electrode 20, a lower dielectric layer 22, a partition wall 24, and a phosphor 26 formed on the lower substrate 18. The upper substrate 10 and the lower substrate 18 are spaced apart in parallel by the partition wall 24. The scan / sustain electrode 12a and the common sustain electrode 12b are formed side by side on the upper substrate 10. The metal bus electrodes 13a and 13b are formed on the scan / sustain electrode 12a and the common sustain electrode 12b to form the scan / sustain electrode 12a and the common sustain electrode 12b made of indium tin oxide. ) To reduce resistance. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective layer 16 not only prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, but also increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The address electrode 20 is formed to cross the scan / sustain electrode 12a and the common sustain electrode 12b. The data signal is supplied to this address electrode 20. The partition wall 24 is formed in parallel with the address electrode 20. The partition wall 24 prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells. The phosphor 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower plates and the partition wall.

Referring to FIG. 2, in the driving apparatus of an AC PDP, m × n discharge cells 1 have scan / sustain electrode lines Y1 to Ym, common sustain electrode lines Z1 to Zm, and address electrode lines. PDP 30 arranged in a matrix so as to be connected to the electrodes X1 to Xn, the scan / sustain electrode driver 32 for driving the scan / sustain electrode lines Y1 to Ym, and the common sustain electrode line. The sustain electrode driver 34 for driving the fields Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and the even-numbered address electrode lines X2, X4. And first and second address electrode drivers 36a and 36b for dividing and driving Xm-2 and Xm. The scan / sustain electrode driver 32 supplies scan pulses and sustain pulses sequentially to the scan / sustain electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × The discharge in each of the n discharge cells 1 is continued. The common sustain electrode driver 34 simultaneously supplies the sustain pulses to all of the common sustain electrode lines Z1 to Zn. The first and second address electrode drivers 36a and 36b supply image data to the address electrode lines X1 to Xm in synchronization with the scan pulse. The first address electrode driver 36a supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, while the second address electrode driver 36b is the even-numbered address. Image data is supplied to the electrode lines X2, X4, ..., Xn-2, Xn.

The AC PDP realizes gray levels by adjusting the amount of light depending on the discharge time. In other words, in the AC PDP, the discharge time is adjusted to change the contrast and chromaticity of the image. To this end, the AC type PDP is mainly used as a driving method of ADS (Addressing Display Separated). In the ADS-based PDP driving method, one frame is divided into a plurality of subfields according to the gray level to be implemented, and each subfield is divided into an address period and a sustain period different from each other. For example, when the image is to be displayed with 256 gray levels, the frame period corresponding to 1/60 second is divided into eight subfields SF1 to SF8. In addition, each of the eight subfields SF1 to SF8 is divided into an address period and a sustain period.

Such a driving method of the PDP is roughly classified into a selective writing method and a selective erasing method according to whether the discharge cell 1 to which the writing pulse WRS is supplied emits light.

In the selective write method, the discharge cells 1 to which the writing pulses WRS are supplied are turned on in the address period, and then sustain discharges and erase discharges are continuously generated in the discharge cells 1. In this selective writing method, since the discharge cell 1 having discharged in the previous frame and the discharge cell 1 having no discharge can coexist, the full screen is initialized before address discharge or writing discharge to equalize the electric field in all discharge cells. A reset discharge is required. However, in the selective writing method, since the width of the writing pulses WRS supplied to the address electrode lines X must be at least 3 μs in order to sufficiently form the wall charges, the address period including the syringes is long. have. That is, since the interval between the syringes of 3 µs or more is required for every scan / sustain electrode line Y, the sustain period, which is the display period, is shortened by that amount. Furthermore, as the resolution of the PDP increases, the amount of data increases, so that the length of the syringe becomes long within the limited frame period, while the sustain period that influences luminance is shortened by that much. For example, considering the red, green, and blue sub-discharge cells, 256 gray levels (8 bits), and 60 Hz frame frequency at a resolution of 1280 × 1024, the amount of data to be processed is 1.75 Gbits per second (1024 × 1280 ×). 3 x 8 x 60), 30 Mbits (1024 x 1280 x 3 x 8) per frame (16.67 ms for NTSC video signals), and 30 Kbits (1280 x 3 x 8) per address electrode line. The amount of data to be processed is increased proportionally.

In contrast to the selective write method, the selective erase method turns all the discharge cells 1 on, and then turns off the discharge cells 1 having the video data "0" in the address period. Turn-off). At this time, the remaining discharge cells 1 that are not turned off are sustained by sustain discharge. Accordingly, in every subfield, all the discharge cells 1 must be turned on by the lighting discharge. In the state where all the discharge cells 1 are turned on, the discharge cells 1 whose video data is "0" in the address period are turned off by the erase discharge. The pulse width for causing the erase discharge is approximately 1 to 2 s. Therefore, the selective erasing scheme enables high-speed driving, making it suitable for high resolution with a large amount of data to be processed. However, the selective erasing method turns on all the discharge cells 1 every frame by writing discharge, and then turns off only the discharge cells 1 whose video data is "0". The writing discharge of the discharge cells 1 should be stable. That is, all the discharge cells 1 turned on by the lighting discharge during full screen initialization must have the same wall charge quantity or electric field, but the walls accumulated in all the discharge cells 1 according to the discharge deviation of the previous frame or the previous subfield. The amount of charge or electric field may be different. In this case, even if an erase pulse is applied to the discharge cells 1 having the video data "0" in the address period, the turn-on state may be maintained according to the wall charge or the electric field in the discharge cells 1. You may be in an unstable state that may not be. In order to solve this problem, a pulse signal for stabilizing the lighting discharge is applied to the lighting discharge as shown in FIG. 3.

Referring to FIG. 3, the scan / sustain electrode lines Y are supplied with a slow ramp positive writing signal WRS in a reset period, and then a negative scan pulse (-SCP) is sequentially supplied in an address period. Supplied. In addition, the sustain pulse SUSP is commonly supplied to the scan / sustain electrode lines Y during the sustain period. The common sustain electrode line Z has a negative writing signal (-WRS) and a positive writing stabilization pulse (STP) inverted in phase with the writing signal WRS supplied to the scan / sustain electrode line Y in the reset period. Sequentially supplied, the sustain pulse SSUS is supplied sequentially in the sustain period. The positive electrode data pulse DP is supplied to the address electrode line X in synchronization with the scan pulse (-SCP).

First, writing pulses WRS and -WRS are simultaneously supplied to the scan / sustain pole lines Y and the common sustain electrode lines Z during a reset period. At this time, all the discharge cells 1 are discharged when the voltage difference between the scan / sustain electrode lines Y and the common sustain electrode lines Z increases and a discharge can occur. During writing discharge, wall charges are generated in the discharge spaces of all the discharge cells 1. On the dielectric layer 14 covered with the scan / sustain electrode lines Y according to the polarity of the writing pulses WRS and-WRS supplied to the scan / sustain electrode lines Y and the common sustain electrode lines Z. While negative wall charges are accumulated, positive wall charges are accumulated on the dielectric layer 14 covered by the common sustain electrode lines Z. By this writing discharge, the discharge cells 1 connected to the scan / sustain electrode lines Y to which the writing pulses WRS and -WRS are supplied and the common sustain electrode lines Z are turned on and emit light. .

Subsequently, the writing stabilization pulse STP is simultaneously supplied to the common sustain electrode lines Z. The lighting stabilization pulses STSUSP and -STSUSP cause the same amount of wall charge or electric field to be formed in all the discharge cells 1 by discharge. In other words, the writing discharge of all the selected discharge cells 1 may occur unevenly according to the discharge state of the previous frame or the previous subfield. In this case, the wall charge amount and the electric field generated for each of the discharge cells 1 may be different. The stabilization pulse STP uniformly discharges all the discharge cells 1 to stabilize the unstable discharge state during the lighting discharge. In detail, when the writing stabilization pulse STP is supplied to the scan / sustain electrode lines Y and the common sustain electrode lines Z, each of the discharge cells 1 generates wall charges and charged particles generated during the writing discharge. The wall voltage in the cell and the voltage caused by the lighting stabilization pulse (STP) are added. Accordingly, the discharge occurs between all the scan / sustain lines Y and the common sustain electrode lines Z even by the writing stabilization pulse STP having a level lower than the discharge start voltage. By this discharge, wall loads are generated at the same level in all the discharge cells 1. At this time, negative wall charges are accumulated in the scan / sustain electrode lines Y, while positive wall charges are accumulated in the common sustain electrode lines Z.

In the address period, the positive data pulse DP is supplied to the address electrode line X connected to the discharge cells having video data of "0". At the same time, scan pulses (-SCP) are supplied to the scan / sustain electrode lines (Y) connected to the corresponding discharge cells (1) so as to be synchronized with the data pulses (DP). As a result, the discharge cells having video data of "0" are turned off while address discharge occurs. That is, since the sum of the voltages formed by the wall charges and charged particles previously formed in the discharge cells 1 and the voltage formed by the two pulses DP and -SCP is lower than the discharge maintenance level, the corresponding discharge cells 1 In the interior, light emission stops after a weak erase discharge occurs.

In the sustain period, the sustain pulses SUSP are alternately supplied to the scan / sustain electrode lines Y and the common sustain electrode lines Z, so that the data pulses DP and scan pulses (-SCP) are not supplied. Discharges continuously in the cell. At the end of the sustain period, the negative erasing pulse (-EP) is supplied to the common sustain electrode lines Z to erase the discharges of all the discharge cells 1.

However, the selective erasing method has the advantage of being able to operate at high speed by a short scan pulse (-SCP), while the discharge occurs every time the writing signals WRS and -WRS and the stabilization pulse (STP) are supplied in the reset period. There is a problem that is lowered. In other words, since all the discharge cells 1 emit twice in the reset period, which is the non-display period, the black luminance level is increased. As a result, the difference between the black luminance level and the peak white level is reduced and the contrast is lowered.

Accordingly, it is an object of the present invention to provide a method of driving a PDP to improve contrast in a selective erase method.

1 is a perspective view showing one discharge cell of a conventional plasma display panel.

FIG. 2 is a block diagram illustrating an electrode arrangement and a driving unit of the plasma display panel shown in FIG. 1.

3 is a drive waveform diagram of a plasma display panel for explaining a conventional selective erasing scheme;

4 is a driving waveform diagram for explaining a method of driving a plasma display panel according to an embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12a: scan / sustain electrode 12b: common sustain electrode

13a, 13b: metal bus electrode 14: upper dielectric layer

16: protective film 18: lower substrate

20: address electrode 22: lower dielectric layer

24: partition 26: phosphor

In order to achieve the above object, the driving method of the PDP according to the present invention includes an initialization period for initializing the full screen, an address period for selectively turning off the discharge cells turned on in the initialization period, and a discharge without address discharge. In the selective erasing driving method of a plasma display panel which displays an image divided by a sustain period in which sustain discharge is performed with respect to the cells, an initializing signal of a ramp wave type having a large pulse width and voltage level in the initializing period is assigned to the discharge cells. It is characterized in that the initializing discharge is supplied in turn.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIG. 4.

4 is a driving waveform diagram of a PDP for explaining a method of driving a PDP according to an embodiment of the present invention.

Referring to FIG. 4, after the writing ramp signal HRS having a large pulse width and peak level is supplied to the scan / sustain electrode lines Y in the reset period, a negative scan pulse (-SCP) is provided in the address period. Are supplied sequentially. In addition, the sustain pulse SUSP is commonly supplied to the scan / sustain electrode lines Y during the sustain period. The ground voltage GND is supplied to the common sustain electrode line Z during the reset period and the address period, and the stabilization sustain pulse HSUSP having a large peak level in the sustain period and the sustain pulse SSUS having a relatively small peak level are provided. Are supplied sequentially. The positive electrode data pulse DP is supplied to the address electrode lines X to be synchronized with the scan pulse (-SCP) in the address period, and the positive electrode misalignment prevention is synchronized with the stabilization sustain pulse HSUSP in the sustain period. The pulse PMDP is supplied.

First, a ramp signal HRS having a sufficiently large pulse width and peak level is simultaneously supplied to each of the scan / sustain pole lines Y in the reset period. At this time, all the discharge cells 1 are discharged when the voltage difference between the scan / sustain electrode lines Y and the common sustain electrode lines Z increases and a discharge voltage can occur. During writing discharge, wall charges are generated in the discharge spaces of all the discharge cells 1. Negative wall charges are accumulated on the dielectric layer 14 covered by the scan / sustain electrode lines Y, while positive wall charges are accumulated on the dielectric layer 14 covered by the common sustain electrode lines Z. . At this time, the ramp signal HRS causing the lighting discharge continues to rise at a constant level even after the lighting discharge, thereby sufficiently generating wall charges in the discharge cells 1. By this writing discharge, all the discharge cells 1 are turned on and accumulate the same amount of wall charges.

In the address period, the positive data pulse DP is supplied to the address electrode line X connected to the discharge cells having video data of "0". At the same time, scan pulses (-SCP) are supplied to the scan / sustain electrode lines (Y) connected to the corresponding discharge cells (1) so as to be synchronized with the data pulses (DP). As a result, the discharge cells 1 whose video data is "0" are turned off while the address discharge occurs. In the dielectric layer 14 covering the scan / sustain electrode lines Y in the discharge cells 1 in which the address discharge has occurred, positive wall charges are accumulated while the dielectric layer 22 covering the address electrode lines X. Negative wall charges are accumulated. In contrast, a large amount of negative wall charges accumulated in the dielectric layer 14 covering the scan / sustain electrode lines Y in the discharge cells 1 in which the address discharge has not occurred, and the address electrode lines A large amount of positive wall charges are held in the dielectric layer 22 covering (X).

In the sustain period, first, the stabilizing sustain pulse HSUSP having a high peak level is supplied to the common sustain electrode lines Z. The common sustain electrode lines Z to which the stabilization sustain pulse HSUSP is supplied and the scan / sustain lines before supplying the base voltage GND are wall voltages in the discharge cells 1 in which no address discharge occurs. In addition, sustain discharge occurs. Here, when the stabilization sustain pulse HSUSP having a high peak level is supplied, sustain discharge may occur even in the discharge cells 1 in which the wall charge in the cell is not sufficient even though the address discharge does not occur. On the other hand, in the discharge cells 1 in which the address discharge has occurred, a large wall drop disappears during the address discharge, and thus, even when the stabilization sustain pulse HSUSP is applied to the discharge cells 1, the discharge cells 1 do not have a voltage difference. Since no discharge occurs. In particular, the negative wall charges accumulated in the dielectric layer 14 covered by the scan / sustain electrode lines Y of the discharge cells 1 in which the address discharge has occurred are converted to the positive wall charges, and thus the charged wall charges in the cells are changed. The amount will be significantly reduced. On the other hand, since the positive anti-discharge prevention pulse (PMDP) is supplied to the address electrode lines (X) in synchronization with the stabilization sustain pulse (HSUSP), it is discharged between the address electrode lines (X) and the common sustain electrode lines (Z). Since no voltage difference may occur, erroneous discharge between the address electrode lines X and the common sustain electrode lines Z is prevented. Subsequently, a sustain pulse SSUS having a fine sustain pulse level is alternately supplied to the scan / sustain electrode lines Y and the common sustain electrode lines Z. At this time, a sustain discharge is continuously generated between the scan / sustain electrode lines Y and the common sustain electrode lines Z according to the supplied sustain pulse SSUS. Finally, at the end of the sustain period, the positive erase lamp signal ERS is supplied to the common sustain electrode lines Z to erase the discharges of all the discharge cells 1.

As described above, the PDP driving method according to the present invention supplies the ramp signal having a large pulse width and peak level only once in the reset period in the selective erasing method. Accordingly, the driving method of the PDP according to the present invention improves the contrast by minimizing light emission occurring during the reset period in the selective erasing method capable of high speed driving.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

The image is divided into an initialization period for initializing the full screen, an address period for selectively turning off the discharge cells turned on in the initialization period, and a sustain period for sustain discharge for the discharge cells in which the address discharge has not occurred. In the selective erase driving method of the plasma display panel to display, And an initialization discharge by supplying a ramp wave type initialization signal having a large pulse width and voltage level to the discharge cells once in the initialization period. The method of claim 1, And the initialization signal is supplied to any one of the sustain electrode pairs. The method of claim 1, And setting the voltage level of the sustain pulse initially supplied in the sustain period to be greater than the sustain pulse supplied thereafter. The method of claim 3, wherein The first sustain pulse is supplied to any one of the sustain electrode pairs driving method of the plasma display panel. The method of claim 4, wherein And a pulse signal having the same polarity as the sustain pulse is supplied to an address electrode crossing the sustain electrode pair in synchronization with the first supplied sustain pulse.