KR100646241B1 - Driving apparatus for plasma display panel - Google Patents

Abstract

A plasma display panel driving device is provided to reduce the manufacturing cost by securing a stable driving operation while reducing the number of expensive switching elements. A plasma display panel driving device includes a drive IC(Integrated Circuit) unit(230) supplying driving voltage to a plasma display panel; an energy recovery circuit unit(200) supplying sustain voltage to the drive IC unit and recovering the voltage; and a setup supply unit(210) supplying a sustain-driving ramp-up waveform to the drive IC unit during a setup period. The setup supply unit comprises a switching element connected to a setup voltage source, and capacitors(C1~C3) of which one side is connected to the setup voltage source and arranged in parallel with the switching element and the other side is connected to the ground. The energy recovery circuit unit includes a ground voltage supply unit having switching elements connected in series.

Description

Plasma Display Panel Driving Device {Driving Apparatus for Plasma Display Panel}

1 is a driving waveform diagram showing a driving process of a general PDP.

2 is a block diagram illustrating a conventional plasma display panel driving apparatus.

3 is a timing diagram illustrating a switching operation of FIG. 2.

4 is a block diagram of a plasma display panel driving apparatus according to the present invention;

5 is a timing diagram showing a switching operation process according to the present invention.

<Description of the symbols for the main parts of the drawings>

200: energy recovery circuit

210: setup supply unit

220: scan driver

230: drive integrated circuit

2100: set down supply

2120: scan voltage supply unit

Q1 to Q15: FET switch

VR: Variable resistor

C1 ~ C3: Capacitor

The present invention relates to a plasma display panel driving apparatus, and more particularly, to a plasma display panel driving apparatus for maintaining a stable driving while reducing costs by reducing expensive switching elements.

In general, a plasma display panel (hereinafter referred to as "PDP") refers to a device for displaying an image including text or graphics by emitting phosphors by ultraviolet rays generated when the inert gas is discharged.

1 is a driving waveform diagram illustrating a driving process of a general PDP as described above.

As shown, the PDP is divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period (reset period), the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform causes discharge to occur in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. In the set-down period SD, after the rising ramp waveform is supplied, the positive voltage lower than the peak voltage of the rising ramp waveform begins to drop, and the falling ramp waveform Ramp- falls to the base voltage GND or a specific voltage level of the negative polarity. down) causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulse Scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied. The sustain electrode Z is supplied with a positive polarity DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference with the scan electrode Y so that an erroneous discharge with the scan electrode Y does not occur.

In the sustain period, a sustain pulse Su is applied to the scan electrodes Y and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrode Z every time the sustain pulse is applied.

After the sustain discharge is completed, a ramp waveform (Ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode (Z) to erase the wall charge remaining in the cells of the full screen.

FIG. 2 is a block diagram illustrating a conventional plasma display panel driving apparatus, and FIG. 3 is a timing diagram illustrating a switching operation of FIG. 2.

As shown in FIG. 2, the driving apparatus of the conventional PDP includes an energy recovery circuit unit 100, a setup supply unit 110, a scan reference voltage supply unit 120, a drive integrated circuit unit 130, a setdown supply unit 140, The scan voltage supply unit 150 is provided. In addition, the setup supply unit 110 includes a sixth switch Q6 connected between the energy recovery circuit unit 100, and a seventh switch Q7 is connected between the setup supply unit 110 and the drive integrated circuit unit 130. do.

The energy recovery circuit unit 100 includes a capacitor C1 for charging energy recovered from the panel Cp, an inductor L1 connected between the capacitor C1 and the drive integrated circuit unit 130, and an inductor L1. And a first switch Q1, a first diode D1, a second diode D2, and a second switch Q2 connected in parallel between the capacitor C1 and the capacitor C1.

Referring to the operation of the energy recovery circuit unit 100 as follows.

First, it is assumed that the capacitor C1 is charged with the voltage Vs / 2.

When the first switch Q1 is turned on, the voltage charged in the capacitor C1 is the first switch Q1, the first diode D1, the inductor L, the internal diodes of the sixth switch Q6, and the first voltage. 7 is supplied to the drive integrated circuit unit 130 via the switch Q7, and the drive integrated circuit unit 130 switches the voltage supplied thereto and supplies it to the panel Cp. In this case, since the inductor L1 forms a series LC resonant circuit together with the capacitance C of the PDP discharge cell, a voltage of Vs is supplied to the scan electrode line (not shown) of the panel Cp.

Thereafter, the third switch Q3 is turned on. When the third switch Q3 is turned on, the sustain voltage Vs is supplied to the drive integrated circuit 130 through the internal diode of the sixth switch Q6 and the seventh switch Q7. The drive integrated circuit unit 130 switches the sustain voltage supplied thereto to supply the panel Cp. Accordingly, the voltage level on the scan electrode line of the panel Cp is maintained by the sustain voltage Vs, and thus the sustain discharge occurs in the discharge cells.

After the sustain discharge occurs in the discharge cells, the second switch Q2 is turned on. When the second switch Q2 is turned on, the panel Cp, the drive integrated circuit unit 130, the internal diode of the seventh switch Q7, the sixth switch Q6, the inductor L1, and the second diode D2. And energy is recovered to the capacitor C1 via the second switch Q2. Subsequently, the fourth switch Q4 is turned on to maintain the voltage on the panel Cp at the ground GND level.

The energy recovery circuit unit 100 recovers energy from the PDP, and then supplies the voltage to the panel Cp again using the recovered energy to reduce excessive power consumption during the discharge during the setup period and the sustain period.

The setup supply unit 110 includes a fifth switch Q5 and a first variable resistor VR1 connected between the setup voltage source Vsetup and the first node n1, the setup voltage source Vsetup and the energy recovery circuit unit 100. And a second capacitor C2 provided therebetween. The second capacitor C2 adds the sustain voltage Vs supplied from the energy recovery circuit unit 100 and the voltage value of the setup voltage source Vsetup to the fifth switch Q5. The fifth switch Q5 is switched in response to a control signal (not shown) during the reset period of the selective write subfield WSF to supply the setup voltage to the first node n1.

The scan reference voltage supply unit 120 includes a third capacitor C3 connected between the reference voltage source Vsc and the second node n2, and an eighth connected between the reference voltage source Vsc and the second node n2. Switch Q8 and ninth switch Q9. The eighth switch Q8 and the ninth switch Q9 are switched by a control signal supplied from a timing controller (not shown) during the selective write and erase address periods, and drive the voltage of the reference voltage source Vsc to the drive integrated circuit unit 130. To supply. The third capacitor C3 adds the voltage applied to the second node n2 and the voltage value of the reference voltage source Vsc to the eighth switch Q8.

The drive integrated circuit unit 130 is connected in a push-pull form, and voltage signals from the energy recovery circuit unit 100, the setup supply unit 110, the set-down supply unit 140, the scan voltage supply unit 150, and the scan reference voltage supply unit 120 are applied. The fourteenth and fifteenth switches Q14 and Q15 are inputted. The output line between the fourteenth and fifteenth switches Q14, Q15 is connected to the panel Cp.

The set-down supply unit 140 includes a tenth switch Q10 connected between the second node n2 and the write scan voltage -Vyw. The set-down supply unit 140 gradually lowers the voltage supplied to the drive integrated circuit unit 130 to the write scan voltage -Vyw during the set-down period included in the reset period of the selective write subfield WSF. , Write scan voltage (-Vyw) is used as the set-down voltage source.)

The scan voltage supply unit 150 includes an eleventh switch Q11 connected between the second node n2 and the write scan voltage source -Vyw. The eleventh switch Q11 is switched in response to a control signal supplied from a timing controller not shown during the address period of the selective write subfield WSF to supply the write scan voltage -Vyw to the drive integrated circuit unit 130. .

Next, a process of generating setup and set-down voltages during the reset period will be described with reference to FIG. 3.

It is assumed that the second capacitor C2 is charged with the voltage of the setup voltage source Vsetup. It is assumed that the sustain voltage Vs is supplied from the energy recovery circuit unit 100 to the first node n1 at the turn-on time of the fifth switch Q5.

As shown in FIG. 3, first, the fifth switch Q5 and the seventh switch Q7 are turned on during the setup period. At this time, the sustain voltage Vs is supplied from the energy recovery circuit unit 100. The sustain voltage Vs supplied from the energy recovery circuit unit 100 is supplied to the panel Cp via the internal diode of the sixth switch Q6, the seventh switch Q7, and the drive integrated circuit unit 130. Therefore, the voltage of the panel Cp rises rapidly to Vs.

On the other hand, since the voltage of Vs is supplied to the negative terminal of the second capacitor C2, the second capacitor C2 supplies the voltage of Vs + Vsetup to the fifth switch Q5. The fifth switch Q5 supplies the voltage supplied from the second capacitor C2 to the first node n1 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. . The voltage applied to the first node n1 with a predetermined slope is supplied to the panel Cp via the seventh switch Q7 and the drive integrated circuit unit 130. Therefore, the rising ramp waveform Ramp-up is formed in the scan electrode line of the panel Cp.

As such, the fifth switch Q5 is turned off after the rising ramp waveform Ramp-up is supplied. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the energy recovery circuit unit 100 is applied to the first node n1. Accordingly, the voltage of the panel Cp drops rapidly to Vs.

Thereafter, the seventh switch Q7 is turned off and the tenth switch Q10 is turned on in the set down period. The tenth switch Q10 adjusts the channel width by the second variable resistor VR2 provided at the front end thereof, and writes the voltage of the second node n2 as a write scan voltage (-Vw) (or a setdown voltage source). Descend with a slope. At this time, a falling ramp waveform Ramp-down is formed in the panel Cp.

The setup supply unit 110 and the set-down supply unit 140 repeat the above process and supply the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the panel Cp during the reset period.

At this time, since the voltage difference between the voltages applied to the first node n1 and the second node n2 is large, a sixth switch Q6 having a high breakdown voltage is used. Here, the sixth switch Q6 prevents the Vsetup voltage from flowing into the energy recovery circuit unit 100.

On the other hand, a voltage of Vs is applied to the first node n1 and a write scan voltage (-Vyw) is applied to the second node n2 during the set-down period. Here, if the voltage of Vs is set to about 180V and the write scan voltage (-Vyw) is set to -70V, the sixth switch Q6 should have a breakdown voltage of about 300V in consideration of the actual driving voltage margin.

However, such a conventional PDP driving apparatus applies a high voltage reset pulse to one sustain electrode when driving a reset pulse, so that the peripheral elements must use a high breakdown voltage element. Therefore, there is a problem in that the manufacturing cost increases because a large number of rated voltage and high current switching devices must be used.

In addition, when the switching element is removed, there is a problem that technology development is difficult because a new driving method suitable for this is developed.

Accordingly, the present invention has been made to solve the above-mentioned problems, and provides a plasma display panel driving apparatus for maintaining a more stable driving by applying a conventional driving method while reducing costs by reducing expensive switching elements. Its purpose is to.

A plasma display panel driving apparatus according to the present invention for achieving the above object, the drive integrated circuit unit for supplying a drive voltage to the panel, the energy recovery circuit unit for supplying and recovering a sustain voltage to the drive integrated circuit unit, during the setup period A plasma display panel driving apparatus comprising a setup supply unit for supplying a sustain driving and rising ramp waveform to the drive integrated circuit unit, wherein the setup supply unit is a switching element connected to a setup voltage source, and one side is connected to the setup voltage source for switching. Comprising in parallel with the element, the other side includes a capacitor connected to the ground, the energy recovery circuit portion is characterized in that it comprises a ground voltage supply unit connected in series a plurality of switching elements.

Preferably, the switching device is a high voltage FET. The ground voltage supply unit configures a voltage divider circuit with the plurality of switching elements, and the ground voltage supply unit divides the setup voltage so as to be divided and applied to the plurality of switching elements, respectively.

The plurality of switching elements of the ground voltage supply unit may further include diodes connected in reverse directions with respect to ground.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a block diagram of a plasma display panel driving apparatus according to the present invention, and FIG. 5 is a timing diagram illustrating a switching operation process according to the present invention.

As shown, the present invention includes an energy recovery circuit unit 200, a setup supply unit 210, a scan driver 220, and a drive integrated circuit unit 230.

The drive integrated circuit unit 230 supplies a driving voltage to the panel Cp, and the energy recovery circuit unit 200 supplies a sustain voltage to the drive integrated circuit unit 230.

The energy recovery circuit unit 200 may reduce energy consumption by storing energy consumed during charging and discharging of the panel to recover accumulated energy when applying a pulse to the panel. The energy recovery circuit unit 200 includes a ground voltage supply unit 201 in which a plurality of switching elements, that is, fourth and twelfth switches Q4 and Q12 are connected in series.

The setup supply 210 supplies a sustain drive and rising ramp waveform to the drive integrated circuit 230 during the setup period. Accordingly, the setup supply unit 210 is connected to the switching voltage source Vsetup, that is, the fifth switch Q5 and one side thereof is connected to the setup voltage source Vsetup in parallel with the fifth switch Q5. It consists of the capacitor C2 connected to the ground GND of the other side.

The fifth switch Q5 forms a ramp pulse having a Vs voltage level and supplies the ramp pulse to the drive integrated circuit unit 230.

The switching elements Q4, Q5, and Q12 are preferably high voltage FETs.

In addition, the ground voltage supply unit 201 constitutes a voltage dividing circuit by the plurality of switching elements Q4 and Q12, and the ground voltage supply unit 201 divides the set-up voltage into the plurality of switching elements Q4. Each of them is divided into (Q12).

The plurality of switching elements Q4 and Q12 of the ground voltage supply part include diodes connected in reverse directions with respect to ground, respectively.

In addition, the scan driver 220 supplies a scan voltage necessary for driving the integrated circuit 230 and the address.

The present invention removes the sixth high-switch (Path_down) Q6 of the conventional high voltage as shown, and configured the capacitor C2 connected to the setup voltage source Vsetup to the ground GND.

In this case, when the setup voltage source Vsetup is assumed to be 450 V, for example, since the internal voltage of about 200 to 250 V is applied by the voltage distribution of the two switching elements Q4 and Q12, the sixth switch Q6 for high voltage is used. ) Can be removed.

In the waveform, the setup voltage Vsetup increases as a ramp waveform with an inclination, so that voltage distribution occurs as the capacitance component between the drain and the sources present in the two switching elements Q4 and Q12 is slowly charged. will be.

Therefore, while reducing the cost by reducing the expensive switching element (Q6) to maintain a more stable drive by applying the existing drive method.

Referring to the operation of the present invention configured in this way in more detail as follows.

As shown in FIG. 4, first, the fifth switch Q5 and the seventh switch Q7 are turned on during the setup period. At this time, the sustain voltage Vs is supplied from the energy recovery circuit unit 200.

The sustain voltage Vs supplied from the energy recovery circuit unit 200 is supplied to the panel Cp via the seventh switch Q7 and the drive integrated circuit unit 230. Therefore, the voltage of the panel Cp rises rapidly to Vs.

On the other hand, one end of the second capacitor C2 is grounded GND, and supplies the voltage of Vsetup to the fifth switch Q5. The fifth switch Q5 supplies the voltage supplied from the second capacitor C2 to the first node n1 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. .

The voltage applied with the predetermined slope to the first node n1 is supplied to the panel Cp via the seventh switch Q7 and the drive integrated circuit unit 230. Therefore, the rising ramp waveform Ramp-up is formed in the scan electrode line of the panel Cp.

As such, the fifth switch Q5 is turned off after the rising ramp waveform Ramp-up is supplied. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the energy recovery circuit unit 200 is applied to the first node n1, so that the voltage of the panel Cp drops rapidly to Vs.

Thereafter, the seventh switch Q7 is turned off and the tenth switch Q10 is turned on in the set down period. The tenth switch Q10 adjusts the channel width by the second variable resistor VR2 provided at the front end thereof, and writes the voltage of the second node n2 as a write scan voltage (-Vw) (or a setdown voltage source). Descend with a slope. At this time, a falling ramp waveform Ramp-down is formed in the panel Cp.

The setup supply unit 210 and the set-down supply unit 240 repeat the above process and supply the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the panel Cp during the reset period.

At this time, the ground voltage supply unit 201 constitutes a voltage divider circuit with the plurality of switching elements Q4 and Q12, and the ground voltage supply unit 201 divides the set-up voltage into the plurality of switching elements Q4 ( Q12) to be applied separately.

Therefore, it is possible to remove some of the conventional expensive FET switching elements, i.e., passive elements such as the sixth switch Q6, to achieve a low price, use a device having a low withstand voltage, and simplify the driving waveform.

Although the above has been illustrated and described with respect to preferred embodiments of the present invention, the present invention is not limited to the above-described embodiments, and the general knowledge in the field to which the present invention pertains without departing from the gist of the present invention claimed in the claims. Anyone with a variety of variations will be possible.

As described above, according to the plasma display panel driving apparatus according to the present invention, the cost can be reduced by reducing expensive switching elements, and the conventional driving method can be applied to maintain a more stable driving, thereby reducing manufacturing costs. There is.

In addition, it is possible to reduce the time and cost required to develop a separate driving method by applying the existing driving method as it is without having to develop a new driving method.

Claims (5)

A drive integrated circuit unit for supplying a driving voltage to the panel, an energy recovery circuit unit for supplying and recovering a sustain voltage to the drive integrated circuit unit, and a setup supply unit for supplying a sustain driving and rising ramp waveform to the drive integrated circuit unit during a setup period; In the plasma display panel drive device, The setup supply unit A switching element connected to the setup voltage source, one side connected to the setup voltage source and configured in parallel with the switching element, and the other side connected to ground; The energy recovery circuit portion And a ground voltage supply unit connecting a plurality of switching elements in series. The method of claim 1, And said switching element is a high voltage FET. The method of claim 1, The ground voltage supply unit And a voltage dividing circuit is constituted by the plurality of switching elements. The method of claim 3, wherein The ground voltage supply unit And dividing the setup voltage so as to be divided and applied to the plurality of switching elements. The method of claim 1, The plurality of switching elements of the ground voltage supply unit And a diode connected in a reverse direction with respect to the ground.

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