KR100662432B1 - Apparatus and method for driving plasma display panel - Google Patents

Abstract

A method and an apparatus for driving a plasma display panel are provided to stabilize an address discharge by decreasing driving impedance by directly applying a driving voltage on a gate of a first transistor. An apparatus for driving a plasma display panel includes a first transistor(Q1), a first resistor(R1), and a second transistor(Q2). The first transistor supplies a falling ramp pulse to a scan electrode in response to a driving voltage, which is generated during a set down period of a reset period. The first resistor is arranged between a gate of the first transistor and the driving voltage. The second transistor is parallel-coupled with the first resistor and turned on during an address period. The second transistor is turned on, while a gate-source voltage of the first transistor rises to a first voltage. The first voltage is a gate-source voltage of the first transistor when the first transistor is turned on.

Description

Apparatus and method for driving plasma display panel}

1 is a waveform diagram illustrating a driving waveform of a PDP supplied to two subfields.

2 is a circuit diagram of an embodiment of a driving apparatus of a plasma display panel according to the present invention.

FIG. 3 is a circuit diagram of a falling ramp pulse and a scan down pulse generator shown in FIG. 2.

4A to 4C are waveform diagrams of respective units in the falling ramp pulse and the scan down pulse generator shown in FIG. 3.

FIG. 5 is a circuit diagram of a falling ramp pulse and a scan down pulse generator shown in FIG. 2.

6A to 6C are waveform diagrams of respective parts of the falling ramp pulse and the scan down pulse generator shown in FIG. 5.

7 (a) to 7 (d) are waveform diagrams for explaining the operation of the plasma display panel driving apparatus according to the present invention and the conventional one.

8 shows a simulation circuit diagram of the driving apparatus of the plasma display panel according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a plasma display panel (hereinafter referred to as a " PDP "). In particular, a single switch can generate both a falling ramp pulse in a reset period and a negative scan pulse in an address period. Relates to a driving device of a PDP.

In the conventional AC type surface discharge PDP, time division driving is performed by dividing one frame into several subfields having different emission counts in order to realize gray level of an image. At this time, each subfield has a reset period for initializing the entire screen, an address period for selecting a scan line and selecting a cell from the selected scan line, and a sustain for implementing gray levels according to the number of discharges. divided into sustain periods.

1 is a waveform diagram illustrating a driving waveform of a PDP supplied to two subfields, in which signals Y supplied to a scan electrode, signals Z supplied to a sustain electrode, and signals supplied to an address electrode are shown in FIG. (X) is shown.

Referring to FIG. 1, each subfield is divided into a reset period, an address period, and a sustain period. In the reset period, the rising ramp pulse Ramp-up is applied to all the scan electrodes Y simultaneously. In the set down period, after the rising ramp pulse is supplied, the falling ramp pulse Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp pulse is applied to the scan electrodes Y simultaneously.

In the address period, the negative scan pulse Scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the reset period are added, an address discharge is generated in the cells to which the data pulse is applied.

In the sustain period, a sustain pulse su is applied to the scan electrodes Y and the sustain electrodes Z alternately. Erase in the sustain period represents an erase pulse.

On the other hand, the driving apparatus of the conventional plasma display panel may generate a falling ramp pulse in the reset period using a single switch (not shown), or may generate a negative scan pulse in the address period. In the conventional drive device of the plasma display panel, after the switch generating the falling ramp pulse generates the falling ramp pulse, it is not completely turned on at the start of the address period. Therefore, in a situation where the switch is not completely turned on, when the negative scan pulse (or scan down pulse) is applied, the high on-resistance of the switch may reduce the driving efficiency of the circuit and may cause a problem in the reliability of the circuit. have.

An object of the present invention is to provide a plasma display panel that can improve driving efficiency by improving switching loss when generating a scan sustain voltage (or scan up pulse) after generating a falling ramp pulse using a single switch. It is to provide a driving device.

According to an aspect of the present invention, there is provided a driving apparatus of a plasma display panel, comprising: a first transistor supplying a falling ramp pulse to a scan electrode in response to a driving voltage generated during a set down period of a reset period; A first resistor provided between the gate and the driving voltage and a second transistor connected in parallel with the first resistor and turned on in the address period are preferable.

Hereinafter, a configuration and an operation of a driving apparatus of a plasma display panel according to the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram of an embodiment of a driving apparatus of a plasma display panel according to the present invention, including a falling ramp pulse and a scan down pulse generator 10, a scan driver 12, a scan up pulse generator 14, and a rise lamp And a pulse generator 16, a sustain up voltage generator 18, a sustain down voltage generator 20, an energy recovery unit 22, and pass transistors Q5 and Q6.

The falling ramp pulse and the scan down pulse generator 10 shown in FIG. 2 generate the falling ramp pulse and the scan down pulse using a single switch Q1. To this end, the falling ramp pulse and the scan down pulse generator 10 may be implemented as a first transistor Q1, a first resistor R1, and a second transistor Q2.

The first transistor Q1 supplies the falling ramp pulse to the scan electrode Y in response to the driving voltage V1 generated during the set down period of the reset period. To this end, the first transistor Q1 is connected between a gate connected to the first resistor R1, a scan electrode Y, and a scan bias voltage source (not shown) generating the scan bias voltage (-Vy). Has a drain and a source. The first resistor R1 is provided between the gate of the first transistor Q1 and the driving voltage V1 and may be implemented as a variable resistor that may be variable as shown in FIG. 2.

The second transistor Q2 is connected in parallel with the first resistor R1 and turned on in the address period. To this end, the second transistor Q2 has a gate connected to the address signal V2 generated in the address period, a drain and a source connected to the driving voltage V1 and the gate of the first transistor Q1, respectively. That is, the second transistor Q2 is turned on when the address signal is input. For example, the second transistor Q2 is turned on in the address period.

According to the present invention, the falling ramp pulse and the scan down pulse generator 10 may further include a capacitor C _F1 , a second resistor R2, and a diode D1. Here, the second resistor R2 has one side connected to the drain of the first transistor Q1 and forms a charging path of the capacitor C _F1 . The capacitor C _F1 is connected between the other side of the second resistor R2 and the gate of the first transistor Q1, and serves to grow a Miller capacitor between the drain and the gate of the first transistor Q1. The diode D1 has a cathode and an anode connected to one side and the other side of the second resistor R2, respectively.

In addition, the falling ramp pulse and the scan down pulse generator 10 shown in FIG. 2 further include a diode D2 having a cathode and an anode connected between the gate of the first transistor Q1 and the scan bias voltage source, respectively. You may.

The scan driver 12 of the driving apparatus of the plasma display panel shown in FIG. 2 serves to drive the scan electrode Y. FIG. To this end, the scan driver 12 may be implemented with first and second switches Q4 and Q3. Here, the first switch Q4 is connected between the drain of the first transistor Q1 and the scan electrode Y. When the down ramp pulse is generated in the set down period of the reset period or the scan down pulse is generated in the address period, Turns on when generated. In addition, the second switch Q3 is connected between the first switch Q4 and a scan voltage source (not shown) generating the scan voltage Vscan and is turned on when a scan up pulse is generated.

The scan up pulse generator 14 generates a scan up pulse (or scan sustain voltage) in the address period. To this end, the scan up pulse generator 14 may include a scan up voltage source generating a scan voltage Vscan, a diode D3 having a positive electrode and a negative electrode connected between the scan up voltage source and the second switch Q3, respectively; The capacitor C ₁ is connected between the cathode of the diode D3 and the cathode of the diode D1.

The rising ramp pulse generator 16 serves to generate an upward ramp pulse in the reset period. To this end, the rising ramp pulse generator 16 is a driving voltage source for generating diodes D4, D5, D6 and D7, resistors R4 and R5, transistors Q7, capacitors C ₂ and a driving voltage. It may be implemented as (V3). Here, since the rising ramp pulse generator 16 has the same configuration as the falling ramp pulse and the scan down pulse generator 10 except for providing the diode D5 instead of the transistor Q2, the detailed description will be made as follows. Omit.

In the reset period, an upward ramp pulse is generated from the rising ramp pulse generator 16 and is supplied to the scan electrode 12 via the scan transistor 12 via the pass transistor Q6 to the sustain up voltage generator 18. Reverse current can flow. To prevent this, the pass transistor Q5 is turned off in the setup period of the reset period.

Also, when the falling ramp pulse and the scan down pulse generator 10 generate the falling ramp pulse, the falling ramp pulse and the scan down pulse are generated from the sustain down voltage generator 20 via the pass transistors Q5 and Q6. Reverse current may flow to the unit 10. To prevent this, the pass transistor Q6 is turned off in the set down period of the reset period.

The sustain up voltage generator 18 generates a sustain up voltage in the sustain period and supplies the sustain up voltage to the scan electrode Y. To this end, the sustain up voltage generator 18 may be implemented as a sustain voltage source generating the sustain voltage Vs and a transistor Q8 connected to the scan electrode through the pass transistors Q5 and Q6.

The sustain down voltage generator 20 generates a sustain down voltage in the sustain period and supplies the sustain down voltage to the scan electrode (Y). For this purpose, the sustain down voltage generator 20 may be implemented as a transistor Q9 connected to the scan electrode Y through the reference potential GND corresponding to the sustain down voltage and the pass-through transistors Q5 and Q6. have.

The energy recovery unit 22 recovers energy discharged from the scan electrode Y in the sustain period or re-supplies the recovered energy to the scan electrode Y in the sustain period. To this end, the energy recovery unit 22 may be implemented with transistors Q10 and Q11, diodes D8, D9, D10 and D11, and an inductor L.

In the driving apparatus of the plasma display panel according to the present invention having the above-described configuration, the operation of the falling ramp pulse and the scan down pulse generator 10 will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram of the falling ramp pulse and scan down pulse generator 10 shown in FIG. 2, and includes diodes D1 and D2, resistors R1 and R2, capacitor C _F1 , and transistors Q1. And Q2).

4 (a) to (c) are waveform diagrams of the respective parts of the falling ramp pulse and the scan down pulse generator 10 shown in FIG. 3, and FIG. 4 (a) shows the signal supplied to the scan electrode (Y). 4B shows a waveform diagram of the drive voltage V1, and FIG. 4C shows a waveform diagram of the address signal, respectively.

As shown in FIG. 4B, when a driving voltage V1 having a "high" logic level is applied to the gate of the first transistor Q1, a path of the gate input current is formed in the arrow direction 40. In this case, a current path from the panel capacitor Cp to the drain and the source of the first transistor Q1 via the first switch Q4 is formed in the arrow direction 44. Therefore, the falling ramp pulse 42 may be generated and supplied to the scan electrode Y, as shown by a thick solid line in FIG. 4A. At this time, since the address signal V2 is generated at the "low" logic level, the second transistor Q2 is in the turned off state.

FIG. 5 is a circuit diagram of the falling ramp pulse and scan down pulse generator 10 shown in FIG. 2, wherein the diodes D1 and D2, the resistors R1 and R2, the capacitor C _F1 , and the transistors ( Q1 and Q2).

6 (a) to 6 (c) are waveform diagrams of respective parts of the falling ramp pulse and the scan down pulse generator 10 shown in FIG. 5, and FIG. 6 (a) shows the signal supplied to the scan electrode (Y). 6 (b) shows the waveform diagram of the drive voltage V1, and FIG. 6 (c) shows the waveform diagram of the address signal, respectively.

As shown in FIG. 6C, when an address voltage V2 having a "high" logic level is applied to the gate of the second transistor Q2 in the address period, the first transistor Q1 is moved in the arrow direction 60. A path of current input to the gate is formed. In this case, the current path from the scan bias voltage (-Vy) through the source and the drain of the first transistor Q1 to the panel capacitor Cp via the capacitor C1 and the second switch Q3 is indicated by the arrow direction. 64 is formed. Therefore, scan sustain voltages (or scan up pulses) 61 and 62 may be generated and supplied to the scan electrode Y, as shown by a thick solid line in FIG. 6A.

7 (a) to (d) are waveform diagrams for explaining the operation of the plasma display panel driving apparatus according to the present invention and the operation of the driving apparatus of the conventional plasma display panel in comparison with each other, Figure 7 (a) is a scan 7B shows a waveform diagram of the signal supplied to the electrode Y, FIG. 7B shows a waveform diagram of the driving voltage V1, and FIG. 7C shows a first diagram included in a conventional plasma display panel driving apparatus. FIG. 7D is a waveform diagram of the gate-source voltage of the first transistor Q1 included in the driving apparatus of the plasma display panel according to the present invention. Indicates.

2 and 7 (a) to (d), the driving voltage V1 shown in FIG. 7 (b) is the gate of the first transistor Q1 shown in FIG. 2 in the set down period of the reset period. Is applied to. Here, considering the RC time constant formed by the Miller capacitor between the resistance value of the first resistor R1 and the drain-gate of the first transistor Q1, the driving voltage applied to the gate of the first transistor Q1 is For example, it may be set to 15 volts as shown in Figure 7 (b). At this time, as shown in FIG. 7 (c) or (d), when the gate-source voltage Vgs of the first transistor Q1 is about 4 volts, the Miller capacitor of the first transistor Q1 is applied to the Miller capacitor. Charged charges are discharged through the first resistor R1. Therefore, as shown in FIG. 7A, a ramp waveform may be generated in the set-down period of the reset period. At this time, when the charge charged in the Miller capacitor reaches 0 volts, the generation of the falling ramp pulse is terminated.

Next, at the time of the address period, the parasitic capacitors are charged between the gate-drain and the gate-source of the first transistor Q1 since the drive signal V1 continues to maintain a "high" logic level of 15 volts. do.

As shown in FIG. 2, the falling ramp pulse and the scan down pulse generator 10 of the driving apparatus of the conventional plasma display panel include a diode (not shown) instead of the second transistor Q2. Therefore, since the resistance value of the first resistor R1 has a large value corresponding to several hundred to several kilo ohms (Ω), the gate-source voltage Vgs of the first transistor Q1 is at the time of the address period. As shown in FIG. 7C, the voltage 80 gradually increases to 15 volts during the period X, and the on resistance of the first transistor Q1 decreases. That is, the driving device of the conventional plasma display panel provides a diode instead of the second transistor Q2, and thus is not completely turned on in the initial portion X of the address period. In this state, when the first switch Q4 shown in FIG. 2 is turned on and the second switch Q3 is turned off at the same time to generate a scan down pulse, due to the high on resistance of the first transistor Q1. Drive efficiency can be reduced.

In order to prevent this, the falling ramp pulse and the scan down pulse generator 10 of the driving apparatus of the plasma display panel according to the present invention provide a second transistor Q2 instead of a diode. Here, the driving apparatus of the plasma display panel according to the present invention turns on the second transistor Q2 at the time of the address period so that an input current for driving the first transistor Q1 does not pass through the first resistor R1. Rather, it flows directly through the second transistor Q2. Therefore, as shown in FIG. 7D, the first transistor Q1 may be turned on 82 quickly at the beginning of the address period. As such, since the first transistor Q1 may be turned on at a lower ON resistance than the related art, driving efficiency may be improved and a stable scan up waveform may be generated.

According to the present invention, the address signal V2 may be generated only during the period X during which the gate-source voltage of the first transistor Q1 rises to the first voltage. For example, the second transistor Q2 may be turned on only during the period X during which the gate-source voltage of the first transistor Q1 rises to the first voltage. Here, the first voltage is a gate-source voltage of the first transistor Q1 when the first transistor Q1 is turned on and may be, for example, 15 volts.

8 shows a simulation circuit diagram of the driving apparatus of the plasma display panel according to the present invention.

As described above, the driving apparatus of the plasma display panel according to the present invention uses only one switch Q1 to generate the down ramp pulse in the set down period of the reset period and to generate the scan up waveform in the address period. It is possible to increase the driving efficiency by improving the switching loss of the first transistor. In particular, when the scan up pulse is generated in the address period, the driving voltage is converted to the first transistor Q1 by using the second transistor Q2 instead of the first resistor R1. Since it is applied immediately to the gate of the has the effect that can provide a stable address discharge characteristics by a low drive impedance.

Claims (7)

A first transistor supplying a falling ramp pulse to the scan electrode in response to a driving voltage generated during the set down period of the reset period; A first resistor provided between the gate of the first transistor and the driving voltage; And And a second transistor connected in parallel with the first resistor and turned on in an address period. The method of claim 1, wherein the second transistor is turned on while the gate-source voltage of the first transistor is increased to the first voltage, And the first voltage corresponds to a gate-source voltage of the first transistor when the first transistor is turned on. The apparatus of claim 1, wherein the first resistor is variable. The method of claim 1, wherein the first transistor A gate connected to the first resistor; And a drain and a source connected between the scan electrode and the scan bias voltage source, respectively. The method of claim 1, wherein the second transistor A gate connected to an address signal generated in the address period; And a drain and a source connected to the driving voltage and the gate of the first transistor, respectively. The driving apparatus of claim 1, wherein the plasma display panel is driven. A second resistor having one side connected to the drain of the first transistor; A capacitor connected between the other side of the second resistor and the gate of the first transistor; And And a diode having a cathode and an anode connected to one side and the other side of the second resistor, respectively. The driving apparatus of claim 1, wherein the plasma display panel is driven. A first switch connected between the drain of the first transistor and the scan electrode and turned on when a scan down pulse is generated in the set down period or the address period; And And a second switch connected between the first switch and the scan up pulse and turned on when a scan up pulse is generated.

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