KR100390887B1 - Driving Circuit for AC-type Plasma Display Panel - Google Patents

Abstract

The present invention relates to a drive circuit of an AC plasma display panel which can reduce the number of switching elements in a drive circuit to which a ramp wave driving method is applied, which is a driving operation in accordance with a reset section, an address section and a sustain section of the display panel. It is possible to reduce the number of switching elements required of the driving circuit by changing the circuit configuration so as to exclude the control switch on the high current flow path applied to the panel.

Description

Driving Circuit for AC Plasma Display Panel {Driving Circuit for AC-type Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP), and more particularly, to a driving circuit of an AC plasma display panel capable of reducing the number of switching elements in a driving circuit to which a lamp wave driving method is applied.

In general, a plasma display panel (hereinafter, referred to as a 'PDP') is a light emitting device that displays an image by exciting a phosphor formed in a discharge cell. As image display apparatuses used for conference displays, large-screen wall-mounted TVs, and the like, the use thereof is greatly increased.

These PDPs are classified into AC type and DC type according to the driving voltage. In the case of AC type PDP, one frame is divided into a plurality of subfields according to the gray level to be implemented. The ADS (Addressing Display Separated) method of driving separately is mainly used. Each subfield is divided into a reset section, an address section, and a sustain section, and one frame includes eight or more subfields to implement 256 gray levels.

The reset section is a section for initializing wall charges in the discharge cells by generating wall charges in all the discharge cells of the PDP and erasing the generated wall charges after the sustain discharge of the previous subfield is performed. As an example, an initialization pulse (lamp wave pulse) equal to or greater than the discharge start voltage is applied to the scan / hold electrode, which will be described later. It is a section.

The address section is a section in which image discharge, that is, address discharge, of image data is selectively performed for each discharge cell after the reset section, and the sustain section repeats the discharge operation of the discharge cell selected to maintain the address discharge. This section is for performing gradation display by weighting the number of discharges of each subfield and combining them.

1 is a block diagram schematically illustrating a configuration of a conventional AC PDP device driven according to the ADS method.

In FIG. 1, reference numeral 10 denotes M scan / sustain electrodes Y _{1 to} Y _M and sustain electrodes X _{1 to} X _M arranged in parallel, and N address electrodes A _{1 to} A _N are scanned / The storage electrodes Y _{1 to} Y _M and the storage electrodes X _{1 to} X _M are orthogonally arranged with a predetermined space therebetween, and the scan / hold electrodes Y _{1 to} Y _M and the storage electrodes X _{1 to} X _M ) And a plurality of discharge cells S divided into R (Red), G (Green), and B (Blue) cells are formed at each intersection point of the _first and second address electrodes A _{1 to} A _N. It is the panel 10 which displays the image of MxN resolution of a form.

In Fig. 1, reference numerals 20, 30, and 40 denote predetermined driving pulses on the scan / sustain electrodes Y _{1 to} Y _M , sustain electrodes X _{1 to} X _M , and address electrodes A _{1 to} A _N, respectively. As the scan / sustain electrode driver, sustain electrode driver, and address electrode driver for supplying, the scan / sustain electrode driver 20 and the sustain electrode driver 30 are each of the above-described reset section, address section, and sustain section. Each of the predetermined driving circuits for supplying the driving pulse corresponding to (10) is provided.

Reference numeral 50 denotes the scan / sustain electrode driver to output a digital image signal based on an external input signal CLK, a horizontal synchronization signal HS, a vertical synchronization signal VS, and an input image signal IMAGE. 20), a control unit for controlling the sustain electrode driver 30 and the address electrode driver 40.

On the other hand, when the PDP device is driven, a charge / discharge current, for example, a high current of 100 A or more flows through the panel 10 of FIG. 1. The charge / discharge current flows into and out of the panel 10 through a predetermined driving circuit (not shown) provided in the scan / sustain electrode driver 20 and the sustain electrode driver 30. Many control switches are connected in parallel to withstand charge and discharge current.

Therefore, this is acting as one of the causes to increase the production cost, the reality is that various attempts have been made to reduce the number of control switches required in the drive circuit to solve this problem.

In recent years, the use of the ramp wave driving method proposed in Japanese Patent Laid-Open No. 11-133914 (Publication No.) among the driving methods of the PDP device is increasing. The ramp wave driving method includes a wall charge on the scan / hold electrode before the start of the address section by supplying a ramp wave driving pulse in which the slope of the output voltage rises and falls linearly as a driving pulse of the reset section according to the ADS driving method described above. By uniformly distributing the distribution, a uniform discharge is performed in the discharge cell (S).

However, the driving circuit according to the ramp wave driving method has an advantage of improving the driving characteristics of the PDP device, but there is a problem in that a large number of circuit elements (particularly, switching elements) in the driving circuit are required.

Accordingly, an object of the present invention is to provide a driving circuit of an AC plasma display panel which can reduce the number of switching elements of a driving circuit included in a PDP device while using a lamp wave driving method. There is this.

1 is a block diagram schematically showing the configuration of a conventional AC PDP apparatus driven according to an ADS scheme.

Figure 2 is a circuit diagram showing the internal configuration of the Y drive circuit according to an embodiment of the present invention.

3 is a voltage waveform diagram showing an output waveform of the Y driving circuit according to an embodiment of the present invention.

4 is a timing diagram showing switching timing of a Y driving circuit according to an embodiment of the present invention;

5 is a circuit diagram showing an internal configuration of a Y driving circuit according to another embodiment of the present invention.

6 is a circuit diagram showing an internal configuration of a Y driving circuit according to another embodiment of the present invention.

*** Brief description of symbols for the main parts of the drawings ***

10: panel, 20: scanning / holding electrode driver,

30: sustain electrode driver, 40: address electrode driver,

50: control unit, 200, 300, 400: Y drive circuit,

210, 310: first switching unit, 220, 410: second switching unit,

230: third switching unit, 231: drive IC,

Q _LH , Q _LL , Q1 ~ Q7: Control switch, D1 ~ D4: Diode,

C1, C2: capacitors.

The drive circuit of the AC plasma display panel according to the present invention for achieving the above object is connected between the sustain power supply, the lamp power supply and the scan power supply and the panel to generate a drive pulse for each section consisting of a reset section, an address section and a sustain section. And a driving circuit of an AC plasma display panel wherein the driving pulse of the reset section is a ramp wave driving pulse, the driving power being connected between the holding power source, the lamp power source, the ground terminal, and the panel based on the holding power source and the lamp power source. A first switching unit for interrupting a predetermined driving pulse supplied to the panel; a second switching unit electrically coupled to the first switching unit and preventing a predetermined driving pulse from the scan power from flowing into the first switching unit; And electrically coupled to a switching unit, the first and second switching units, and the panel, respectively. A third switching unit for controlling a predetermined driving pulse supplied to the panel based on a ground power source, a lamp power source and a scan power source, and a ramp wave which is coupled between the lamp power source and the first switching part and rises in the reset section; A first integrating circuit generating a driving pulse and supplying it to the panel; and a second integrating circuit generating a ramp wave driving pulse coupled between the first switching unit and a ground terminal and falling in the reset section, and supplying the driving pulse to the panel. Characterized in that provided with.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

<First Embodiment>

First, when the driving circuit provided in the scan / sustain electrode driving unit 20 of FIG. 1 is referred to as the Y driving circuit, and the driving circuit provided in the sustain electrode driving unit 30 is referred to as the X driving circuit, the present exemplary embodiment of the Y driving circuit In order to reduce the number of switching elements, a detailed description of the X driving circuit will be omitted herein.

FIG. 2 is a circuit diagram illustrating an internal configuration of a Y driving circuit according to an embodiment of the present invention. In FIG. 2, reference numeral 200 denotes a sustain power supply (V _S ), a lamp power supply (V _R ), and a scan power supply (V _F). ) And a Y driving circuit connected between the panel 10 of FIG. 1 (part denoted by C _P in FIG. 2) and switching-controlled when the PDP device is driven to supply a predetermined driving pulse to the panel 10. As a result, a plurality of control switches Q are applied to drive the reset pulses A, the address B, and the sustain period C shown in FIG. 3 to the panel 10 when the PDP device is driven. _LH , Q _LL , and Q1 to Q7).

In FIG. 2, the control switches Q _LH , Q _LL , and Q1 to Q7 include a metal-oxide semiconductor field-effect transistor (MOSFET) and an anti-parallel diode, and an insulated gate bipolar transistor (IGBT). It is also possible to use an Insulated Gate Bipolat Transistor.

In FIG. 2, reference numeral C _P denotes a capacitance component of the panel 10 (hereinafter, referred to as a 'panel capacitor'), and the PDP apparatus scan / hold electrodes Y _{1 to} Y in the discharge cell S during driving. _The high voltage above the discharge start voltage must be continuously applied alternately between _M ) and the sustain electrodes X _{1 to} X _M. In this case, a dielectric is coated on the scan / sustain electrodes Y _{1 to} Y _M and the sustain electrodes X _{1 to} X _M , whereby the panel capacitor C _P is present on both electrodes.

Figure reference numeral 210 denotes a sustain power source (V _S), the lamp power (V _R), maintaining the connection between the ground terminal and the panel capacitor (C _P) that is supplied to the panel 10, power supply (V _S) and the lamp in the second As a first switching unit for intermitting the power supply (V _R ), the first switching unit 210 is a backflow prevention diode (D1) having an anode connected to the holding power supply (V _S ), at least three control switches (Q _LH) , Q1, Q _LL ) are sequentially connected in series.

In FIG. 2, the connection node a between the control switch Q1 and the control switch Q _LL is connected to an energy recovery circuit (not shown), and the connection node b between the control switch Q _LH and the control switch Q1. ) Is connected to the panel capacitor C _P through a driving IC (Integrated Circuit) to be described later.

In addition, the energy recovery circuit (not shown) is for recovering reactive power generated during the charging / discharging operation of the panel 10, and a detailed description thereof will be omitted.

In FIG. 2, reference numeral 220 denotes a connection between the first switching unit 210 and a third switching unit, which will be described later, so that driving pulses by the scan power V _F flow into the first switching unit 210. As a second switching unit for preventing, the second switching unit 220 includes a control switch Q2 having a source connected to the first switching unit 210 and a drain connected to a third switching unit described later. It is configured by.

In FIG. 2, reference numeral 230 denotes a third switching for intermittent driving pulses supplied to the panel 10 based on the sustain power V _S , the lamp power V _R , and the scan power V _F. In an exemplary embodiment, the third switching unit 230 includes a backflow prevention diode D2, a control switch Q3, and a driving IC 231 sequentially connected to an anode connected to the scan power supply V _F. .

In FIG. 2, the driving IC 231 includes control switches Q4 and Q5 connected in series, and the connection node V _OUT of the control switches Q4 and Q5 is connected to the panel capacitor C _P. It is connected to supply the driving pulse for each section to the panel 10. Meanwhile, in the present embodiment, the driving IC 231 has a configuration in which two control switches Q4 and Q5 are connected, but it may be configured as one control switch.

In FIG. 2, reference numeral 240 denotes a first integrating circuit for generating a rising wave driving pulse Rising Ramp Pulse in the reset period A shown in FIG. 3, which is connected to the anode of the lamp power supply V _R. The non-return diode D3 and the control switch Q6, and the capacitor C1 connected between the drain and the gate of the control switch Q6. The first integrating circuit 240 is a general Miller integrating circuit for generating a ramp wave pulse, and a detailed description thereof will be omitted.

In FIG. 2, reference numeral 250 denotes a second integrating circuit for generating a ramp wave driving pulse falling in the reset period A shown in FIG. 3, which is a control switch Q7 and a capacitor C2. Constitutes the Miller integrating circuit, and the cathode of the backflow prevention diode D2 is connected to the drain of the control switch Q7.

That is, the Y driving circuit having the above-described configuration includes the driving pulses divided into the reset section A, the address section B, and the sustain section C shown in FIG. 3 for each subfield of the image data. Switching control according to the timing diagram of FIG.

Hereinafter, the operation of the Y driving circuit 200 having the configuration of FIG. 2 will be described with reference to FIGS. 3 and 4.

First, in the Y driving circuit 200 of FIG. 2, the control switch Q1 of the first switching unit 210 and the control switch Q6 of the first integrating circuit 240 are driven on / off complementarily. That is, the control switch Q6 is off-driven when the control switch Q1 is on-driven, and the control switch Q1 is off-driven when the control switch Q6 is on-driven. In addition, in FIG. 2, the control switch Q2 of the second switching unit 220 and the control switch Q3 of the third switching unit 230 are also complementarily turned on / off in the above-described manner. This shows an example of the driving method of the Y driving circuit 200, and does not necessarily need to be driven in the above-described manner.

In FIG. 3, the TO section is a section for discharging the panel 10 after the sustain section C of the previous subfield is finished. In this case, the control switches Q _LL , Q1, Q2 and Q5 of FIG. The driving path is turned on to form a discharge path of the control switch _Q5- > control switch _Q1- > control switch Q _LL . At this time, the control switch (Q2) is the control switch (Q3) is driven off and complementary on.

In FIG. 3, the T1 section supplies ramp wave driving pulses rising to the panel 10 of FIG. 1 as the reset section A starts to generate wall charges in all the discharge cells S of the panel 10. As the section, the control switches Q _LH , Q2, Q5 and Q6 in FIG. 2 are driven on.

Therefore, the driving pulse by the sustain power supply (V _S ) is supplied to the panel 10 through the path of the diode (D1)-> control switch (Q _LH )-> control switch (Q5) and the lamp power (V _R ). The driving pulse is supplied to the panel 10 through the path of the diode D3-> control switch Q6-> control switch Q _LH- > control switch Q5.

At this time, the driving pulse applied to the panel 10 of FIG. 1 forms a ramp wave in which the voltage rising slope increases linearly as shown in FIG. 3 by the first integrating circuit 240 of FIG. Is raised to the holding voltage + lamp voltage (V _S + V _R ).

In FIG. 3, the T2 section is a rest period for maintaining the voltage level of the ramp wave driving pulse applied to the panel 10 for a predetermined period. In this case, the control switches Q _LH , Q2, Q5, and Q6 of FIG. 2 are driven on. . That is, the section T2 of FIG. 3 is a section for waiting for space charges formed in the discharge cells S, that is, attenuation of priming particles, and when the rest period is absent or too short, the self discharge (S) in the discharge cells S Self Discharge) causes a deterioration of the driving characteristics of the PDP.

In FIG. 3, the section T3 is a section in which the voltage level of the driving pulse drops to the sustain voltage V _S before supplying the ramp wave driving pulse to the panel 10. In this case, the control switches Q _LH , Q1, and FIG. Q2 and Q5) are driven on. In this case, the control switch Q1 of FIG. 2 is complementarily turned on as the control switch Q6 of the first integrating circuit 240 is turned off.

In FIG. 3, the section T4 is a section for gradually erasing wall charges formed in all the discharge cells S by supplying a ramp wave driving pulse that descends to the panel 10, and the control switches Q1, Q2, and Q5 of FIG. 2. , Q7) is turned on to form a discharge path of the control switch Q5-> diode D4-> control switch Q7 from the panel capacitor C _P.

In FIG. 3, the section T5 is a section for discharging the panel 10 before the address section B starts, and the control switches Q _LL , Q1, Q2, Q5, and Q7 of FIG. 2 are driven on to allow the panel capacitor ( C _P ) discharge path of control switch Q5-> diode D4-> control switch Q7 as well as other discharges of control switch _Q5- > control switch _Q1- > control switch Q _LL Paths are formed at the same time.

In FIG. 3, the periods T6 and T7 are address periods B in which write discharges for selectively writing image data into discharge cells S of the panel 10 are performed by the address electrode driver 40 of FIG. 1. The driving pulses shown in FIG. 3 are sequentially supplied to the discharge cells S. As shown in FIG. In this case, the control switches Q _LL , Q1, Q3, and Q4 of FIG. 2 are driven on, and the driving pulses of the scan power supply V _F are supplied to the panel 10 (T6 section), and the control switches Q _LL , Q1, Q3, and Q5 are driven on to discharge the panel 10. (T7 section)

In the T6 section, the control switches Q _LL and Q1 of FIG. 2 are pre-driven for the discharge operation of the T7 section. Thereafter, the operations of the T6 and T7 sections are repeatedly performed during the address section B.

In FIG. 3, the periods T8 and T9 are sustain periods C in which sustain discharge (oil-dielectric discharge) for gradation display is repeatedly performed according to a predetermined weight with respect to the discharge cells S in which image data is written. In this case, the control switches Q _LH , Q1, Q2, and Q5 of FIG. 2 are driven on, and a driving pulse by the sustain power supply V _S is supplied to the panel 10 (T8 section), and the control switches Q _LL , Q1, Q2, and Q5 are turned on to discharge the panel 10. (T9 section)

And the operation of the T8 and T9 section is repeatedly performed during the sustain period (C), the sustain discharge in the sustain period (C) is the Y driving circuit 200 shown in Figure 2 as well as the sustain electrode driver of FIG. It is alternately made through the X driving circuit (not shown) provided in the (30).

A Y driver circuit of Figure 2 according to this embodiment as described above 200 is controlled to be installed in the flow path of the discharge current of the driving pulse to the panel 10 by the sustain power source (V _S) and a lamp power supply (V _R) By changing or disposing the switch, the number of switching elements of the Y driving circuit to which the ramp wave driving method is applied is reduced.

That is, since the control switch installed on the charge / discharge path of the panel 10 has a configuration in which a plurality of control switches are actually connected in parallel to withstand the internal pressure according to the high voltage / high current, the connection node of FIG. By excluding the switching element between (b) and the connection node (c), it is possible to reduce the power consumption by the control switch and the required number of circuit elements.

Second Embodiment

FIG. 5 is a circuit diagram showing an internal configuration of a Y driving circuit according to another embodiment of the present invention. The same reference numerals denote the same components as those shown in FIG. It will be omitted.

That is, the Y driving circuit 300 of FIG. 5 performs the same function as the Y driving circuit 200 of FIG. 2 while further reducing the number of switching elements required for the driving circuit. Circuit configuration is changed.

Figure reference numeral 310-5 is held power (V _S), the lamp power (V _R), maintaining the connection between the ground terminal and the panel capacitor (C _P) which is supplied to the panel (10), power (V _S) and a lamp power As a first switching unit for intermitting (V _R ), the first switching unit 310 is a backflow prevention diode (D1), the control switch (Q _LH , Q _LL ) having an anode connected to the holding power supply (V _S ). Are sequentially connected in series. In FIG. 5, the connection node d of the control switch Q _LH and the control switch Q _LL is connected to an energy recovery circuit (not shown) and connected to the panel capacitor C _P through the driving IC 231. .

That is, the first switching unit 310 shown in FIG. 5 is configured to exclude the control switch Q1 from the first switching unit 210 of FIG. 2. In FIG. 2, only one control switch Q1 is illustrated, but in fact, a plurality of control switches are connected in parallel. According to the present embodiment, the number of control switches required for the Y driving circuit can be further reduced. do.

However, when the control switch Q1 is excluded as shown in FIG. 5, the internal voltage of the control switch Q _LL of FIG. 5 is increased, but, for example, the control switch Q _{LL is} connected to the insulated gate bipolar transistor IGBT. It is possible to overcome the burden by using a switching element having a high breakdown voltage.

Meanwhile, the operation of the Y driving circuit 300 shown in FIG. 5 is operated in the same manner as the Y driving circuit 200 of FIG. 2, and a detailed description thereof will be omitted.

Third Embodiment

FIG. 6 is a circuit diagram showing the internal structure of the Y driving circuit according to another embodiment of the present invention. The same components as those shown in FIGS. 6 to 5 are denoted by the same reference numerals, and detailed description thereof. Will be omitted.

That is, the Y driving circuit 400 of FIG. 6 performs the same function as the Y driving circuit 300 of FIG. 5 and the control switch Q2 in the second switching unit 220 of FIG. 5 as shown in FIG. 6. Likewise, it is replaced by the reverse current prevention diode (D5). In FIG. 6, an anode of the diode D5 is connected to a connection node of the first switching unit 310 and the second integrating circuit 250, and a cathode of the control switch Q3 in the third switching unit 400. And a driving pulse connected to the connection node of the driving IC 231 to prevent the driving pulse by the scan power supply V _F from flowing back to the first switching unit 310. Therefore, according to this embodiment, the number of switching elements required for the Y driving circuit can be further reduced.

As described above, according to the present invention, as the number of switching elements required in the driving circuit using the ramp wave driving method is greatly reduced, the production cost can be reduced. In addition, according to the present invention, as the number of switching elements in the driving circuit is reduced, the driving circuit can be configured more concisely, and power consumption through the switching elements can be reduced.

Claims (5)

An AC plasma display panel is connected between a sustain power supply, a lamp power supply, and a scan power supply and a panel to generate a drive pulse for each section including a reset section, an address section and a sustain section, and the drive section of the reset section has a ramp wave driving pulse. In the driving circuit, A first switching unit connected between the holding power source, the lamp power source, the ground terminal, and the panel to control a predetermined driving pulse supplied to the panel based on the holding power source and the lamp power source; A second switching unit electrically coupled to the first switching unit and preventing a predetermined driving pulse from the scan power from flowing into the first switching unit; A third switching unit electrically coupled to the first and second switching units and the panel, respectively, to control a predetermined driving pulse supplied to the panel based on the sustain power, lamp power, and scan power; A first integrating circuit coupled between the lamp power source and the first switching unit to generate a ramp wave driving pulse rising in the reset section and to supply the ramp wave driving pulse to the panel; And a second integrating circuit coupled between the first switching unit and the ground terminal to generate a ramp wave driving pulse falling in the reset section and to supply the ramp wave driving pulse to the panel. . The method of claim 1, The first switching unit is a driving circuit of the AC plasma display panel, characterized in that the reverse flow prevention diode having an anode connected to the holding power supply and at least three control switches (Q _LH , Q1, Q _LL ) are sequentially connected in series. . The method according to claim 1 or 2, And the second switching unit comprises a control switch having a source connected to the first switching unit and a drain connected to the third switching unit. The method of claim 1, The first switching means is a drive circuit of the AC plasma display panel, characterized in that the reverse flow prevention diode and the two control switches (Q _LH , Q _LL ) is connected in series with an anode connected to the holding power supply in sequence. The method of claim 4, wherein And the second switching means comprises a diode in which an anode is connected to the first switching part and a cathode is connected to the third switching part.