KR100645790B1 - Driving apparatus for plasma display panel - Google Patents

Abstract

A driving device of a plasma display panel is provided to reduce the number of switching elements of the driving device supplying setup pulse and scan reference voltage and to facilitate controlling of the driving device by generating and supplying a control signal by combining control signals of other switching elements. A driving device of a plasma display panel includes an energy recovery circuit unit(700) supplying sustain voltage(Vs) to a scan electrode of the plasma display panel through a scan drive IC(Integrated Circuit,730) and recovering unavailable energy from the scan electrode; a setup and scan reference voltage supply unit(740) supplying setup pulse including the ramp-up pulse, to the scan electrode with scan reference voltage(Vsc) supplied from a scan reference voltage source and sustain voltage supplied from the energy recovery circuit unit through the scan drive IC, for a setup time of a reset period and feeding the scan reference voltage to the scan electrode during an address period; a setdown supply unit(710) supplying setdown pulse including ramp-down pulse, to the scan electrode through the scan drive IC for the setdown time after the setup time of the reset period; and a negative-polarity scan voltage supply unit(720) supplying scan pulse falling from the scan reference voltage, to the scan electrode through the scan drive IC during the address period after the reset period.

Description

Driving device for plasma display panel {Driving Apparatus for Plasma Display Panel}

1 is a diagram showing the structure of a typical plasma display panel.

2 is a diagram illustrating a method of implementing image gradation of a conventional plasma display panel.

3 is a view showing a driving waveform generated by a driving apparatus of a conventional plasma display panel.

4 is a view for explaining a driving apparatus of a conventional plasma display panel.

FIG. 5 is a diagram for explaining input of a control signal for controlling the operation of a scan drive integrated circuit in a driving apparatus of a conventional plasma display panel. FIG.

FIG. 6 is a view for explaining switching timing of switching elements and timing of a control signal of a scan drive integrated circuit in a driving apparatus of a conventional plasma display panel. FIG.

Fig. 7 is a diagram for explaining the configuration of a drive device for a plasma display panel of the present invention.

FIG. 8 is a view for explaining in detail the configuration of a setup selection unit 743 and a scan selection unit 744 of the driving apparatus of the plasma display panel of the present invention of FIG.

9 is a view for explaining the operation of the driving apparatus of the plasma display panel of the present invention of FIG.

10A to 10B are views for explaining in more detail the operation of the setup and scan reference voltage supply unit in the driving apparatus of the plasma display panel of the present invention of FIG.

FIG. 11 is a diagram for explaining switching timing of switching elements in the driving apparatus of the plasma display panel of the present invention; FIG.

12A to 12B illustrate a control signal for controlling switching of switching elements of a scan drive integrated circuit and a process of forming the same in a driving apparatus of a plasma display panel of the present invention.

FIG. 13 is a view for explaining the configuration of a driving apparatus of a plasma display panel of the present invention to generate control signals for controlling switching timing of switching elements of a scan drive integrated circuit as setup selection signals and scan selection signals.

14A to 14B are views for explaining in more detail the operation of the driving apparatus of the plasma display panel of the present invention in FIG.

Fig. 15 is a view for explaining still another configuration of a driving device of the plasma display panel of the present invention.

<Explanation of symbols for main parts of the drawings>

700: energy recovery circuit unit 710: set down supply unit

720: negative scan voltage supply unit 730: scan drive integrated circuit

740: setup and scan reference voltage supply 741: voltage regulation capacitor

742: setup / scan common switch 743: setup selector

744: scan selector 745: energy path selector

746: reverse current prevention portion Qb: blocking switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to providing a setup pulse to a scan electrode in a setup period of a reset period, and to supplying a setup pulse to a scan electrode in an address period. The present invention relates to a driving apparatus of a plasma display panel with improved wealth and improved generation and supply of control signals of a scan drive integrated circuit.

In general, a plasma display panel is a partition wall formed between a front panel and a rear panel to form one unit cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He) and An inert gas containing the same main discharge gas and a small amount of xenon is filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Such a plasma display panel has a spotlight as a next generation display device because of its thin and light configuration.

1 illustrates a structure of a general plasma display panel.

As shown in FIG. 1, a plasma display panel includes a front panel in which a plurality of sustain electrode pairs formed by pairing a scan electrode 102 and a sustain electrode 103 are arranged on a front glass 101 that is a display surface on which an image is displayed. The rear panel 110 on which the plurality of address electrodes 113 are arranged so as to intersect the plurality of sustain electrode pairs on the back glass 111 forming the back surface 100 and the rear surface is coupled in parallel with a predetermined distance therebetween. .

The front panel 100 is made of a scan electrode 102 and a sustain electrode 103, that is, a transparent electrode (a) formed of a transparent ITO material and a metal material to mutually discharge and maintain light emission of the cells in one discharge cell. The scan electrode 102 and the sustain electrode 103 provided as the bus electrode b are included in pairs. The scan electrode 102 and the sustain electrode 103 are covered by one or more upper dielectric layers 104 that limit the discharge current and insulate the electrode pairs, and to facilitate the discharge conditions on the upper dielectric layer 104 top surface. A protective layer 105 on which magnesium oxide (MgO) is deposited is formed.

The rear panel 110 is arranged such that a plurality of discharge spaces, that is, barrier ribs 112 of a stripe type (or well type) for forming discharge cells are maintained in parallel. In addition, a plurality of address electrodes 113 which perform address discharge to generate vacuum ultraviolet rays are arranged in parallel with the partition wall 112. On the upper side of the rear panel 110, R, G, and B phosphors 114 which emit visible light for image display during address discharge are coated. A lower dielectric layer 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113.

A method of implementing image gradation in the plasma display panel having such a structure is shown in FIG. 2.

2 is a diagram illustrating a method of implementing image grayscale of a conventional plasma display panel.

As shown in FIG. 2, in the conventional method of expressing a gray level of a plasma display panel, a frame is divided into several subfields having different number of emission times, and each subfield is a reset period (RPD) for initializing all cells again. ) Is divided into an address period APD for selecting a cell to be discharged and a sustain period SPD for implementing gradation according to the number of discharges. For example, when displaying an image with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. 2, and eight subfields. Each of the SFs SF1 to SF8 is divided into a reset period, an address period, and a sustain period.

The reset period and the address period of each subfield are the same for each subfield. The address discharge for selecting the cell to be discharged is caused by the voltage difference between the address electrode and the transparent electrode which is the scan electrode. The sustain period is increased at a rate of 2 ⁿ ( ^where n = 0, 1, 2, 3, 4, 5, 6, 7) in each subfield. In this way, since the sustain period is different in each subfield, the gray scale of the image is expressed by adjusting the sustain period of each subfield, that is, the number of sustain discharges.

A driving method of a conventional plasma display panel according to the general image gray scale representation method is as follows in FIG. 3.

3 is a diagram illustrating a driving waveform generated by a driving apparatus of a conventional plasma display panel.

As shown in Fig. 3, the plasma display panel erases the reset period for initializing all the cells, the address period for selecting the cells to be discharged, the sustain period for maintaining the discharge of the selected cells, and the wall charges in the discharged cells. It is divided into an erase period for driving.

In the reset period, the rising ramp waveform Ramp-up is applied to all the scan electrodes at the same time in the setup period. This rising ramp waveform causes weak dark discharge within the full discharge cells. By this setup discharge, positive wall charges are accumulated on the address electrode and the sustain electrode, and negative wall charges are accumulated on the scan electrode.

During the set-down period, after the rising ramp waveform is supplied, the falling ramp waveform (Ramp-down) starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to a specific voltage level below the ground (GND) level voltage. By generating a weak erase discharge in the inside, the wall charges excessively formed in the scan electrode are sufficiently erased. By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulses are sequentially applied to the scan electrodes, and the positive data pulses are applied to the address electrodes in synchronization with the scan pulses. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the reset period are added, address discharge is generated in the discharge cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. The sustain electrode is supplied with a positive polarity voltage Vz during the set down period and the address period so as to reduce the voltage difference with the scan electrode so as to prevent mis-discharge with the scan electrode.

In the sustain period, a sustain pulse Su is applied to the scan electrode and the sustain electrodes alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge, occurs between the scan electrode and the sustain electrode every time the sustain pulse is applied.

After the sustain discharge is completed, in the erase period, a voltage of an erase ramp waveform Ramp-ers having a small pulse width and a low voltage level is supplied to the sustain electrode to erase the wall charge remaining in the cells of the full screen.

A driving apparatus of a conventional plasma display panel for generating such a driving waveform is as shown in FIG. 4.

4 is a view for explaining a driving apparatus of a conventional plasma display panel.

Referring to FIG. 4, a driving apparatus of a conventional plasma display panel includes an energy recovery circuit unit 300, a drive integrated circuit 350, a setup supply unit 310, a setdown supply unit 330, a negative scan voltage supply unit 320, and a scan. A seventh switch Q7 connected between the reference voltage supply unit 340 and the setup supply unit 310 and the drive integrated circuit 350, and a sixth switch connected between the setup supply unit 310 and the energy recovery circuit 300. (Q6) is provided.

The drive integrated circuit 52 is connected in a push / pull form and includes an energy recovery circuit 300, a setup supply unit 310, a set-down supply unit 330, a negative scan voltage supply unit 320, and a scan reference voltage supply unit. And the twelfth and thirteenth switches Q12 and Q13 to which a voltage signal is input from 340. The output line between the twelfth and thirteenth switches Q12 and Q13 is connected to any one of the scan electrode lines Y1 to Ym of the panel Cp.

The energy recovery circuit 300 recovers energy recovered from the panel Cp and supplies the sustain voltage Vs to the panel Cp.

The negative scan voltage supply unit 320 supplies a scan pulse Sp having a voltage magnitude of -Vy to the scan electrode lines Y1 to Ym in the address period.

The scan reference voltage supply unit 340 supplies the scan reference voltage Vsc to the scan electrode lines Y1 to Ym in the address period.

The setdown supply unit 330 supplies the falling ramp pulse to the scan electrode lines Y1 to Ym in the setdown period of the reset period.

The setup supply unit 310 supplies a ramp-up pulse to the scan electrode lines Y1 to Ym in the setup period of the reset period.

On the other hand, such a conventional driving apparatus uses a field effect transistor (FET) as a switching element. Since the FET is relatively expensive, it is a major factor that increases the manufacturing cost of the driving device of the plasma display panel. Therefore, the above-described driving apparatus of the conventional plasma display panel of FIG. 4 has a problem in that the manufacturing cost increases due to the relatively large number of switching elements, that is, FETs.

In addition, in the driving apparatus of the conventional plasma display panel as described above, since the voltage difference between the voltages applied to the first node n1 and the second node n2 is large, the seventh switch Q7 having a high breakdown voltage is generated. There is a problem that the manufacturing cost increases by using.

Here, the seventh switch Q7 includes an internal diode in a direction different from that of the sixth switch Q6, so that the voltage applied to the second node n2 is applied to the internal diode and the fourth switch of the sixth switch Q6 ( It is prevented from being supplied to the ground level GND via the internal diode of Q4). Meanwhile, a voltage of Vs is applied to the first node n1 and a voltage (-Vy) of the scan pulse Sp is applied to the second node n2 during the set down period. Here, if the voltage of Vs is set to about 180V and the scan pulse voltage (-Vy) is set to -70V, the seventh switch Q7 should have a breakdown voltage of approximately 300V (in consideration of the actual driving voltage margin). That is, since the switching element having a high breakdown voltage must be provided as the seventh switch Q7, the manufacturing cost increases.

In addition, since the reset voltage and the sustain voltage pass through the sixth switch Q6 and the seventh switch Q7, the switch must be a high breakdown voltage higher than the reset voltage for applying the setup waveform, thereby increasing the cost and increasing heat generation and energy loss. A problem occurs.

In the conventional plasma display panel driving apparatus, a predetermined control signal for controlling timing is supplied from a timing controller (not shown) to the scan drive integrated circuit, thereby switching the switching elements Q12 and Q13 of the scan drive integrated circuit. This is turned On (Off), looking at it as shown in FIG.

FIG. 5 is a view for explaining input of a control signal for controlling an operation of a scan drive integrated circuit in a driving apparatus of a conventional plasma display panel.

Referring to FIG. 5, control signals for controlling on / off timings of the switching elements Q12 and Q13 of the scan drive integrated circuit 350 of the driving apparatus of the conventional plasma display panel are supplied to OC1 and OC2. The scan drive integrated circuit 350 is a form of an integrated circuit in which a plurality of input / output pins are formed. The above-described OC1 and OC2 are not signals supplied to the gate terminals of the switching elements Q12 and Q13 of FIG. 5. The control signal is supplied to one or more of the plurality of input and output pins of the scan drive integrated circuit 350 of the integrated circuit form.

The switching timing of the switching elements in consideration of the above-described OC1 and OC2 in the driving apparatus of the conventional plasma display panel is shown in FIG. 6.

FIG. 6 is a view for explaining switching timing of switching elements and timing of a control signal of a scan drive integrated circuit in a driving apparatus of a conventional plasma display panel.

Referring to FIG. 6, in the setup period of the reset period, the above-described OC1 and OC2 are both off, that is, low level. Accordingly, the twelfth switch Q12 and the thirteenth switch Q13 of the scan drive integrated circuit 350 are turned off in the setup period of the reset period. At this time, the ninth switch Q9 is in an off state. Accordingly, the setup voltage output from the setup supply unit 310 of FIG. 4 is supplied to the panel Cp through the internal diode of the thirteenth switch Q13.

In the set-down period of the reset period, OC1 of the above-described OC1 and OC2 is on, that is, high level. Accordingly, in the set down period of the reset period, the twelfth switch Q12 of the scan drive integrated circuit 350 maintains the off state, and the thirteenth switch Q13 is turned on. At this time, the ninth switch Q9 is turned on. Accordingly, the setdown voltage output from the setdown supply unit 330 of FIG. 4 is supplied to the panel Cp through the thirteenth switch Q13.

In the address period after the reset period, OC2 of the above-described OC1 and OC2 is on, i.e., high level. Accordingly, in the address period after the reset period, the twelfth switch Q12 and the thirteenth switch Q13 of the scan drive integrated circuit 350 are turned on or off in accordance with the scanning order of the corresponding line, thereby addressing the address. This is done.

In the sustain period after the address period, OC1 of the above-described OC1 and OC2 is on, that is, high level. Accordingly, in the set down period of the reset period, the twelfth switch Q12 of the scan drive integrated circuit 350 maintains the off state, and the thirteenth switch Q13 is turned on. At this time, the ninth switch Q9 is turned on. Accordingly, the sustain voltage output from the energy recovery circuit unit 300 of FIG. 4 is supplied to the panel Cp through the thirteenth switch Q13.

As described above, in the driving apparatus of the conventional plasma display panel, a control signal for controlling the on / off timing of the switching elements Q12 and Q13 of the scan drive integrated circuit 350, that is, OC1 and OC2 is used to control the switching timing of other switching elements. It must be input separately from the control signal to control. As a result, the number of control signals for controlling the respective switching elements is increased, and thus the computation process for supplying such control signals becomes complicated. As a result, the control of the driving apparatus of the plasma display panel is complicated.

In order to solve this problem, an object of the present invention is to provide a plasma display driving apparatus which reduces the manufacturing cost by reducing the number of switching elements used.

Another object of the present invention is to provide a driving device of the plasma display panel which simplifies the control of the driving device of the plasma display panel.

The driving device of the plasma display panel of the present invention for achieving the above object is to supply a sustain voltage (Vs) to the scan electrode of the plasma display panel through a scan drive integrated circuit (IC), and to recover the reactive energy from the scan electrode The sustain voltage Vs supplied by the energy recovery circuit unit through the scan drive integrated circuit and the scan reference voltage Vsc supplied by the scan reference voltage source are applied to the scan electrode during the setup period of the reset period. A setup and scan reference voltage supply for supplying a setup pulse including ramp-up and supplying a scan reference voltage Vsc to the scan electrode in the address period, and a set-down after the setup period of the reset period through the scan drive integrated circuit. To supply a set-down pulse containing a ramp ramp down to the scan electrode And a negative scan voltage supply unit configured to supply a scan pulse Sp, which descends from the scan reference voltage, to the scan electrode in the address period after the reset period through the set-down supply unit and the scan drive integrated circuit.

The apparatus may further include a blocking switch between the energy recovery circuit unit and the setdown supply unit to block an electrical connection between the energy recovery circuit unit and the setdown supply unit when a scan pulse is supplied to the scan electrode.

In addition, the setup and scan reference voltage supply unit supplies a scan pulse through the scan drive integrated circuit to the scan electrode which gradually rises from the sustain voltage (Vs) to the sum of the sustain voltage (Vs) and the scan reference voltage (Vsc) during the setup period. Characterized in that.

In addition, the setup and scan reference voltage supply unit is connected to the voltage control capacitor and the scan control voltage and the scan reference voltage source, the drain is stored in the voltage control capacitor (Vsc) stored by the scan reference voltage source, the source (Source ) Is connected to the scan drive integrated circuit and is turned on in a setup period of a reset period so that a setup pulse gradually rising from the sustain voltage is supplied to the scan electrode through the scan drive integrated circuit, and turned on in an address period. A setup / scan common switch that supplies the scan reference voltage to the scan electrode through the scan drive integrated circuit, a setup selector connected to the gate terminal of the setup / scan common switch, and a setup terminal of the setup / scan common switch And a scan selector connected in parallel with the selector.

In addition, between the scan reference voltage source and the drain of the setup / scan common switch, a reverse current prevention unit for blocking the reverse current flowing from the setup / scan common switch to the scan reference voltage source is characterized in that it further comprises.

In addition, the setup selector has one end connected to the gate of the setup / scan common switch and the other end of the variable resistor supplied with a setup select signal for supplying a setup pulse to the scan electrode through the scan drive integrated circuit in the setup period of the reset period. And a first diode having an anode connected to one end of the variable resistor and a cathode connected to the other end of the variable resistor, wherein the scan selector comprises a setup selector at a gate terminal of the setup / scan common switch. And a second diode connected in parallel with the cathode of the second diode, the cathode of the second diode being commonly connected with the gate and the setup selector of the setup / scan common switch, the anode being a scan for supplying a scan reference voltage to the scan electrode in the address period. The reference voltage selection signal is supplied.

In addition, the scan drive integrated circuit includes a scan top switch and a scan bottom switch, and the scan drive integrated circuit is driven by a control signal supplied to the first control terminal and the second control signal terminal, and the scan selection is performed. A signal inverting unit inverting the scan selection signal supplied to the anode terminal of the negative second diode and supplying the scan selection signal to the first control terminal of the scan drive integrated circuit; and a setup selection signal supplied to the variable resistor of the setup selection unit and a second portion of the scan selection unit. And a signal adder configured to supply a logic sum (OR) signal of the scan reference voltage selection signal supplied to the anode terminal of the diode to the second control terminal of the scan drive integrated circuit.

In addition, during the setup period in which the setup selection signal is supplied to the variable resistor of the setup selector, a high level control signal is supplied to the first control terminal and the second control terminal of the scan drive integrated circuit. In an address period in which the scan selection signal is supplied to the anode of the second diode of the scan selection unit, a low level control signal is supplied to the first control terminal of the scan drive integrated circuit, and the second control terminal is supplied to the second control terminal. The high level control signal is supplied, so that the scan top switch and the scan bottom switch perform addressing.

In addition, the setup selector includes a variable resistor having one end connected to the gate of the setup / scan common switch, a cathode connected to the other end of the variable resistor, and an anode configured to supply a setup pulse to the scan electrode in the setup period of the reset period. A first diode to which a select signal is supplied, the scan selector being connected to an emitter terminal with a gate of a setup / scan common switch, and a collector terminal between a source terminal of a setup / scan common switch The connected control signal selection switch and the cathode are commonly connected to the emitter terminal of the control signal selection switch and the base of the control signal selection switch, and the anode is a scan for supplying a scan reference voltage to the scan electrode in the address period. The reference voltage selection signal is supplied.

In addition, the scan drive integrated circuit includes a scan top switch and a scan bottom switch, and the scan drive integrated circuit is driven by a control signal supplied to the first control terminal and the second control signal terminal, and the scan selection is performed. A signal inverting unit for inverting the scan selection signal supplied to the anode terminal of the negative second diode and supplying it to the first control terminal of the scan drive integrated circuit; and a setup selection signal and scanning supplied to the anode terminal of the first diode of the setup selection unit. And a signal adder configured to supply a logic sum (OR) signal of the scan reference voltage selection signal supplied to the anode terminal of the second diode of the selector to the second control terminal of the scan drive integrated circuit.

In the setup period in which the setup selection signal is supplied to the anode terminal of the first diode of the setup selection unit, a high level control signal is supplied to the first control terminal and the second control terminal of the scan drive integrated circuit, thereby scanning In the address period during which the top switch is turned on and the scan selection signal is supplied to the anode of the second diode of the scan selection unit, a low level control signal is supplied to the first control terminal of the scan drive integrated circuit, and the second A control signal of a high level is supplied to the control terminal, and the scan top switch and the scan bottom switch perform addressing.

Hereinafter, a driving apparatus of the plasma display panel of the present invention will be described in detail with reference to the accompanying drawings.

7 is a view for explaining the configuration of a driving apparatus of the plasma display panel of the present invention.

Referring to FIG. 7, an apparatus for driving a plasma display panel according to the present invention includes an energy recovery circuit unit 700, a setup and scan reference voltage supply unit 740, a set-down supply unit 710, a negative scan voltage supply unit 720, and the like. And a scan drive integrated circuit (Scan Drive IC) 730.

Here, the voltage difference between the energy recovery circuit 700 and the set-down supply 710 described above is relatively large. Accordingly, when scan pulses are supplied to the scan electrode lines Y1 to Ym between the energy recovery circuit unit 700 and the setdown supply unit 710, the electrical connection between the energy recovery circuit unit 700 and the setdown supply unit 710 is blocked. It is preferable that a blocking switch Qb is further included.

The scan drive integrated circuit 730 described above is connected in a push / pull form and includes an energy recovery circuit 700, a setup and scan reference voltage supply 740, a set-down supply 710, and a negative scan voltage supply ( It consists of a scan top switch (Q7: referred to as 'seventh switch') and a scan bottom switch (Q8: referred to as 'eighth switch'). . The output line between the seventh and eighth switches Q7 and Q8 is connected to any one of the scan electrode lines Y1 to Ym.

The energy recovery circuit unit 700 supplies the sustain voltage Vs to the panel Cp, and recovers the reactive energy of the panel Cp. The energy recovery circuit unit 700 may include, for example, an energy storage capacitor C1 for charging energy recovered from the scan electrode lines Y1 to Ym, an energy storage capacitor C1, and a scan drive integrated circuit. Inductor L1 connected between 730 and first switch Q1, fourth diode D4, fifth diode D5, and fifth connected in parallel between inductor L1 and external capacitor C1. 2 the switch Q2, the sustain voltage source supplying the sustain voltage Vs, and the base voltage source supplying the voltage of the third switch Q3 and the ground level GND connected between the inductor L1 and the aforementioned inductor And a fourth switch Q4 connected between L1.

Referring to the operation of the energy recovery circuit unit 700 as follows. First, it is assumed that the energy storage capacitor C1 is charged with the voltage Vs / 2. Here, when the above-described first switch Q1 is turned on, the voltage charged in the energy storage capacitor C1 is the first switch Q1, the fourth diode D4, and the inductor L1. The scan drive IC 730 is supplied to the scan drive integrated circuit 730 via a blocking switch Qb, and the scan drive IC 730 supplies the voltage supplied thereto to the scan electrode lines Y1 to Ym.

At this time, since the inductor L1 forms a series LC resonant circuit together with the capacitance Cp of the plasma display panel discharge cell, a voltage of Vs is supplied to the scan electrode lines Y1 to Ym.

Thereafter, the third switch Q3 is turned on. When the third switch Q3 is turned on, the sustain voltage Vs is supplied to the scan drive integrated circuit 730 via the internal diode of the blocking switch Qb. The scan drive integrated circuit 730 supplies the sustain voltage Vs supplied thereto to the scan electrode lines Y1 to Ym. Due to the sustain voltage Vs, the voltage level on the scan electrode lines Y1 to Ym maintains the sustain voltage Vs, and thus sustain discharge occurs in the discharge cells of the panel Cp.

After the sustain discharge occurs in the discharge cells of the panel Cp, the fourth switch Q4 is turned on. When the fourth switch Q4 is turned on, the scan electrode lines Y1 to Ym, the scan drive integrated circuit 730, the blocking switch Qb, the inductor L1, the fifth diode D5, and the second switch are turned on. Reactive power is recovered to the energy storage capacitor C1 via Q2. That is, energy from the plasma display panel Cp is recovered to the energy storage capacitor C1. Subsequently, the fourth switch Q4 is turned on to maintain the voltage on the scan electrode lines Y1 to Ym at the potential GND of the ground level.

In this way, the energy recovery circuit unit 700 recovers energy from the plasma display panel Cp, and then supplies a voltage to the scan electrode lines Y1 to Ym using the recovered energy to discharge the battery during the setup period and the sustain period. Excessive power consumption is reduced.

The negative scan voltage supply unit 720 includes a sixth switch Q6 connected between the first node n1 and the scan voltage source -Vy. The sixth switch Q6 switches in response to a control signal supplied from a timing controller (not shown) during the address period, thereby scanning the negative scan voltage (-Vy) falling from the scan reference voltage Vsc. ).

In the setdown supply unit 710, the blocking switch Qb is turned off and the fifth switch Q5 is turned on in the setdown period after the setup period of the reset period. The fifth switch Q5 has a predetermined slope with a negative scan voltage (-Vy) of the voltage of the first node n1 while the channel width is adjusted by the second variable resistor VR2 installed at the front end thereof. Lower At this time, a setdown pulse, that is, a ramp ramp down, is supplied to the scan electrode lines Y1 to Ym.

The setup and scan reference voltage supply unit 740 is connected to the sustain voltage Vs from the sustain voltage Vs supplied by the energy recovery circuit unit 700 in the setup period of the reset period through the scan drive integrated circuit 730 described above. The setup pulse which gradually rises to the sum of the scan reference voltages Vsc is supplied to the scan electrode lines Y1 to Ym, and the scan reference voltage Vsc is supplied to the scan electrode lines Y1 to Ym in the address period. This setup and scan reference voltage supply 740 includes voltage regulation capacitors C2 and 741, setup / scan common switches Qcom and 742, setup selector 743, scan selector 744 and energy path. Selection switches Q9 and 745;

The setup and scan reference voltage supply 740 scans from the setup / scan common switch 742 between the scan reference voltage source supplying the scan reference voltage Vsc and the drain of the setup / scan common switch 742. It is preferable to further include a reverse current prevention unit (D3, 746) for blocking the reverse current flowing to the reference voltage source.

Here, the aforementioned voltage adjusting capacitors C2 and 741 store the scan reference voltage Vsc supplied by the scan reference voltage source. Accordingly, the input voltage of the setup / scan common switch 742 is adjusted such that the voltage supplied to the aforementioned setup / scan common switch 742 is maintained at the scan reference voltage Vsc.

The setup / scan common switch (Qcom, 742) has a drain terminal connected in common with a scan reference voltage source (Vsc) for supplying a voltage adjusting capacitor 741 and a scan reference voltage, and a source terminal with a scan drive integrated. Is connected to the circuit 730. The setup / scan common switch 742 is turned on in the setup period of the reset period so that the scan electrode is supplied with a gradually rising set-up pulse from the above-described sustain voltage Vsc, and turned on in the address period to scan electrode. Supply a scan reference voltage (Vsc) to (Y).

The setup selector 743 described above is connected to a gate terminal of the setup / scan common switch 742.

The scan selector 744 is connected in parallel with the setup selector 743 to the gate terminal of the setup / scan common switch 742.

Here, a detailed configuration of the above-described setup selector 743 and scan selector 744 will be described with reference to FIG. 8.

8 is a view for explaining in detail the configuration of the setup selection unit 743 and the scan selection unit 744 of the driving apparatus of the plasma display panel of the present invention in FIG.

Referring to FIG. 8, this setup selector 743 has one end connected to the gate terminal of the setup / scan common switch 742, and the other end thereof has a setup pulse to the scan electrode Y in the setup period of the reset period. A variable resistor VR1 to which a setup selection signal for supplying a signal is supplied, an anode terminal is connected to one end of the variable resistor VR1 described above, and a cathode is connected to the other end of the variable resistor VR1. It comprises a first diode (D1) which is made.

The scan selector 744 includes a second diode D2 connected in parallel with the setup selector 743 at a gate terminal of the setup / scan common switch 742. Here, the cathode terminal of the second diode D2 is commonly connected to the gate of the setup / scan common switch 742 and the setup selector 743, and the anode reference terminal is a scan reference voltage to the scan electrode Y in the address period. The scan reference voltage selection signal for supplying (Vsc) is supplied.

The energy path selection switches Q9 and 745 are turned off when the above-described setup / scan common switch 742 is turned on to supply the setup voltage or the scan reference voltage Vsc to the scan electrode of the panel Cp. A setup voltage and a scan reference voltage are supplied to the seventh switch of 730.

The operation of the driving apparatus of the plasma display panel according to the present invention will be described in detail with reference to FIGS. 9, 10A, and 10B.

9 is a view for explaining the operation of the driving apparatus of the plasma display panel of the present invention of FIG.

10A to 10B are views for explaining in more detail the operation of the setup and scan reference voltage supply unit in the driving apparatus of the plasma display panel of the present invention of FIG.

9, 10A, and 10B, it is assumed that a voltage of Vs / 2 is charged in the energy storage capacitor C1 of the energy recovery circuit unit 700 of FIG. 7.

When the first switch Q1 of the energy recovery circuit unit 700 is turned on and the blocking switch Qb is turned on in the setup period of the reset period after the pre-reset period (Pre-Reset), the capacitor component of the inductor L1 and the panel. By LC resonance by (Cp), the voltage of the first node n1 rises to the sustain voltage Vs. Then, the sustain voltage Vs of the first node n1 is supplied to the scan electrode Y through the eighth switch Q8 of the scan drive integrated circuit 730 so that the voltage of the panel Cp is sustain voltage. (Vs) rises sharply. In addition, the scan reference voltage Vsc supplied from the scan reference voltage source is charged in the voltage adjusting capacitors C2 and 741 of the setup and scan reference voltage supply unit 740 connected to the first node n1 described above.

At this time, as shown in FIG. 10A, the setup selection signal is supplied from the timing controller not shown to the setup selection unit 743 described above. That is, the setup selection signal for supplying the setup pulse to the scan electrode Y in the setup period of the reset period is supplied to the variable resistor VR1 of the setup selection unit 743. In this case, the scan selection signal is not supplied to the scan selection unit 744. Then, the setup / scan common switch Qcom 742 is turned on, and the scan reference voltage Vsc is supplied to the setup / scan common switch 742 through the reverse current prevention unit 746 from the aforementioned scan reference voltage source. As a result, the scan reference voltage Vsc is supplied to the setup / scan common switch 742.

In addition, the sustain voltage Vs from the energy recovery circuit unit 700 passes through the first node n1 to the scan electrode Y of the panel Cp through the eighth switch Q8 of the scan drive integrated circuit 730. Is supplied, and the voltage of the panel Cp rises to the sustain voltage Vs.

Here, when the channel width is adjusted by the variable resistor VR1 of the setup selector 743 installed at its gate terminal, the setup / scan common switch 742 described above has a sustain voltage on the panel Cp. A ramp-up pulse that gradually rises from Vs to the sum of the sustain voltage Vs and the scan reference voltage Vsc (Vs + Vsc) is supplied through the scan drive integrated circuit 730, FIG. Form a waveform equal to the setup period of 9.

As such, the reason why the size of the setup pulse can be set to the sum of the sustain voltage Vs and the scan reference voltage Vsc (Vs + Vsc) in the setup period of the reset period is that the scan electrode is in the preliminary reset period before the reset period. A falling ramp pulse gradually descending to (Y) is supplied, and a predetermined positive voltage, for example, a sustain voltage (Vs), is supplied to the sustain electrode (Z), and the positive wall on the scan electrode (Y) before the reset period is supplied. This is because by accumulating charges and stacking negative wall charges on the sustain electrode Z, the state of wall charges can be sufficiently evened in the reset period even if the size of the setup pulse supplied in the setup period of the reset period is reduced.

The supply of the setup selection signal to the setup selector 743 is cut off in the setdown period after the setup period of this reset period. This causes the gate terminal of the setup / scan common switch 742 to be at a low level so that the setup / scan common switch 742 is turned off. The ramp-down, which gradually descends from a predetermined positive voltage, preferably the sustain voltage Vs, is supplied to the scan electrode Y by the set-down supply unit 740 of FIG. 7.

The scan reference voltage Vsc is supplied to the scan electrode Y in the address period after the set-down period. In this address period, a scan selection signal from a timing controller not shown by the scan selection unit 744 described above as shown in FIG. 10B. Is supplied. That is, the scan selection signal for supplying the scan reference voltage Vsc to the scan electrode Y in the address period is supplied to the anode terminal of the second diode of the scan selection unit 744 as shown in FIG. 8. In this case, the setup selection signal 743 is not supplied with the setup selection signal. Then, the setup / scan common switch Qcom 742 is turned on, and the scan reference voltage Vsc is supplied to the setup / scan common switch 742 through the reverse current prevention unit 746 from the aforementioned scan reference voltage source. As a result, the scan reference voltage Vsc is supplied to the setup / scan common switch 742.

Then, the above-described setup / scan common switch 742 supplies the scan reference voltage Vsc to the scan electrode Y through the seventh switch Q7 of the scan drive integrated circuit 730, and accordingly, FIG. The same waveform as the address period is formed.

As described above in detail, the driving apparatus of the plasma display panel of the present invention significantly reduces the magnitude of the setup pulse supplied in the setup period of the reset period, compared to the prior art, thereby preventing the dark discharge generated in the reset period. Reduced size improves contrast characteristics. In addition, the number of switching elements used, i.e., the number of field effect transistors (FETs) used in comparison with the conventional driving apparatus, can be reduced, and also the switching elements used by reducing the magnitude of the setup voltage supplied in the setup period of the reset period. Even if the withstand voltage characteristic of R is relatively small compared with the related art, stable driving can be performed, thereby reducing the manufacturing cost of the driving apparatus of the plasma display panel.

Meanwhile, in the driving apparatus of the plasma display panel of the present invention, a predetermined control signal for controlling timing is supplied from the timing controller (not shown) to the scan drive integrated circuit, thereby switching the switching elements Q12 and Q13 of the scan drive integrated circuit. ) Is turned On (Off), an example of such switching is as shown in FIG.

FIG. 11 is a diagram for describing switching timing of switching elements in the driving apparatus of the plasma display panel of the present invention.

Referring to FIG. 11, in the pre-reset period before the reset period, the seventh switch Q7 of the scan drive integrated circuit 730 of FIG. 7 is turned off, and the eighth switch Q8 is turned on. At this time, the energy path selection unit Q9 is turned on, and the setup selection signal supplied to the setup selection unit 743 and the scan selection signal supplied to the scan selection unit 744 maintain a low level, that is, supply is stopped. Is blocked.

In the setup period of the reset period, the seventh switch Q7 of the scan drive integrated circuit 730 of FIG. 7 is turned on, and the eighth switch Q8 is turned off. At this time, the energy path selection units Q9 and 745 are in an off state. Herein, the setup selection signal is supplied to the above-described setup selection unit 743, and the scan selection signal is blocked from being supplied to the scan selection unit 744. Accordingly, the setup pulse gradually rises from the sustain voltage Vs to the sum of the sustain voltage Vs and the scan reference voltage Vsc through the scan drive integrated circuit 730 to the scan electrode Y of the panel Cp. Is supplied.

In the set-down period of the reset period, the seventh switch Q7 of the scan drive integrated circuit 730 is turned off, and the eighth switch Q8 is turned on. At this time, the energy path selectors Q9 and 745 are turned on. Accordingly, the setdown voltage output by the setdown supply unit 710 of FIG. 7 is supplied to the panel Cp through the eighth switch Q8 of the scan drive integrated circuit 730. In this case, the supply of the setup selection signal to the setup selector 743 described above is cut off, and the supply of the scan selection signal to the scan selector 744 is cut off.

In the address period after the reset period, the supply of the setup selection signal to the setup selection unit 743 is cut off, and the scan selection signal is supplied to the scan selection unit 744. In addition, the seventh switch Q7 and the eighth switch Q8 of the scan drive integrated circuit 730 are turned on or off in accordance with the scanning order of the corresponding line. Accordingly, addressing is performed. For example of such addressing, in the address period, first, the seventh switch Q7 of the scan drive integrated circuit 730 is turned on, and the scan reference voltage is supplied to the scan electrode Y of the panel Cp. While the reference voltage Vsc is being supplied, the eighth switch Q8 of the scan drive integrated circuit 730 is turned on, and the negative scan voltage (-Vy) supplied by the negative scan voltage supply unit 720 is 8th. The switch is supplied to the scan electrode Y of the panel Cp. The negative scan voltage described above is a voltage falling from the aforementioned scan reference voltage Vsc.

In the sustain period after the address period, the seventh switch Q7 of the scan drive integrated circuit 730 remains off, and the eighth switch Q8 is turned on. At this time, the energy path selection units 745 and Q9 are turned on. In addition, the supply of the setup selection signal to the setup selector 743 is cut off, and the supply of the scan selection signal to the scan selector 744 is cut off. Accordingly, the sustain voltage Vs output from the energy recovery circuit unit 700 of FIG. 7 is supplied to the panel Cp through the eighth switch Q8 of the scan drive integrated circuit 700.

As described above, a control signal supplied to the scan drive integrated circuit 730 and a process of forming the control signal in order to adjust the switching timing of the scan drive integrated circuit 730 in the driving apparatus of the plasma display panel according to the present invention are illustrated in FIGS. Referring to Figure 12b as follows.

12A to 12B illustrate a control signal for controlling switching of switching elements of a scan drive integrated circuit and a process of forming the same in the driving apparatus of the plasma display panel according to the present invention.

First, referring to FIG. 12A, the control signals OC1 and OC2 for controlling the switching timing of the switching elements Q7 and Q8 of the scan drive integrated circuit 730 are the eighth in the pre-reset period. In order to make the switch Q8 turn on and the seventh switch Q7 turn off, OC1 has a high level value and OC2 has a low level value. In other words, OC1 is on and OC2 is off during the preliminary reset period.

In the setup period of the reset period Reset after the preliminary reset period, the seventh switch Q7 is turned on, and the values of OC1 and OC2 are set to high levels so that the eighth switch Q8 is turned off. Has In other words, OC1 and OC2 are turned on in the preliminary reset period, respectively.

In the set-down period after the setup period of the above-described reset period, the eighth switch Q8 is turned on, and the seventh switch Q7 is turned off so that OC1 has a high level value, and OC2 has a low level. It has a value of (Low Level). In other words, OC1 is on and OC2 is off during the preliminary reset period.

In the address period after the above-described set-down period, in order for the seventh switch Q7 and the eighth switch Q8 to operate alternately to perform addressing, OC1 sets a low level value. OC2 has a high level value. In other words, OC1 is off and OC2 is on during the preliminary reset period.

In the sustain period after the above-described address period, the eighth switch Q8 is turned on, and the seventh switch Q7 is turned off so that OC1 has a high level value, and OC2 has a low level. It has a value of (Low Level). In other words, OC1 is on and OC2 is off during the preliminary reset period.

)이고, OC2는 (b)와 같이 전술한 도 11에서의 셋업 선택 신호(Setup)와 스캔 선택 신호(Scan)의 논리 합(OR)이다.Next, referring to FIG. 12B, the control signals OC1 and OC2 as shown in FIG. 12A may be generated as the setup selection signal and the scan selection signal in FIG. 11. For example, OC1 in FIG. 12A is an inverted signal of the scan selection signal Scan in FIG. 11 described above (a).

OC2 is a logical sum OR of the setup selection signal Setup and the scan selection signal Scan in FIG. 11 described above as shown in (b).

Accordingly, although the control signals OC1 and OC2 are generated and supplied separately for controlling the switching timing of the switching elements of the scan drive integrated circuit, in the present invention, the control signals for controlling the switching timing of the switching elements of the scan drive integrated circuit are provided. By generating and supplying OC1 and OC2 in the appropriate combination of control signals of other switching elements, that is, setup selection signal and scan selection signal, control of the scan drive integrated circuit is easier.

The configuration of the driving apparatus of the plasma display panel of the present invention for generating a control signal for controlling switching timing of the switching elements of the scan drive integrated circuit as a setup selection signal and a scan selection signal will be described with reference to FIG. 13. .

FIG. 13 is a diagram for describing a configuration of a driving apparatus of a plasma display panel of the present invention for generating a control signal for controlling switching timing of switching elements of a scan drive integrated circuit as a setup selection signal and a scan selection signal.

Referring to FIG. 13, the scan reference voltage Vsc is applied to the scan electrode Y in the supply line of the setup selection signal for supplying the setup pulse to the scan electrode Y in the setup period of the reset period and in the address period of the reset period. A signal adder 1301 is formed in parallel with the supply line of the scan selection signal for supplying, and the scan selection signal supply line for supplying the scan reference voltage Vsc to the scan electrode Y in the address period of the reset period. In parallel with the signal inversion unit 1300 is formed.

Accordingly, both the scan selection signal and the setup selection signal are supplied to the signal summing unit 1301, and the scan selection signal among the scan selection signal and the setup selection signal is supplied to the signal inversion unit 1300.

Here, the above-described signal summing unit 1301 outputs a high level signal when at least one of the scan selection signal and the setup selection signal input as the OR gate is turned on.

The signal inversion unit 1300 outputs a low level signal when the scan selection signal input as the logic inversion gate is at a high level, while the scan selection signal input as the logic inversion gate is at a low level. Outputs a high level signal.

As a result, a logic inversion signal of the scan selection signal is output to the output terminal of the signal inverting unit 1300 to generate the control signal OC1 of the scan drive integrated circuit, and the scan selection signal and the setup selection to the output terminal of the signal summing unit 1301. The OR signal of the signal is output to generate the control signal OC2 of the scan drive integrated circuit.

The operation of the driving apparatus of the plasma display panel of FIG. 13 will now be described with reference to FIGS. 14A to 14B.

14A to 14B are views for explaining the operation of the driving apparatus of the plasma display panel of the present invention in FIG. 13 in more detail.

First, referring to FIG. 14A, the setup selection signal is supplied to the scan electrode Y in a setup period in which a setup pulse rising gradually from the sustain voltage Vs to the sum of the sustain voltage Vs and the scan reference voltage Vsc is supplied. Is supplied to the high level, that is, the setup selection signal is supplied to the variable resistor VR1 of the setup selection unit (unsigned), and the scan is performed to the anode terminal of the second diode D2 of the scan selection unit (unsigned). When supply of the selection signal is cut off, the signal summing unit 1301 outputs a high level of OC2. Accordingly, the control signal OC2 for controlling the switching timing of the switching elements Q7 and Q8 of the scan drive integrated circuit 730 is turned high, that is, on.

In this case, the signal inverting unit 1300 receives a low level scan selection signal and outputs a high level OC1. Accordingly, the control signal OC1 for controlling the switching timing of the switching elements Q7 and Q8 of the scan drive integrated circuit 730 is turned high, that is, on.

Accordingly, in the setup period, OC1 is turned on (high level) and OC2 is turned on (high level) so that the seventh switch Q7 is turned on and the eighth switch Q8 is turned off.

Next, referring to FIG. 14B, in the address period in which the scan reference voltage Vsc is supplied to the scan electrode Y, the setup selection signal goes to the low level, that is, to the variable resistor VR1 of the setup selection unit (unsigned). When the supply of the setup selection signal is cut off and the scan selection signal is supplied to the anode terminal of the second diode D2 of the scan selection unit (unsigned), the signal summing unit 1301 outputs a high level of OC2. . Accordingly, the control signal OC2 for controlling the switching timing of the switching elements Q7 and Q8 of the scan drive integrated circuit 730 is turned high, that is, on.

In this case, the signal inverting unit 1300 receives the high level scan selection signal and outputs the low level OC1. Accordingly, the control signal OC1 for controlling the switching timing of the switching elements Q7 and Q8 of the scan drive integrated circuit 730 is turned low, that is, off.

Accordingly, in the setup period, OC1 is turned off (low level), OC2 is turned on (high level) so that the seventh switch Q7 is turned on and the eighth switch Q8 alternately operates to perform addressing. .

As described above, in the driving apparatus of the plasma display panel of the present invention, a control signal for controlling the on / off timing of the switching elements Q7 and Q8 of the scan drive integrated circuit 730, that is, switching timings of switching elements having different OC1 and OC2. Instead of being input separately from the control signal for controlling the control signal, the control signal of the other switching elements is generated and input by a proper combination of the setup selection signal and the scan selection signal, thereby making it easier to control the driving apparatus.

On the other hand, unlike the above-described driving device of the plasma display panel of the present invention, it is also possible to configure a setup and scan reference voltage supply, which will be described with reference to FIG.

15 is a view for explaining another configuration of the driving apparatus of the plasma display panel of the present invention.

Referring to FIG. 15, an apparatus for driving a plasma display panel according to the present invention includes an energy recovery circuit 700, a setup and scan reference voltage supply unit 740, a set-down supply unit 710, a negative scan voltage supply unit 720, and the like. And a scan drive integrated circuit (730), preferably an energy recovery circuit portion when a scan pulse is supplied to the scan electrodes (Y1 to Ym) between the energy recovery circuit portion 700 and the set-down supply portion 710. A blocking switch Qb is further included to block the electrical connection between the 700 and the setdown supply 710.

15 is different from the configuration of the setup and scan reference voltage supply unit 740, compared with FIG.

In the driving apparatus of FIG. 15, the setup of the reference numeral 740 and the scan reference voltage supply unit are sustained from the sustain voltage Vs supplied by the energy recovery circuit unit 700 described above in the setup period of the reset period through the scan drive integrated circuit 730. The setup pulse which gradually rises up to the sum of the voltage Vs and the scan reference voltage Vsc is supplied to the scan electrodes Y1 to Ym, and the scan reference voltage Vsc to the scan electrode lines Y1 to Ym in the address period. The setup and scan reference voltage supply 740 includes voltage regulation capacitors C2 and 741, setup / scan common switches Qcom and 742, setup selector 743, and scan selector 744. ) And energy path selection switches Q9 and 745.

Here, the above-described setup selector 743 is connected to the variable resistor VR1 having one end connected to the gate of the setup / scan common switch 742, the cathode connected to the other end of the variable resistor VR1, and reset to the anode. And a first diode D1 to which a setup select signal is supplied for supplying a setup pulse to the scan electrode Y in the setup period of the period.

The scan selector 744 has an emitter terminal connected to the gate terminal of the setup / scan common switch 742, and a collector terminal connected between the source terminal of the setup / scan common switch 744. The control signal selector switch T1 and the cathode are commonly connected to the emitter terminal of the control signal selector switch T1 and the base of the control signal selector switch T1, and the anode serves as the scan electrode Y in the address period. ) A second diode D2 to which a scan reference voltage selection signal for supplying a scan reference voltage Vsc is supplied.

The operation of the driving apparatus of the plasma display panel of FIG. 15 will be described below with reference to FIG. 9.

It is assumed that the energy storage capacitor C1 of the energy recovery circuit unit 700 of FIG. 15 is charged with a voltage of Vs / 2.

When the first switch Q1 of the energy recovery circuit unit 700 is turned on and the blocking switch Qb is turned on in the setup period of the reset period after the pre-reset period (Pre-Reset), the capacitor component of the inductor L1 and the panel. By LC resonance by (Cp), the voltage of the first node n1 rises to the sustain voltage Vs. Then, the sustain voltage Vs of the first node n1 is supplied to the scan electrode Y through the eighth switch Q8 of the scan drive integrated circuit 730 so that the voltage of the panel Cp is sustain voltage. (Vs) rises sharply. In addition, the scan reference voltage Vsc is charged to the voltage adjusting capacitors Q2 and 741 of the setup and scan reference voltage supply unit 740 connected to the first node n1 described above.

At this time, the setup selection signal is supplied from the timing controller (not shown) to the setup selection unit 743 described above. That is, the setup selection signal for supplying the setup pulse to the scan electrode Y in the setup period of the reset period is supplied to the anode terminal of the first diode D1 of the setup selection unit 743. In this case, the scan selection signal is not supplied to the scan selection unit 744. Then, the base terminal and the emitter terminal of the control signal selector switch T1 of the scan selector 744 are at the same level, so that the control signal selector switch T1 is turned off, whereby the setup / scan common. The switches Qcom and 742 are turned on, and the scan reference voltage Vsc is supplied to the setup / scan common switch 742 through the reverse current prevention unit 746 from the aforementioned scan reference voltage source. As a result, the scan reference voltage Vsc is supplied to the setup / scan common switch 742.

Here, the channel width is adjusted by the variable resistor VR1 of the setup selector 743 installed at its gate terminal in the aforementioned setup / scan common switch 742, and thus the sustain voltage Vs is applied to the panel Cp. Is supplied with a setup pulse including a ramp-up pulse that gradually rises from the sustain voltage Vs to the sum Vs + Vsc of the scan reference voltage Vsc. This setup pulse is supplied to the scan electrode Y through the seventh switch Q7 and the eighth switch Q8 of the scan drive integrated circuit 730 to form a waveform as in the setup period of FIG.

The supply of the setup selection signal to the setup selector 743 is cut off in the setdown period after the setup period of this reset period. As a result, the gate terminal of the setup / scan common switch 742 becomes a low level, and the setup / scan common switch 742 is turned off. Then, a ramp R-Down gradually descending from a predetermined positive voltage, preferably the sustain voltage Vs, is supplied to the scan electrode Y by the set-down supply unit 740 of FIG. 15.

The scan reference voltage Vsc is supplied to the scan electrode Y in the address period after the set down period. In this address period, the scan selection signal is supplied from the timing controller (not shown) to the scan selection unit 744 described above. That is, the scan selection signal for supplying the scan reference voltage Vsc to the scan electrode Y in the address period is supplied to the anode terminal of the second diode of the scan selector 744. In this case, the setup selection signal 743 is not supplied with the setup selection signal. Then, the base terminal and the emitter terminal of the control signal selection switch T1 are turned to the same level, and the setup / scan common switches Qcom and 742 are turned on, and the reverse current prevention unit ( The scan reference voltage Vsc is supplied to the setup / scan common switch 742 through 746. As a result, the scan reference voltage Vsc is supplied to the setup / scan common switch 742.

Then, the above-described setup / scan common switch 742 supplies the scan reference voltage Vsc to the scan electrode Y through the seventh switch Q7 of the scan drive integrated circuit 730, and accordingly, FIG. The same waveform as in the address period is formed.

As described in detail above, in another structure of the driving apparatus of the plasma display panel of the present invention, the number of switching elements, that is, the number of FETs (Field Effect Transistors) used in comparison with the conventional driving apparatus, is reduced, thereby reducing the plasma display panel. This reduces the manufacturing cost of the drive device.

The generation and supply of a control signal for controlling the switching timing of the switching elements Q7 and Q8 of the scan drive integrated circuit 730 in the driving apparatus of the plasma display panel of the present invention as shown in FIG. Since it is the same as that of the drive apparatus of the plasma display panel of this invention, overlapping description is abbreviate | omitted.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above in detail, the present invention sets the magnitude of the setup pulse supplied in the setup period of the reset period to the sum of the sustain voltage Vs and the scan reference voltage Vsc, and supplies the setup pulse and the scan reference voltage. By reducing the number of switching elements used in the drive device to reduce the manufacturing cost of the drive device of the plasma display panel.

In addition, the control signal for controlling the switching timing of the switching elements of the scan drive integrated circuit is not supplied separately, but is generated and supplied as a combination of the control signals of the other switching elements, thereby providing more control of the driving apparatus of the plasma display panel. There is an effect to facilitate.

Claims (11)

An energy recovery circuit unit which supplies a sustain voltage Vs to a scan electrode of the plasma display panel through a scan drive integrated circuit and recovers reactive energy from the scan electrode; Ramp-Up to the scan electrode in the setup period of the reset period with the sustain voltage Vs supplied by the energy recovery circuit unit and the scan reference voltage Vsc supplied by the scan reference voltage source through the scan drive integrated circuit. A setup and scan reference voltage supply unit configured to supply a setup pulse including a setup pulse and supply the scan reference voltage Vsc to the scan electrode in an address period; A set-down supply unit configured to supply a set-down pulse including a ramp ramp down to the scan electrode in the set-down period after the setup period of the reset period through the scan drive integrated circuit; And A negative scan voltage supply unit configured to supply a scan pulse Sp falling from the scan reference voltage to the scan electrode in the address period after the reset period through the scan drive integrated circuit; Driving device for a plasma display panel comprising a. The method of claim 1, And a blocking switch between the energy recovery circuit unit and the setdown supply unit to block an electrical connection between the energy recovery circuit unit and the setdown supply unit when a scan pulse is supplied to the scan electrode. The drive unit of the panel. The method of claim 1, The setup and scan reference voltage supply unit And supplying a setup pulse gradually rising from the sustain voltage (Vs) to the sum of the sustain voltage (Vs) and the scan reference voltage (Vsc) to the scan electrode through the scan drive integrated circuit. A drive device for a plasma display panel. The method of claim 3, wherein The setup and scan reference voltage supply unit A voltage adjusting capacitor configured to store a scan reference voltage Vsc supplied by the scan reference voltage source; A drain is commonly connected to the voltage regulating capacitor and the scan reference voltage source, a source is connected to the scan drive integrated circuit, and is turned on in a setup period of a reset period to supply the scan drive integrated circuit. A setup / scan common switch that supplies a setup pulse that gradually rises from the sustain voltage to the scan electrode and that is turned on in an address period to supply the scan reference voltage to the scan electrode through the scan drive integrated circuit ; A setup selector connected to a gate terminal of the setup / scan common switch; And A scan selector connected in parallel with the setup selector to a gate terminal of the setup / scan common switch; Driving device for a plasma display panel comprising a. The method of claim 4, wherein And a reverse current preventing unit for blocking a reverse current flowing from the setup / scan common switch to the scan reference voltage source between the scan reference voltage source and the drain of the setup / scan common switch. . The method of claim 4, wherein The setup selector A variable resistor having one end connected to the gate of the setup / scan common switch and the other end supplied with a setup select signal for supplying a setup pulse to the scan electrode through the scan drive integrated circuit in a setup period of a reset period; A first diode is connected to one end of the variable resistor and a cathode is connected to the other end of the variable resistor. Including, The scan selector A second diode connected in parallel with the setup selector at a gate terminal of the setup / scan common switch; The cathode of the second diode is commonly connected to the gate of the setup / scan common switch and the setup selector, and an anode is supplied with a scan reference voltage selection signal for supplying a scan reference voltage to the scan electrode in an address period. A drive device for a plasma display panel. The method of claim 6, The scan drive integrated circuit includes a scan top switch and a scan bottom switch. The scan drive integrated circuit is driven by a control signal supplied to a first control terminal and a second control signal terminal. A signal inversion unit inverting a scan selection signal supplied to an anode terminal of the second diode of the scan selection unit and supplying the scan selection signal to a first control terminal of the scan drive integrated circuit; And controlling a logic sum (OR) signal of the setup selection signal supplied to the variable resistor of the setup selector and the scan reference voltage selection signal supplied to the anode terminal of the second diode of the scan selector. Signal adder to supply terminal Driving device for a plasma display panel comprising a. The method of claim 7, wherein In a setup period in which a setup selection signal is supplied to the variable resistor of the setup selection unit, a high level control signal is supplied to the first control terminal and the second control terminal of the scan drive integrated circuit, thereby providing the scan top. The switch is on, In the address period during which the scan selection signal is supplied to the anode of the second diode of the scan selection unit, a low level control signal is supplied to the first control terminal of the scan drive integrated circuit, and the second control terminal is provided. The furnace is supplied with a control signal having a high level, and the scan top switch and the scan bottom switch perform addressing. The method of claim 4, wherein The setup selector A variable resistor whose one end is connected to the gate of the setup / scan common switch, The first diode is connected to the other end of the variable resistor and the anode is supplied with a setup select signal for supplying a setup pulse to the scan electrode in the setup period of the reset period. Including, The scan selector A control signal selection switch connected to an emitter terminal of the setup / scan common switch and a collector terminal connected to a source terminal of the setup / scan common switch; The cathode is commonly connected to the emitter terminal of the control signal selection switch and the base of the control signal selection switch, and the anode has a scan reference voltage selection signal for supplying a scan reference voltage to the scan electrode in an address period. It is supplied, the drive device of the plasma display panel. The method of claim 9, The scan drive integrated circuit includes a scan top switch and a scan bottom switch. The scan drive integrated circuit is driven by a control signal supplied to a first control terminal and a second control signal terminal. A signal inversion unit inverting a scan selection signal supplied to an anode terminal of the second diode of the scan selection unit and supplying the scan selection signal to a first control terminal of the scan drive integrated circuit; A scan sum signal (OR) between a setup selection signal supplied to an anode terminal of the first diode of the setup selection unit and the scan reference voltage selection signal supplied to an anode terminal of the second diode of the scan selection unit; A signal summing unit for supplying to the second control terminal of the Driving device for a plasma display panel comprising a. The method of claim 10, In a setup period in which a setup selection signal is supplied to an anode terminal of a first diode of the setup selection unit, a high level control signal is supplied to the first control terminal and the second control terminal of the scan drive integrated circuit. The scan top switch is turned on, In the address period during which the scan selection signal is supplied to the anode of the second diode of the scan selection unit, a low level control signal is supplied to the first control terminal of the scan drive integrated circuit, and the second control terminal is provided. The furnace is supplied with a control signal having a high level, and the scan top switch and the scan bottom switch perform addressing.

Images