KR100870224B1 - Circuit for driving plasma display panel - Google Patents

Abstract

The plasma display panel driving circuit 100 includes a scan-electrode driving circuit 110 for applying a driving voltage to the scan electrode, and the scan-electrode driving circuit 110 holds for applying a sustain-discharge pulse to the scan electrode. A clamp circuit 112 and a reset circuit 113 for applying a reset pulse to the scan electrodes. The first sustain-clamp circuit comprises a first power supply terminal VS having a voltage higher than the ground voltage. The reset circuit includes a second power supply terminal VW having a voltage lower than the ground voltage. The first holding-clamp circuit includes a first current blocking element S5 which prevents current from flowing from the first ground terminal to the second power supply terminal, which is applied when a voltage is applied to the scan electrode through the first power supply terminal. Located in a current path other than the current path through which the current flows.

Plasma display panel drive circuit, scan electrode drive circuit, sustain clamp circuit, reset circuit

Description

Plasma Display Panel Driving Circuit {CIRCUIT FOR DRIVING PLASMA DISPLAY PANEL}

1 is a circuit diagram of a conventional circuit for driving a plasma display panel (PDP).

2 is a timing chart showing the operation of the circuit shown in FIG. 1;

3 is a circuit diagram of another conventional circuit for driving a plasma display panel.

4 is a circuit diagram of a plasma display panel (PDP) driving circuit according to the first embodiment of the present invention.

5 is a circuit diagram of a plasma display panel (PDP) driving circuit according to a second embodiment of the present invention.

6 is a circuit diagram of a plasma display panel (PDP) driving circuit according to a third embodiment of the present invention.

7 is a circuit diagram of a plasma display panel (PDP) driving circuit according to a fourth embodiment of the present invention.

8 is a circuit diagram of a plasma display panel (PDP) driving circuit according to a fifth embodiment of the present invention.

9 is a circuit diagram of a plasma display panel (PDP) driving circuit according to a sixth embodiment of the present invention.

10 is a circuit diagram of a plasma display panel (PDP) driving circuit according to a seventh embodiment of the present invention.

Fig. 11 is a circuit diagram of a plasma display panel (PDP) driving circuit according to an eighth embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: plasma display panel driving circuit

Cp: plasma display panel

110: Y-electrode driving circuit

120: X-electrode drive circuit

111: collection circuit

112: holding clamp circuit

VS: power supply terminal

S3: transistor switch

G1: ground terminal

S4: transistor switch

113: reset circuit

VW: power supply terminal

S8: transistor switch

S5: transistor switch

124: resettable circuit

122: holding clamp circuit

S12: transistor switch

G2: ground terminal

S13: transistor switch

VRST: power terminal

S10: transistor switch

S11: transistor switch

200: plasma display panel driving circuit

212: holding-clamp circuit

VP: power supply terminal

S7: transistor switch

S6: transistor switch

300: plasma display panel driving circuit

312: holding-clamp circuit

D5: diode

400: plasma display panel driving circuit

412: holding-clamp circuit

D6: diode

500: plasma display panel driving circuit

512: holding-clamp circuit

600: plasma display panel drive circuit

612: holding clamp circuit

700: plasma display panel driving circuit

712: holding-clamp circuit

800: plasma display panel driving circuit

822: holding-clamp circuit

The present invention relates to a plasma display panel driving circuit.

1 is a circuit diagram of a conventional circuit 1000 for driving a plasma display panel (PDP).

As shown in Fig. 1, the conventional circuit 1000 applies a driving voltage to a terminal (hereinafter referred to as a "scan electrode terminal") of a Y electrode (scan electrode) of a plasma display panel Cp. X-electrode driving circuit 1200 for applying a driving voltage to Y-electrode driving circuit 1100 and a terminal (hereinafter referred to as "common-electrode terminal") of an X electrode (common electrode) of plasma display panel Cp. ).

The Y-electrode drive circuit 1100 includes a collection circuit 111, a sustaining-clamp circuit 1102, a reset circuit (priming circuit 113), a scan IC 114, And a first coil L1 electrically connected between the collection circuit 111 and the holding-clamp circuit 1102.

The collection circuit 111 consists of a first capacitor C1, a first transistor switch S1, a second transistor switch S2, a first diode D1, and a second diode D2.

One end of the first capacitor C1 is grounded and the other end is electrically connected to both the drain terminal of the first transistor switch S1 and the source terminal of the second transistor switch S2.

The first and second diodes D1 and D2 are electrically connected in series with each other between the source terminal of the first transistor switch S1 and the drain terminal of the second transistor switch S2.

Specifically, the source terminal of the first transistor switch S1 is electrically connected to the anode terminal of the first diode D1, and the cathode terminal of the first diode D1 is electrically connected to the anode terminal of the second diode D2. Is connected, and the cathode terminal of the second diode D2 is electrically connected to the drain terminal of the second transistor switch S2.

The sustain-clamp circuit 1102 includes third to sixth transistor switches S3 to S6.

The third transistor switch S3 is electrically connected to both the drain terminal electrically connected to the power supply terminal VS, the drain terminal of the fifth transistor switch S5 and the drain terminal of the fourth transistor switch S4. Has a source terminal.

The fourth transistor switch S4 has a source terminal electrically connected to the ground terminal G1.

The fifth transistor switch S5 has a source terminal electrically connected to the source terminal of the sixth transistor switch S6.

One end of the first coil L1 is connected to a second junction J2 in which the third to fifth transistor switches S3, S4, and S5 are electrically connected to each other, and the other end thereof is the first and second diodes. D1 and D2 are electrically connected to the first connection point J1 which is electrically connected to each other.

The reset circuit 113 is composed of a seventh transistor switch S7 and an eighth transistor switch S8.

The seventh transistor switch S7 has a drain terminal electrically connected to the power supply terminal VP, and a source terminal electrically connected to the drain terminal of the eighth transistor switch S8.

The eighth transistor switch S8 has a source terminal electrically connected to the power supply terminal VW.

The sixth transistor switch S6 has a drain terminal electrically connected to a third connection point J3 in which the source terminal of the seventh transistor switch S7 and the drain terminal of the eighth transistor switch S8 are electrically connected to each other. .

The scan IC 114 includes a sixteenth transistor switch S21, a seventeenth transistor switch S22, a seventh diode D10, an eighth diode D11, a first inverter I21, and a second inverter I22. Is done.

The sixteenth transistor switch S21 is electrically connected to a drain terminal electrically connected to both the power supply terminal VH and the cathode terminal of the seventh diode D10, and to the drain terminal of the seventeenth transistor switch S22. Has a source terminal.

The seventeenth transistor switch S22 has a source terminal electrically connected to the above-mentioned third connection point J3 and the anode terminal of the eighth diode D11.

The eighth diode D11 is a sixth connection point J6 in which the anode terminal of the seventh diode D10 and the source terminal of the sixteenth transistor switch S21 and the drain terminal of the seventeenth transistor switch S22 are electrically connected to each other. ) Has a cathode terminal electrically connected to both.

The first inverter I21 has an output terminal electrically connected to both the gate terminal of the sixteenth transistor switch S21 and the input terminal of the second inverter I22.

The second inverter I22 has an output terminal electrically connected to both the input terminal of the seventeenth transistor switch S22 and the first inverter I21.

The fifth connection point J5 in which the fifth and sixth diodes D10 and D11 are electrically connected to each other is electrically connected to the scan-electrode terminal of the plasma display panel Cp.

The X-electrode drive circuit 1200 includes a collection circuit 121, a sustain-clamp circuit 1202, a sub-voltage application circuit 123, a reset-enhancing circuit 124, and a second coil ( L2).

The sub-voltage application circuit 123 includes a ninth transistor switch S9 having a drain terminal electrically connected to the power supply terminal VSW.

The resetability improving circuit 124 includes a tenth transistor switch S10 having a source terminal electrically connected to the power supply terminal VRST, and a drain terminal electrically connected to the source terminal of the ninth transistor switch S9. do.

A ninth connection point J9 in which the source terminal of the ninth transistor switch S9 and the drain terminal of the tenth transistor switch S10 are electrically connected to each other is electrically connected to the common-electrode terminal of the plasma display panel Cp. .

The sustain-clamp circuit 1202 includes eleventh through thirteenth transistor switches S11 through S13.

The eleventh transistor switch S11 is a source terminal electrically connected to the common-electrode terminal of the plasma display panel Cp through the ninth connection point J9, and the source terminal and the thirteenth transistor of the twelfth transistor switch S12. It has a drain terminal electrically connected to both the drain terminals of switch S13.

The thirteenth transistor switch S13 has a source terminal electrically connected to the ground terminal G2.

The twelfth transistor switch S12 has a drain terminal electrically connected to the power supply terminal VS.

The collection circuit 121 includes a fourteenth transistor switch S14, a fifteenth transistor switch S15, a third diode D3, a fourth diode D4, and a second capacitor C2.

One end of the second capacitor C2 is grounded and the other end is electrically connected to both the drain terminal of the fourteenth transistor switch S14 and the source terminal of the fifteenth transistor switch S15.

The third and fourth diodes D3 and D4 are electrically connected in series with each other between the source terminal of the fourteenth transistor switch S14 and the drain terminal of the fifteenth transistor switch S15.

Specifically, the source terminal of the fourteenth transistor switch S14 is electrically connected to the anode terminal of the third diode D3, and the cathode terminal of the third diode D3 is electrically connected to the anode terminal of the fourth diode D4. Is connected, and the cathode terminal of the fourth diode D4 is electrically connected to the drain terminal of the fifteenth transistor switch S15.

One end of the second coil L2 is connected to the seventh connection point J7 where the third and fourth diodes D3 and D4 are electrically connected to each other, and the other end is provided with the eleventh, twelfth and thirteenth transistors S11, S12 and S13 is electrically connected to the eighth connection point J8 electrically connected to each other.

The voltage applied to the power supply terminal VP is higher than the voltage applied to the power supply terminal VS.

The voltage applied to the power supply terminal VSW is higher than the voltage applied to the power supply terminal VS.

The voltage applied to the power supply terminals VS, VP and VSW is higher than the voltages of the first and second ground terminals G1 and G2.

On the other hand, the voltage applied to the power supply terminals VW and VRST is lower than the voltages of the first and second ground terminals G1 and G2.

The voltage applied to the power supply terminal VH is higher by α than the voltage applied to the scan electrode terminal of the plasma display panel Cp except for the scan period (see FIG. 2).

The control signal is input to each of the gate terminals of the first to fifteenth transistor switches S1 to S15 and to each of the input terminals of the first and second inverters I21 and I22 of the scan IC 114. On / off control is performed for the first to seventeenth transistor switches S1 to S15, S21 and S22 in accordance with this control signal.

2 is a timing chart showing the operation of the PDP driving circuit 1000.

2 shows waveforms of control signals input to the gate terminals of the first to fifteenth transistor switches S1 to S15, waveforms of voltages applied to the scan electrodes of the plasma display panel Cp (Y-electrode waveforms), and plasma displays. The waveform of the voltage applied to the common electrode of the panel Cp (X-electrode waveform), the waveform of the voltage input to the power supply terminal VH (VH waveform), and the waveform of the voltage found at the third connection point (J3 waveform). Indicates.

The PDP driving circuit 1000 according to the control signal input to the gate terminals of the first to fifteenth transistor switches S1 to S15 and the control signals input to the input terminals of the first and second inverters I21 and I22. 2, an operation including a first reset period, a second reset period, a scan period, and a sustaining period is repeatedly performed.

In the first and second reset periods, the wall charge remaining even after the sustain period is reduced or eliminated. In the scan period, data-writing discharges are generated to select the cells to be turned on. In the sustain period, sustain discharge is generated and emitted in the cells selected in the scan period.

As shown in Fig. 2, in the initial state of the first reset period, the transistor switches S1, S2, S3, S7, S8, S9, S10, S12, S14, and S15 are turned off, while the transistor switches S4, S5, S6, S11 and S13 are turned on.

The sixteenth transistor switch S21 of the scan IC 114 is turned off, while the seventeenth transistor switch S22 is turned on.

Therefore, the voltage applied to the scan-electrode terminal of the plasma display panel Cp by the Y-electrode driving circuit 1100 is equal to the voltage of the ground terminal G1, and the plasma is applied by the X-electrode driving circuit 1200. The voltage applied to the common-electrode terminal of the display panel Cp is equal to the voltage of the ground terminal G2.

The waveform of the power supply terminal VH is higher by α than the Y-electrode waveform. The waveform of the third connection point J3 is higher by α than the Y-electrode waveform except for the scan period.

At the timing T1 of the first reset period, the first and tenth transistor switches S1 and S10 are turned on, while the fourth, eleventh and thirteenth transistor switches S4, S11 and S13 are turned off. .

Thus, in the Y-electrode driving circuit 1100, the current i1 is from the first capacitor C1 of the collection circuit 111 to the first transistor switch S1, the first diode D1, the first connection point ( J1, first coil L1, second connection point J2, fifth transistor switch S5, sixth transistor switch S6, third connection point J3, fourth connection point J4 (17th transistor) To the scan-electrode terminal of the plasma display panel Cp through the sequence of the switch S22 and the third connection point J3 electrically connected to each other, the eighth diode D11, and the fifth connection point J5. Flow.

In the X-electrode driving circuit 1200, a current i2 flows from the common-electrode terminal of the plasma display panel Cp to the power supply terminal VRST through the ninth connection point J9 and the tenth transistor switch S10. .

As a result, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 increases from the voltage of the ground terminal G1 to the voltage of the power supply terminal VS, and the X-electrode driving The voltage applied to the common electrode of the plasma display panel Cp by the circuit 1200 decreases from the voltage of the ground terminal G2 to the voltage of the power supply terminal VRST.

At the timing T2 of the first reset period, the first, fifth and sixth transistor switches S1, S5 and S6 are turned off while the third and seventh transistor switches S3 and S7 are turned on. .

As a result, in the Y-electrode driving circuit 1100, the current i3 is transferred from the power supply terminal VP of the reset circuit 113 to the seventh transistor switch S7, the third connection point J3, and the fourth connection point J4. ), The eighth diode D11 and the fifth connection point J5 flow to the scan-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 increases from the voltage of the power supply terminal VS to the voltage of the power supply terminal VP, and the X-electrode driving circuit The voltage applied to the common electrode of the plasma display panel Cp by 1200 is kept equal to the voltage of the power supply terminal VRST.

At the timing T3 of the first reset period, the second, fifth and sixth transistor switches S2, S5 and S6 are turned on, while the third and seventh transistor switches S3 and S7 are turned off. .

As a result, in the Y-electrode driving circuit 1100, the current i4 is transferred from the scan-electrode terminal of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, and the seventeenth transistor switch S22. ), Fourth connection point J4, third connection point J3, sixth transistor switch S6, fifth transistor switch S5, second connection point J2, first coil L1, first connection point ( It flows to the first capacitor C1 of the collection circuit 111 through the sequence of J1) and the second transistor switch S2.

Therefore, after the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 decreases sharply from the voltage of the power supply terminal VP to the voltage of the power supply terminal VS, the power supply terminal ( From the voltage of VS) it gradually decreases.

At the timing T4 of the first reset period, the eleventh and thirteenth transistor switches S11 and S13 are turned on, while the tenth transistor switch S10 is turned off.

As a result, in the X-electrode driving circuit 1200, the current i5 is transferred from the ground terminal G2 to the thirteenth transistor switch S13, the eighth connection point J8, the eleventh transistor switch S11, and the ninth connection point. It flows to the scan-electrode terminal of the plasma display panel Cp through the procedure of J9.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 gradually increases from the voltage of the power supply terminal VRST to the ground voltage.

At the timing T5 of the first reset period, the fourth transistor switch S4 is turned on while the second transistor switch S2 is turned off.

As a result, in the Y-electrode driving circuit 1100, the current i6 is transferred from the scan-electrode terminal of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, and the seventeenth transistor switch S22. ), Fourth connection point J4, third connection point J3, sixth transistor switch S6, fifth transistor switch S5, second connection point J2, fifth transistor switch S5, and fourth It flows to the ground terminal G1 through the sequence of the transistor switch S4.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 is steeply reduced to the voltage of the ground terminal G1.

The first reset period is defined as a period during which the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 increases to the voltage of the ground terminal G2.

At the timing T6 of the second reset period, the thirteenth transistor switch S13 is turned off while the fourteenth transistor switch S14 is turned on.

As a result, in the X-electrode driving circuit 1200, the current i7 is transferred from the second capacitor C2 to the fourteenth transistor switch S14, the seventh connection point J7, the second coil L2, and the eighth connection point. (J8), the eleventh transistor switch S11, and the ninth connection point J9 flow to the common-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 gradually increases from the voltage of the ground terminal G2.

At the timing T7 of the second reset period, the twelfth transistor switch S12 is turned on, while the fourteenth transistor switch S14 is turned off.

As a result, in the X-electrode driving circuit 1200, the current i8 is transferred from the power supply terminal VS to the twelfth transistor switch S12, the eighth connection point J8, the eleventh transistor switch S11, and the ninth transistor. It flows to the common electrode of the plasma display panel Cp through the order of the connection point J9.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 increases steeply up to the voltage of the power supply terminal VS.

At the timing T8 of the second reset period, the twelfth transistor switch S12 is turned off while the fifteenth transistor switch S15 is turned on.

As a result, in the X-electrode driving circuit 1200, the current i9 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eleventh transistor switch S11, and the eighth connection point J8. ), The second coil L2, the seventh connection point J7, the fourth diode D4, and the fifteenth transistor switch S15 flow to the second capacitor C2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 gradually decreases from the voltage of the power supply terminal VS.

At the timing T9 of the second reset period, the thirteenth transistor switch S13 is turned on, while the fifteenth transistor switch S15 is turned off.

As a result, in the X-electrode driving circuit 1200, the current i10 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eleventh transistor switch S11, and the eighth connection point J8. And the thirteenth transistor switch S13 to the ground terminal G2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 is steeply reduced to the voltage of the ground terminal G2.

At the timing T10 of the second reset period, the first transistor switch S1 is turned on while the fourth transistor switch S4 is turned off.

As a result, in the Y-electrode driving circuit 1100, the current i11 is transferred from the first capacitor C1 to the first transistor switch S1, the first diode D1, the first connection point J1, and the first coil. L1, second connection point J2, fifth transistor switch S5, sixth transistor switch S6, third connection point J3, fourth connection point J4, eighth diode D11, and eighth It flows to the scan-electrode terminal of the plasma display panel Cp through the sequence of the five connection points J5.

Thus, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 gradually increases.

At the timing T11 of the second reset period, the first transistor switch S1 is turned off while the third transistor switch S3 is turned on.

As a result, in the Y-electrode driving circuit 1100, the current i11 is transferred from the power supply terminal VS to the third transistor switch S3, the second connection point J2, the fifth transistor switch S5, and the sixth transistor. Flows to the scan-electrode terminal of the plasma display panel Cp through the sequence of the switch S6, the third connection point J3, the fourth connection point J4, the eighth diode D11, and the fifth connection point J5. .

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 sharply increases up to the voltage of the power supply terminal VS.

At the timing T12 of the second reset period, the second transistor switch S2 is turned on while the third transistor switch S3 is turned off.

As a result, in the Y-electrode driving circuit 1100, the current i4 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, 4th junction J4, 3rd junction J3, 6th transistor switch S6, 5th transistor switch S5, 2nd junction J2, 1st coil L1, 1st junction J1 And to the first capacitor C1 through the order of the second transistor switch S2.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 gradually decreases from the voltage of the power supply terminal VS.

At the timing T13 at which the scan period begins, the second and thirteenth transistor switches S2 and S13 are turned off while the fourth and ninth transistor switches S4 and S9 are turned on.

As a result, in the Y-electrode driving circuit 1100, the current i6 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, Ground through the sequence of the fourth connection point J4, the third connection point J3, the sixth transistor switch S6, the fifth transistor switch S5, the second connection point J2, and the fourth transistor switch S4. Flow to terminal G1.

Also, in the X-electrode driving circuit 1200, the current i12 is common to the plasma display panel Cp through the order of the ninth transistor switch S9 and the ninth connection point J9 from the power supply terminal VSW. -Flows into the electrode terminals.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 is steeply reduced to the voltage of the ground terminal G1, and the plasma display is performed by the X-electrode driving circuit 1200. The voltage applied to the common electrode of the panel Cp gradually increases to the voltage of the power supply terminal VSW.

At the timing T14 of the scan period, the fourth, fifth and sixth transistor switches S4, S5 and S6 are turned off while the eighth transistor switch S8 is turned on.

Further, at timing T14, the sixteenth transistor switch S21 is turned on, while the seventeenth transistor switch S22 is turned off.

As a result, in the Y-electrode driving circuit 1100, the current flows from the power supply terminal VH through the sequence of the sixteenth transistor switch S21, the sixth connection point J6, and the fifth connection point J5. Cp) flows to the scan electrode.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 gradually increases from the voltage of the ground terminal G1.

The voltage at the power supply terminal VH gradually increases from the sum of the ground voltage and α.

In addition, the voltage of the third connection point J3 gradually decreases from the sum of the ground voltage and α to the sum of the voltage of the power supply terminal VW and α.

In the selected line in the scan period, after the timing TS1 at which the sixteenth transistor switch S21 is turned off and the seventeenth transistor switch S22 is turned on, at timing TS2, the sixteenth transistor switch S21 is turned on. On, the seventeenth transistor switch S22 is turned off.

As a result, during the timing TS1 and the timing TS2 of the Y-electrode driving circuit 1100, the current i13 is connected to the fifth connection point J5 and the sixth connection point J6 from the scan electrode of the plasma display panel Cp. ), The seventeenth transistor switch S22, the fourth connection point J4, the third connection point J3, and the eighth transistor switch S8 flow to the power supply terminal VW.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 is steeply reduced to the voltage of the power supply terminal VW.

At the timing TS2, the current flows from the power supply terminal VH to the scan electrode of the plasma display panel Cp through the order of the sixteenth transistor switch S21, the sixth connection point J6, and the fifth connection point J5. Flow.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 increases steeply from the voltage of the power supply terminal VW.

The above-described selection (ie data-writing) is performed sequentially for each selected line.

At the timing T15 of the scan period, the ninth transistor switch S9 is turned off while the fifteenth transistor switch S15 is turned on.

As a result, in the X-electrode driving circuit 1200, the current i9 is transferred from the common electrode of the plasma display panel Cp to the ninth connection point J9, the eleventh transistor switch S11, the eighth connection point J8, It flows to the second capacitor C2 through the order of the second coil L2, the fourth diode D4, and the fifteenth transistor switch S15.

Thus, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 gradually decreases from the voltage of the power supply terminal VSW.

At the timing T16 of the scan period, the fourth, fifth and sixth transistor switches S4, S5 and S6 are turned on, while the eighth transistor switch S8 is turned off.

Further, at timing T16, the sixteenth transistor switch S21 is turned off while the seventeenth transistor switch S22 is turned on.

As a result, in the Y-electrode driving circuit 1100, the current i6 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, It flows to the ground terminal G1 through the order of the fourth connection point J4, the third connection point J3, the sixth transistor switch S6, the fifth transistor switch S5, and the fourth transistor switch S4.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 gradually decreases to the voltage of the ground terminal G1.

The voltage at the power supply terminal VH gradually decreases to the sum of the ground voltage and α, and the voltage at the third connection point J3 gradually increases to the sum of the ground voltage and α.

At the timing T17 at which the sustain period starts, the thirteenth transistor switch S13 is turned on, while the fifteenth transistor switch S15 is turned off.

As a result, in the X-electrode driving circuit 1200, the current i10 is transferred from the common electrode of the plasma display panel Cp to the ninth connection point J9, the eleventh transistor switch S11, the eighth connection point J8, And the thirteenth transistor switch S13 to the ground terminal G2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 is steeply reduced to the voltage of the ground terminal G2.

At the timing T18 of the sustain period, the first transistor switch S1 is turned on while the fourth transistor switch S4 is turned off.

As a result, in the Y-electrode driving circuit 1100, the current i1 is transferred from the first capacitor C1 to the first transistor switch S1, the first diode D1, the first connection point J1, and the first coil. L1, second connection point J2, fifth transistor switch S5, sixth transistor switch S6, third connection point J3, fourth connection point J4, eighth diode D11, and eighth It flows to the scan electrode of plasma display panel Cp through the order of 5 connection point J5.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 gradually increases from the voltage of the ground terminal G1.

At the timing T20 of the sustain period, the first transistor switch S1 is turned off while the third transistor switch S3 is turned on.

As a result, in the Y-electrode driving circuit 1100, the current i11 is transferred from the power supply terminal VS to the third transistor switch S3, the second connection point J2, the fifth transistor switch S5, and the sixth transistor. Flows to the scan-electrode terminal of the plasma display panel Cp through the sequence of the switch S6, the third connection point J3, the fourth connection point J4, the eighth diode D11, and the fifth connection point J5. .

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 sharply increases up to the voltage of the power supply terminal VS.

At the timing T21 of the sustain period, the second transistor switch S2 is turned on while the third transistor switch S3 is turned off.

As a result, in the Y-electrode driving circuit 1100, the current i4 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the fifth transistor switch S5, 17th transistor switch S22, 4th junction J4, 3rd junction J3, 6th transistor switch S6, 2nd junction J2, 1st coil L1, 1st junction J1 And to the first capacitor C1 through the order of the second transistor switch S2.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 gradually decreases from the voltage of the power supply terminal VS.

At the timing T22 of the sustain period, the second transistor switch S2 is turned off while the fourth transistor switch S4 is turned on.

As a result, in the Y-electrode driving circuit 1100, the current i6 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, Ground through the sequence of the fourth connection point J4, the third connection point J3, the sixth transistor switch S6, the fifth transistor switch S5, the second connection point J2, and the fourth transistor switch S4. Flow to terminal G1.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 1100 is steeply reduced to the voltage of the ground terminal G1.

At the timing T23 of the sustain period, the thirteenth transistor switch S13 is turned off, while the fourteenth transistor switch S14 is turned on.

As a result, in the X-electrode driving circuit 1200, the current i7 is transferred from the second capacitor C2 to the fourteenth transistor switch S14, the seventh connection point J7, the second coil L2, and the eighth connection point. (J8), the eleventh transistor switch S11, and the ninth connection point J9 flow to the common-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 gradually increases from the voltage of the ground terminal G2.

At the timing T24 of the sustain period, the twelfth transistor switch S12 is turned on, while the fourteenth transistor switch S14 is turned off.

As a result, in the X-electrode driving circuit 1200, the current i8 is transferred from the power supply terminal VS to the twelfth transistor switch S12, the eighth connection point J8, the eleventh transistor switch S11, and the ninth transistor. It flows to the common-electrode terminal of the plasma display panel Cp through the order of the connection point J9.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 increases steeply up to the voltage of the power supply terminal VS.

At the timing T25 of the sustain period, the twelfth transistor switch S12 is turned off while the fourteenth transistor switch S14 is turned on.

As a result, in the X-electrode driving circuit 1200, the current i9 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eleventh transistor switch S11, and the eighth connection point J8. ), The second coil L2, the seventh connection point J7, the fourth diode D4, and the fifteenth transistor switch S15 flow to the second capacitor C2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 gradually decreases from the voltage of the power supply terminal VS.

At the timing T26 of the sustain period, the thirteenth transistor switch S13 is turned on, while the fifteenth transistor switch S15 is turned off.

As a result, in the X-electrode driving circuit 1200, the current i10 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eleventh transistor switch S11, and the eighth connection point J8. And the thirteenth transistor switch S13 to the ground terminal G2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 1200 is steeply reduced to the voltage of the ground terminal G2.

Thereafter, after the operation performed at the timings T18 to T26 is repeatedly performed by the number of the sustaining-discharge pulses, the operation of the first reset period is restarted.

Among the components of the PDP driving circuit 1000, the sixth transistor switch S6 prevents current from flowing from the power supply terminal VP having a voltage higher than the voltage of the power supply terminal VS to the power supply terminal VS. It acts as a cut switch.

Similarly, the fifth transistor switch S5 functions as a cut switch for preventing current from flowing from the ground terminal G1 to the power supply terminal VW having a negative potential.

Similarly, the eleventh transistor switch S11 functions as a cut switch for preventing current from flowing from the ground terminal G2 to the power supply terminal VRST having a negative potential.

3 is a circuit diagram of the plasma display panel drive circuit 2000 disclosed in Japanese Laid-Open Patent Publication No. 2003-76323.

As shown in FIG. 3, the circuit 2000 includes a Y-electrode driving circuit 2100 and an X-electrode driving circuit 2200.

Y-electrode drive circuit 2100 includes a voltage-collecting circuit 10, a reset-pulse transmit circuit 20, a scan-buffer IC 30, and a scan-pulse transmit circuit 40. do.

The reset-pulse transmission circuit 20 includes a power supply Vset that provides a high voltage for applying the reset pulse to the scan electrode of the plasma display panel Cp, and a current from the power supply Vset is applied to the voltage-collection circuit 10. Diodes (Ds) which prevent them from entering.

Current from the power supply Vset flows through the scan-buffer IC 30 to the scan-pulse transmission circuit 40. Thus, the scan-pulse transmission circuit 40 includes a transistor switch Ysp that prevents current from flowing into the voltage-collection circuit 10.

Since the plasma display panel Cp is a capacitive load, the voltage driving the plasma display panel Cp is relatively high (specifically, in the range of several tens to several hundred volts).

Therefore, when the current caused when the driving voltage is applied to the plasma display panel Cp flows through the components of the plasma display panel Cp driving circuit, a lot of power loss is caused.

In particular, since the sustain-discharge pulse is applied to the drive circuit for a long time, it is necessary to reduce the power loss caused when the sustain-discharge pulse is applied to the drive circuit.

In the conventional circuit 1000 shown in Fig. 1, the sustain-discharge pulses for emitting the plasma display panel Cp are generated by the first to fourth transistor switches S1 to S4 of the Y-electrode driving circuit 1100. And a switching operation performed by the twelfth to fifteenth transistor switches S12 to S15 of the X-electrode driving circuit 1200.

Due to the switching operation performed by the first to fourth transistor switches S1 to S4 and the twelfth to fifteenth transistor switches S12 to S15, the currents i1, i4, i11, i6, i8, i10, i7 and i9 flows through each of the transistor switches S1 to S4 and S12 to S15.

Thus, when the sustain-discharge pulse is applied to the conventional circuit 1000 shown in Fig. 1, the currents i1, i4, i11 and i6 are fifth and sixth transistor switches S5 and S6 functioning as cut switches. Flows through, and currents i8, i10, i7 and i9 flow through the eleventh transistor switch S11 which functions as a cut switch, causing a lot of power loss.

Similarly, the conventional circuit 2000 shown in FIG. 3 entails the problem that when a sustain-discharge pulse is applied to the circuit 2000, power loss occurs in both the diode Ds and the transistor switch Ysp. .

An object of the present invention is to solve the above-mentioned problems in the prior art. That is, it is necessary to reduce a lot of power loss which occurs when the current caused when the driving voltage is applied to the plasma display panel Cp flows through the components of the plasma display panel Cp driving circuit, and in particular, the maintenance- Since the discharge pulse is applied to the drive circuit for a long time, it is necessary to reduce the power loss caused when the sustain-discharge pulse is applied to the drive circuit.

In one aspect of the present invention, a plasma display panel driving circuit including a scan-electrode driving circuit for applying a driving voltage to a scan electrode of a plasma display panel, wherein the scan-electrode driving circuit applies a sustain-discharge pulse to the scan electrode. A first sustaining-clamp circuit and a reset circuit for applying a reset pulse to the scan electrode, wherein the first sustain-clamp circuit comprises a first power supply terminal having a voltage higher than the ground voltage, and electrically connecting the first power supply terminal to the scan electrode; A first switching element capable of being connected to the gate, a first ground terminal having a ground voltage, and a second switching element capable of electrically connecting the first ground terminal to the scan electrode, wherein the reset circuit is lower than the ground voltage. A second power supply terminal having a voltage, and a third switch capable of electrically connecting the second power supply terminal to the scan electrode; A switching element, wherein the first holding-clamp circuit comprises a first current cut-off element for preventing current from flowing from the first ground terminal to the second power supply terminal; A plasma display panel driving circuit is provided, which is located in the first holding-clamp circuit of a current path other than the current path through which current flows when a voltage is applied to the scan electrode through the one power supply terminal.

In the circuit according to the invention, since the first current cut-off element is located in the first holding-clamp of the current path other than the current path through which the current flows when a voltage is applied to the scan electrode through the first power supply terminal, It is possible to reduce the power loss caused by the current flowing through the one current cut-off element.

For example, the first current cut-off element may consist of a switching element or a diode.

In a preferred embodiment, the scan-electrode drive circuit further comprises a first collection circuit for applying a voltage to the scan electrode and collecting the voltage from the scan electrode, wherein the first current cut-off element comprises: a first collection When the circuit applies a voltage to the scan electrode, or when the first collection circuit recovers the voltage from the scan electrode, it is located in the first hold-clamp of the current path other than the current path through which the current flows.

This embodiment makes it possible to further reduce the power loss caused by the current flowing through the first current cut-off element.

In a preferred embodiment, the reset circuit comprises a third power supply terminal having a voltage higher than the voltage of the first power supply terminal, and a fourth switching element capable of electrically connecting the third power supply terminal to the scan electrode, the first The holding-clamp circuit includes a second current cut-off element that prevents current from flowing from the third power terminal to the first power terminal, wherein the second current cut-off element is electrically connected to the first power terminal. Is placed in the first holding-clamp circuit of the current path other than the current path through which the current flows.

This embodiment makes it possible to reduce the power loss caused by the current flowing through the second current cut-off element.

In a preferred embodiment, the reset circuit comprises a third power supply terminal having a voltage higher than the voltage of the first power supply terminal, and a fourth switching element capable of electrically connecting the third power supply terminal to the scan electrode, the first The holding-clamp circuit includes a second current cut-off element that prevents current from flowing from the third power supply terminal to the first power supply terminal, wherein the second current cut-off element includes a first collection circuit having a voltage applied to the scan electrode. Is applied, the first collection circuit recovers voltage from the scan electrode, or when the scan electrode is electrically connected to the first power supply terminal, the first holding-clamp of the current path other than the current path through which the current flows. It is located in the circuit.

This embodiment makes it possible to further reduce the power loss caused by the current flowing through the first current cut-off element, and furthermore, the power caused by the current flowing through the second current cut-off element. Makes it possible to reduce the losses.

For example, the second current cut-off element may consist of a switching element or a diode.

Also, a plasma display panel driving circuit including a scan-electrode driving circuit for applying a driving voltage to a scan electrode of the plasma display panel, wherein the scan-electrode driving circuit includes a first sustain-clamp for applying a sustain-discharge pulse to the scan electrode. A circuit, and a reset circuit for applying a reset pulse to the scan electrode, wherein the first sustain-clamp circuit includes a first power supply terminal, a first switching element capable of electrically connecting the first power supply terminal to the scan electrode, and a ground; A first ground terminal having a voltage, wherein the reset circuit comprises: a third power supply terminal having a voltage higher than that of the first power supply terminal; and a fourth switching element capable of electrically connecting the third power supply terminal to the scan electrode. Wherein the first retaining-clamp circuit includes a second current cut-off to prevent current from flowing from the third power supply terminal to the first power supply terminal; And a second current cut-off element, wherein the second current cut-off element is located in the first holding-clamp circuit of a current path other than the current path through which the current flows when the scan electrode is electrically connected to the first ground terminal. A drive circuit is provided.

In the circuit according to the invention, since the second current cut-off element is located in the first holding-clamp circuit of the current path other than the current path through which the current flows when the scan electrode is electrically connected to the first ground terminal. It is possible to reduce the power loss caused by the current flowing through the second current cut-off element.

In a preferred embodiment, the scan-electrode drive circuit further comprises a first collection circuit for applying a voltage to the scan electrode and recovering the voltage from the scan electrode, wherein the second current cut-off element is configured to include a first collection circuit. When a voltage is applied to the scan electrode, or when the first collection circuit recovers the voltage from the scan electrode, it is located in the first holding-clamp circuit of the current path other than the current path through which the current flows.

This embodiment ensures that it is possible to further reduce the power loss caused by the current flowing through the second current cut-off element.

Also, a plasma display panel driving circuit including a common-electrode driving circuit for applying a driving voltage to a common electrode of the plasma display panel, wherein the common-electrode driving circuit includes a second sustain-clamp for applying a sustain-discharge pulse to the common electrode. A circuit and a reset enhancement circuit for applying a pulse to the common electrode to improve reset performance of the common electrode, wherein the second sustain-clamp circuit comprises a fourth power supply terminal having a voltage higher than the ground voltage, a fourth power supply; A fifth switching element that can electrically connect the terminal to the common electrode, a second ground terminal having the ground voltage, and a sixth switching element that can electrically connect the second ground terminal to the common electrode; The enhancement circuit includes a fifth power supply terminal having a lower voltage than the ground voltage, and the fifth power supply terminal to the common electrode. A seventh switching element that can be connected miraculously, and the second holding-clamp circuit includes a third current cut-off element that prevents current from flowing from the second ground terminal to the fifth power supply terminal; The current cut-off element is provided with a plasma display panel drive circuit, which is located in a second holding-clamp circuit in a current path other than the current path through which current flows when a voltage is applied to the common electrode through the fourth power supply terminal.

In the circuit according to the invention, since the third current cut-off element is located in the second holding-clamp circuit of the current path other than the current path through which the current flows when voltage is applied to the common electrode via the fourth power supply terminal. It is possible to reduce the power loss caused by the current flowing through the third current cut-off element.

Also, a plasma display panel driving circuit including a common-electrode driving circuit for applying a driving voltage to a common electrode of the plasma display panel, wherein the common-electrode driving circuit includes a second sustain-clamp for applying a sustain-discharge pulse to the common electrode. A circuit, and a sub-voltage application circuit for applying a sub-scan-voltage to the common electrode, wherein the second sustain-clamp circuit includes a fourth power supply terminal having a voltage higher than the ground voltage, and a fourth power supply terminal to the common electrode. A fifth switching element electrically connectable to the second ground terminal, a second ground terminal having a ground voltage, and a sixth switching element electrically connecting the second ground terminal to the common electrode, wherein the sub-voltage application circuit is provided. A fifth power supply terminal having a voltage higher than that of the fourth power supply terminal, and when the fifth power supply terminal is electrically connected to the common electrode. A sixth switching element, wherein the second holding-clamp circuit includes a third current cut-off element that prevents current from flowing from the fifth power terminal to the fourth power terminal; The device is provided with a plasma display panel driving circuit, which is located in the second holding-clamp circuit in a current path other than the current path through which the current flows when the common electrode is electrically connected to the second ground terminal.

In the circuit according to the invention, since the third current cut-off element is located in the second holding-clamp circuit of the current path other than the current path through which the current flows when the common electrode is electrically connected to the second ground terminal, It is possible to reduce the power loss caused by the current flowing through the third current cut-off element.

In a preferred embodiment, the common-electrode drive circuit further comprises a second recovery circuit for applying a voltage to the common electrode and recovering the voltage from the common electrode, wherein the third current cut-off element is configured to include a second collection circuit. When a voltage is applied to the common electrode, or when the second collection circuit recovers the voltage from the common electrode, it is located in the first holding-clamp circuit of the current path other than the current path through which the current flows.

This embodiment ensures that it is possible to further reduce the power loss caused by the current flowing through the third current cut-off element.

For example, the third current cut-off element may consist of a switching element or a diode.

The plasma display panel driving circuit may be formed of one of the scan-electrode driving circuits described above and one of the common-electrode driving circuits described above.

Description of the Preferred Embodiments

[First embodiment]

4 is a circuit diagram of the plasma display panel (Cp) driving circuit 100 according to the first embodiment of the present invention.

As shown in FIG. 4, the circuit 100 according to the first embodiment drives a voltage to a terminal (hereinafter referred to as a "scan electrode terminal") of the Y-electrode (scan electrode) of the plasma display panel Cp. X-electrode driving circuit 110 for applying a driving voltage to the terminal of the X electrode (common electrode) of plasma display panel Cp (hereinafter referred to as "common-electrode terminal") for applying the Circuit 120.

The Y-electrode drive circuit 110 includes a collection circuit 111, a sustain-clamp circuit 112, a reset circuit (priming circuit) 113, a scan IC 114, and a collection circuit 111 and a sustain-clamp circuit. It consists of a 1st coil L1 electrically connected between 112.

The collection circuit 111 consists of a first capacitor C1, a first transistor switch S1, a second transistor switch S2, a first diode D1, and a second diode D2.

One end of the first capacitor C1 is grounded and the other end is electrically connected to both the drain terminal of the first transistor switch S1 and the source terminal of the second transistor switch S2.

The first and second diodes D1 and D2 are electrically connected in series with each other between the source terminal of the first transistor switch S1 and the drain terminal of the second transistor switch S2.

Specifically, the source terminal of the first transistor switch S1 is electrically connected to the anode terminal of the first diode D1, and the cathode terminal of the first diode D1 is electrically connected to the anode terminal of the second diode D2. Is connected, and the cathode terminal of the second diode D2 is electrically connected to the drain terminal of the second transistor switch S2.

The sustain-clamp circuit 112 includes third to sixth transistor switches S3 to S6.

The third transistor switch S3 has a drain terminal electrically connected to the power supply terminal VS, and a source terminal electrically connected to the drain terminal of the fifth transistor switch S5.

The fourth transistor switch S4 has a source terminal electrically connected to the ground terminal G1, and a drain terminal electrically connected to the drain terminal of the fifth transistor switch S5.

The sixth transistor switch S6 has a source terminal electrically connected to the second connection point J2 to which the third and fifth transistor switches S3 and S5 are electrically connected to each other.

One end of the first coil L1 is electrically connected to the second connection point J2 and the other end is electrically connected to the first connection point J1 to which the first and second diodes D1 and D2 are electrically connected to each other.

The reset circuit 113 is composed of a seventh transistor switch S7 and an eighth transistor switch S8.

The seventh transistor switch S7 has a drain terminal electrically connected to the power supply terminal VP, and a source terminal electrically connected to the drain terminal of the eighth transistor switch S8.

The eighth transistor switch S8 has a source terminal electrically connected to the power supply terminal VW.

The sixth transistor switch S6 has a drain terminal in which the source terminal of the seventh transistor switch S7 and the drain terminal of the eighth transistor switch S8 are electrically connected to the third connection point J3 electrically connected to each other. Has

The scan IC 114 includes a sixteenth transistor switch S21, a seventeenth transistor switch S22, a seventh diode D10, an eighth diode D11, a first inverter I21, and a second inverter I22. Is made of.

The sixteenth transistor switch S21 is electrically connected to a drain terminal electrically connected to both the power supply terminal VH and the cathode terminal of the seventh diode D10, and to the drain terminal of the seventeenth transistor switch S22. Has a source terminal.

The seventeenth transistor switch S22 has a source terminal electrically connected to the above-mentioned third connection point J3 and the anode terminal of the eighth diode D11.

The eighth diode D11 is a sixth connection point at which the anode terminal of the seventh diode D10 and the source terminal of the sixteenth transistor switch S21 and the drain terminal of the seventeenth transistor switch S22 are electrically connected to each other. J6) has a cathode terminal electrically connected to both.

The first inverter I21 has an output terminal electrically connected to both the input terminal of the sixteenth transistor switch S21 and the second inverter I22.

The second inverter I22 has an output terminal electrically connected to both the gate terminal of the seventeenth transistor switch S22 and the input terminal of the first inverter I21.

The fifth connection point J5 in which the fifth and sixth diodes D10 and D11 are electrically connected to each other is electrically connected to the scan-electrode terminal of the plasma display panel Cp.

The X-electrode drive circuit 120 is composed of a collection circuit 121, a sustain-clamp circuit 122, a sub-voltage application circuit 123, a resetability enhancement circuit 124, and a second coil L2.

The sub-voltage application circuit 123 includes a ninth transistor switch S9 having a drain terminal electrically connected to the power supply terminal VSW.

The reset improvement circuit 124 includes a tenth transistor switch S10 having a source terminal electrically connected to a power supply terminal VRST, and a drain terminal electrically connected to a source terminal of the ninth transistor switch S9. Include.

The ninth connection point J9 in which the source terminal of the ninth transistor switch S9 and the drain terminal of the tenth transistor switch S10 are electrically connected to each other is electrically connected to the common-electrode terminal of the plasma display panel Cp. .

The sustain-clamp circuit 122 includes eleventh through thirteenth transistor switches S11 through S13.

The thirteenth transistor switch S13 has a source terminal electrically connected to the ground terminal G2, and a drain terminal electrically connected to the drain terminal of the eleventh transistor switch S11.

The eleventh transistor switch S11 has a source terminal electrically connected to the source terminal of the twelfth transistor switch S12.

The eighth connection point J8 in which the source terminal of the twelfth transistor switch S12 and the source terminal of the tenth transistor switch S10 are electrically connected to each other is common to the plasma display panel Cp through the ninth connection point J9. It is electrically connected to an electrode terminal.

The twelfth transistor switch S12 has a drain terminal electrically connected to the power supply terminal VS.

The collection circuit 121 includes a fourteenth transistor switch S14, a fifteenth transistor switch S15, a third diode D3, a fourth diode D4, and a second capacitor C2.

One end of the second capacitor C2 is grounded and the other end is electrically connected to both the drain terminal of the fourteenth transistor switch S14 and the source terminal of the fifteenth transistor switch S15.

The third and fourth diodes D3 and D4 are electrically connected in series with each other between the source terminal of the fourteenth transistor switch S14 and the drain terminal of the fifteenth transistor switch S15.

Specifically, the source terminal of the fourteenth transistor switch S14 is electrically connected to the anode terminal of the third diode D3, and the cathode terminal of the third diode D3 is electrically connected to the anode terminal of the fourth diode D4. Is connected, and the cathode terminal of the fourth diode D4 is electrically connected to the drain terminal of the fifteenth transistor switch S15.

One end of the second coil L2 is connected to the seventh connection point J7 through which the third and fourth diodes D3 and D4 are electrically connected to each other, and the other end thereof is through the eighth and ninth connection points J8 and J9. It is electrically connected to the common-electrode terminal of the plasma display panel Cp.

In the first embodiment, the voltage applied to the power supply terminal VP is higher than the voltage applied to the power supply terminal VS.

The voltage applied to the power supply terminal VSW is higher than the voltage applied to the power supply terminal VS.

The voltage applied to the power supply terminals VS, VP and VSW is higher than the voltages of the first and second ground terminals G1 and G2.

On the other hand, the voltage applied to the power supply terminals VW and VRST is lower than the voltages of the first and second ground terminals G1 and G2.

The voltage applied to the power supply terminal VH is higher by α than the voltage applied to the scan-electrode terminal of the plasma display panel Cp except for the scan period (see FIG. 2).

The control signal is input to each of the gate terminals of the first to fifteenth transistor switches S1 to S15 and to each of the input terminals of the first and second inverters I21 and I22 of the scan IC 114. On / off control is performed for the first to seventeenth transistor switches S1 to S15, S21 and S22 according to the control signal.

2 is a timing chart showing the operation of the circuit 100 according to the first embodiment.

2 shows waveforms of control signals input to the gate terminals of the first to fifteenth transistor switches S1 to S15, waveforms of voltages applied to the scan electrodes of the plasma display panel Cp (Y-electrode waveforms), and plasma displays. The waveform of the voltage applied to the common electrode of the panel Cp (X-electrode waveform), the waveform of the voltage input to the power supply terminal VH (VH waveform), and the waveform of the voltage found at the third connection point J3 ( J3 waveform).

The PDP driving circuit 100 according to the control signal input to the gate terminals of the first to fifteenth transistor switches S1 to S15 and the control signals input to the input terminals of the first and second inverters I21 and I22. 2, an operation including a first reset period, a second reset period, a scan period, and a sustain period is repeatedly performed.

In the first and second reset periods, the wall charge remaining even after the sustain period is reduced or eliminated. In the scan period, data-writing discharges are generated to select the cells to be turned on. In the sustain period, sustain discharge is generated in the selected cell in the scan period and emits light.

As shown in Fig. 2, in the initial state of the first reset period, the transistor switches S1, S2, S3, S7, S8, S9, S10, S12, S14 and S15 are turned off, whereas the transistor switches S4, S5, S6, S11 and S13 are turned on.

The sixteenth transistor switch S21 of the scan IC 114 is turned off, while the seventeenth transistor switch S22 is turned on.

Therefore, the voltage applied to the scan-electrode terminal of the plasma display panel Cp by the Y-electrode driving circuit 110 is equal to the voltage of the ground terminal G1, and the plasma is applied by the X-electrode driving circuit 120 to the plasma. The voltage applied to the common-electrode terminal of the display panel Cp is equal to the voltage of the ground terminal G2.

The waveform of the power supply terminal VH is higher by α than the Y-electrode waveform. The waveform at the third junction J3 is higher than the Y-electrode waveform except for the scan period.

At the timing T1 of the first reset period, the first and tenth transistor switches S1 and S10 are turned on, while the fourth, eleventh and thirteenth transistor switches S4, S11 and S13 are turned off. .

Thus, in the Y-electrode driving circuit 110, the current i1 is transferred from the first capacitor C1 of the collection circuit 111 to the first transistor switch S1, the first diode D1, and the first connection point J1. ), The first coil L1, the second connection point J2, the sixth transistor switch S6, the third connection point J3, the fourth connection point J4 (the seventeenth transistor switch S22 and the third connection point ( J3) flows to the scan-electrode terminal of the plasma display panel Cp through the order of the connection points electrically connected to each other), the eighth diode D11, and the fifth connection point J5.

In the X-electrode driving circuit 120, the current i2 is supplied to the power supply terminal VRST through the order of the ninth connection point J9 and the tenth transistor switch S10 from the common-electrode terminal of the plasma display panel Cp. Flows into.

As a result, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 increases from the voltage of the ground terminal G1 to the voltage of the power supply terminal VS, and the X-electrode driving The voltage applied to the common electrode of the plasma display panel Cp by the circuit 120 decreases from the voltage of the ground terminal G2 to the voltage of the power supply terminal VRST.

At the timing T2 of the first reset period, the first, fifth and sixth transistor switches S1, S5 and S6 are turned off while the third and seventh transistor switches S3 and S7 are turned on. .

As a result, in the Y-electrode driving circuit 110, the current i3 is transferred from the power supply terminal VP of the reset circuit 113 to the seventh transistor switch S7, the third connection point J3, and the fourth connection point J4. ), The eighth diode D11 and the fifth connection point J5 flow to the scan-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 increases from the voltage of the power supply terminal VS to the voltage of the power supply terminal VP, and the X-electrode driving circuit The voltage applied to the common electrode of the plasma display panel Cp by 120 is kept equal to the voltage of the power supply terminal VRST.

At the timing T3 of the first reset period, the second, fifth and sixth transistor switches S2, S5 and S6 are turned on, while the third and seventh transistor switches S3 and S7 are turned off. .

As a result, in the Y-electrode driving circuit 110, the current i4 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, 4th junction J4, 3rd junction J3, 6th transistor switch S6, 2nd junction J2, 1st coil L1, 1st junction J1, and 2nd transistor switch It flows to the 1st capacitor C1 of the collection circuit 111 through the order of S2.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 decreases steeply from the voltage of the power supply terminal VP to the voltage of the power supply terminal VS, and then the power supply terminal VS. Gradually decreases from the voltage of.

At the timing T4 of the first reset period, the eleventh and thirteenth transistor switches S11 and S13 are turned on, while the tenth transistor switch S10 is turned off.

As a result, in the X-electrode driving circuit 120, the current i5 is transferred from the ground terminal G2 to the thirteenth transistor switch S13, the eleventh transistor switch S11, the eighth connection point J8, and the ninth transistor. It flows to the scan-electrode terminal of the plasma display panel Cp through the order of the connection point J9.

Thus, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 gradually increases from the voltage of the power supply terminal VRST to the ground voltage.

At the timing T5 of the first reset period, the fourth transistor switch S4 is turned on while the second transistor switch S2 is turned off.

As a result, in the Y-electrode driving circuit 110, the current i6 is transferred from the scan-electrode terminal of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, and the seventeenth transistor switch S22. ), The fourth connection point J4, the third connection point J3, the sixth transistor switch S6, the second connection point J2, the fifth transistor switch S5, and the fourth transistor switch S4. It flows to the ground terminal G1 through the sequence.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 is steeply reduced to the voltage of the ground terminal G1.

The first reset period is defined as a period during which the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 increases to the voltage of the ground terminal G2.

At the timing T6 of the second reset period, the thirteenth transistor switch S13 is turned off while the fourteenth transistor switch S14 is turned on.

As a result, in the X-electrode driving circuit 120, the current i7 is transferred from the second capacitor C2 to the fourteenth transistor switch S14, the seventh connection point J7, the second coil L2, and the eighth connection point. J8 and the ninth connection point J9 flow to the common-electrode terminal of the plasma display panel Cp.

Thus, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 gradually increases from the voltage of the ground terminal G2.

At the timing T7 of the second reset period, the twelfth transistor switch S12 is turned on, while the fourteenth transistor switch S14 is turned off.

As a result, in the X-electrode driving circuit 120, the current i8 is transferred from the power supply terminal VS through the order of the twelfth transistor switch S12, the eighth connection point J8, and the ninth connection point J9. It flows to the common-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 increases steeply up to the voltage of the power supply terminal VS.

At the timing T8 of the second reset period, the twelfth transistor switch S12 is turned off while the fifteenth transistor switch S15 is turned on.

As a result, in the X-electrode driving circuit 120, the current i9 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eighth connection point J8, and the second coil L2. , The seventh connection point J7, the fourth diode D4, and the fifteenth transistor switch S15 flow to the second capacitor C2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 gradually decreases from the voltage of the power supply terminal VS.

At the timing T9 of the second reset period, the thirteenth transistor switch S13 is turned on, while the fifteenth transistor switch S15 is turned off.

As a result, in the X-electrode driving circuit 120, the current i10 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eighth connection point J8, and the eleventh transistor switch S11. And the thirteenth transistor switch S13 to the ground terminal G2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 is steeply reduced to the voltage of the ground terminal G2.

At the timing T10 of the second reset period, the first transistor switch S1 is turned on while the fourth transistor switch S4 is turned off.

As a result, in the Y-electrode driving circuit 110, the current i11 is transferred from the first capacitor C1 to the first transistor switch S1, the first diode D1, the first connection point J1, and the first coil. L1, second connection point J2, sixth transistor switch S6, third connection point J3, fourth connection point J4, eighth diode D11, and fifth connection point J5 Flows through the scan-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 gradually increases.

At the timing T11 of the second reset period, the first transistor switch S1 is turned off while the third transistor switch S3 is turned on.

As a result, in the Y-electrode driving circuit 110, the current i11 is transferred from the power supply terminal VS to the third transistor switch S3, the second connection point J2, the sixth transistor switch S6, and the third connection point. And the fourth connection point J4, the eighth diode D11, and the fifth connection point J5 flow to the scan-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 increases steeply up to the voltage of the power supply terminal VS.

At the timing T12 of the second reset period, the second transistor switch S2 is turned on while the third transistor switch S3 is turned off.

As a result, in the Y-electrode driving circuit 110, the current i4 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, Fourth junction J4, third junction J3, sixth transistor switch S6, second junction J2, first coil L1, first junction J1, and second transistor switch ( Flows to the first capacitor C1 through the sequence of S2).

Thus, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 gradually decreases from the voltage of the power supply terminal VS.

At the timing T13 at which the scan period begins, the second and thirteenth transistor switches S2 and S13 are turned off while the fourth and ninth transistor switches S4 and S9 are turned on.

As a result, in the Y-electrode driving circuit 110, the current i6 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, Ground through the order of the fourth connection point J4, the third connection point J3, the sixth transistor switch S6, the second connection point J2, the fifth transistor switch S5, and the fourth transistor switch S4. Flow to terminal G1.

Further, in the X-electrode driving circuit 120, the current i12 is common to the plasma display panel Cp through the order of the ninth transistor switch S9 and the ninth connection point J9 from the power supply terminal VSW. Flow to the electrode terminal.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 is steeply reduced to the voltage of the ground terminal G1, and the plasma display is performed by the X-electrode driving circuit 120. The voltage applied to the common electrode of the panel Cp gradually increases to the voltage of the power supply terminal VSW.

At the timing T14 of the scan period, the fourth, fifth and sixth transistor switches S4, S5 and S6 are turned off while the eighth transistor switch S8 is turned on.

Further, at timing T14, the sixteenth transistor switch S21 is turned on, while the seventeenth transistor switch S22 is turned off.

As a result, in the Y-electrode driving circuit 110, the current is transferred from the power supply terminal VH through the sequence of the sixteenth transistor switch S21, the sixth connection point J6, and the fifth connection point J5. It flows to the scan electrode of (Cp).

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 gradually increases from the voltage of the ground terminal G1.

The voltage at the power supply terminal VH gradually increases from the sum of the ground voltage and α.

In addition, the voltage at the third connection point J3 gradually decreases from the sum of the ground voltage and α to the sum of the voltage of the power supply terminal VW and α.

At the selected line in the scan period, after the timing TS1 at which the sixteenth transistor switch S21 is turned off and the seventeenth transistor switch S22 is turned on, at timing TS2, the sixteenth transistor switch S21 is turned on. On, the seventeenth transistor switch S22 is turned off.

As a result, during the timing TS1 and the timing TS2 of the Y-electrode driving circuit 110, the current i13 is driven from the scan electrode of the plasma display panel Cp by the fifth connection point J5 and the sixth connection point J6. ), The seventeenth transistor switch S22, the fourth connection point J4, the third connection point J3, and the eighth transistor switch S8 flow to the power supply terminal VW.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 is steeply reduced to the voltage of the power supply terminal VW.

At the timing TS2, the current flows from the power supply terminal VH to the scan electrode of the plasma display panel Cp through the sequence of the sixteenth transistor switch S21, the sixth connection point J6, and the fifth connection point J5. Flow.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 increases steeply from the voltage of the power supply terminal VW.

The above-described selection (ie data-writing) is performed sequentially for each selected line.

At the timing T15 of the scan period, the ninth transistor switch S9 is turned off while the fifteenth transistor switch S15 is turned on.

As a result, in the X-electrode driving circuit 120, the current i9 is transferred from the common electrode of the plasma display panel Cp to the ninth connection point J9, the eighth connection point J8, the second coil L2, and the first electrode. Four diodes D4 and a fifteenth transistor switch S15 flow to the second capacitor C2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 gradually decreases from the voltage of the power supply terminal VSW.

At the timing T16 of the scan computation, the fourth, fifth and sixth transistor switches S4, S5 and S6 are turned on, while the eighth transistor switch S8 is turned off.

Further, at timing T16, the sixteenth transistor switch S21 is turned off while the seventeenth transistor switch S22 is turned on.

As a result, in the Y-electrode driving circuit 110, the current i6 is transferred from the scan-electrode terminal of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, and the seventeenth transistor switch S22. ), The fourth connection point J4, the third connection point J3, the sixth transistor switch S6, the second connection point J2, and the fifth transistor switch S5 flow to the ground terminal G1. .

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 gradually decreases to the voltage of the ground terminal G1.

The voltage at the power supply terminal VH gradually decreases to the sum of the ground voltage and α, and the voltage at the third connection point J3 gradually increases to the sum of the ground voltage and α.

At the timing T17 at which the sustain period starts, the thirteenth transistor switch S13 is turned on, while the fifteenth transistor switch S15 is turned off.

As a result, in the X-electrode driving circuit 120, the current i10 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eighth connection point J8, and the eleventh transistor switch S11. ) And the thirteenth transistor switch S13 to the ground terminal G2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 is steeply reduced to the voltage of the ground terminal G2.

At the timing T18 of the sustain period, the first transistor switch S1 is turned on while the fourth transistor switch S4 is turned off.

As a result, in the Y-electrode driving circuit 110, the current i1 is transferred from the first capacitor C1 to the first transistor switch S1, the first diode D1, the first connection point J1, and the first coil. L1, second connection point J2, sixth transistor switch S6, third connection point J3, fourth connection point J4, eighth diode D11, and fifth connection point J5 Flows through the scan-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 gradually increases from the voltage of the ground terminal G1.

At the timing T20 of the sustain period, the first transistor switch S1 is turned off while the third transistor switch S3 is turned on.

As a result, in the Y-electrode driving circuit 110, the current i11 is transferred from the power supply terminal VS to the third transistor switch S3, the second connection point J2, the sixth transistor switch S6, and the third connection point. And the fourth connection point J4, the eighth diode D11, and the fifth connection point J5 flow to the scan-electrode of the plasma display panel Cp.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 increases steeply up to the voltage of the power supply terminal VS.

At the timing T21 of the sustain period, the second transistor switch S2 is turned on while the third transistor switch S3 is turned off.

As a result, in the Y-electrode driving circuit 110, the current i4 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, 4th junction J4, 3rd junction J3, 6th transistor switch S6, 2nd junction J2, 1st coil L1, 1st junction J1, and 2nd transistor switch S2 Flows into the first capacitor C1 in the order of.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 gradually decreases from the voltage of the power supply terminal VS.

At the timing T22 of the sustain period, the second transistor switch S2 is turned off while the fourth transistor switch S4 is turned on.

As a result, in the Y-electrode driving circuit 110, the current i6 is transferred from the scan electrode of the plasma display panel Cp to the fifth junction J5, the sixth junction J6, the seventeenth transistor switch S22, Ground through the order of the fourth connection point J4, the third connection point J3, the sixth transistor switch S6, the second connection point J2, the fifth transistor switch S5, and the fourth transistor switch S4. Flow to terminal G1.

Therefore, the voltage applied to the scan electrode of the plasma display panel Cp by the Y-electrode driving circuit 110 is steeply reduced to the voltage of the ground terminal G1.

At the timing T23 of the sustain period, the thirteenth transistor switch S13 is turned off, while the fourteenth transistor switch S14 is turned on.

As a result, in the X-electrode driving circuit 120, the current i7 is transferred from the second capacitor C2 to the fourteenth transistor switch S14, the seventh connection point J7, the second coil L2, and the eighth connection point. J8 and the ninth connection point J9 flow to the common-electrode terminal of the plasma display panel Cp.

Thus, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 gradually increases from the voltage of the ground terminal G2.

At the timing T24 of the sustain period, the twelfth transistor switch S12 is turned on, while the fourteenth transistor switch S14 is turned off.

As a result, in the X-electrode driving circuit 120, the current i8 is transferred from the power supply terminal VS through the order of the twelfth transistor switch S12, the eighth connection point J8, and the ninth connection point J9. It flows to the common-electrode terminal of the plasma display panel Cp.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 increases steeply up to the voltage of the power supply terminal VS.

At the timing T25 of the sustain period, the twelfth transistor switch S12 is turned off while the fourteenth transistor switch S14 is turned on.

As a result, in the X-electrode driving circuit 120, the current i9 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eighth connection point J8, and the second coil L2. , The seventh connection point J7, the fourth diode D4, and the fifteenth transistor switch S15 flow to the second capacitor C2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 gradually decreases from the voltage of the power supply terminal VS.

At the timing T26 of the sustain period, the thirteenth transistor switch S13 is turned on, while the fifteenth transistor switch S15 is turned off.

As a result, in the X-electrode driving circuit 120, the current i10 is transferred from the common-electrode terminal of the plasma display panel Cp to the ninth connection point J9, the eighth connection point J8, and the eleventh transistor switch S11. And the thirteenth transistor switch S13 to the ground terminal G2.

Therefore, the voltage applied to the common electrode of the plasma display panel Cp by the X-electrode driving circuit 120 is steeply reduced to the voltage of the ground terminal G2.

Thereafter, after the operation performed at the timings T18 to T26 is repeatedly performed by the number of sustain-discharge pulses, the operation of the first reset period is restarted.

Among the components of the circuit 100, the fifth transistor switch S5 functions as a cut switch for preventing current from flowing from the ground terminal G1 to the power supply terminal VW having a negative potential.

Similarly, the sixth transistor switch S6 functions as a cut switch for preventing current from flowing from the power supply terminal VP having a voltage higher than the voltage of the power supply terminal VS to the power supply terminal VS.

Similarly, the eleventh transistor switch S11 functions as a cut switch for preventing current from flowing from the ground terminal G2 to the power supply terminal VRST having a negative potential.

The fifth transistor switch S5 is located between the second and third connection points J2 and J3 of the conventional circuit 1000 shown in FIG. 1, while the fifth transistor switch S5 of the first embodiment is shown in FIG. As shown in FIG. 4, it is located between the 2nd connection point J2 and the 4th transistor switch S4.

Specifically, in the first embodiment, when the voltage is applied to the scan electrode through the power supply terminal VS, the fifth transistor switch S5 serving as the first current cut-off element is subjected to the collection circuit 111. When a voltage is applied to the scan electrode, or when the collection circuit 111 collects the voltage from the scan electrode, the current paths through which the currents i11, i1, and i4 flow (ie, the second and third connection points) The holding-clamp circuit 112 of the current path except for the path between J2 and J3.

Thus, in the first embodiment, the currents i11, i1 and i4 do not flow through the fifth transistor switch S5, ensuring that it is possible to reduce power consumption in comparison with the conventional circuit 1000 shown in FIG. 1. do.

The eleventh transistor switch S11 is located between the ninth and eighth connection points J9 and J8 of the conventional circuit 1000 shown in FIG. 1, while the eleventh transistor switch S11 of the first embodiment is shown in FIG. As shown in 4, it is located between the eighth connection point J8 and the thirteenth transistor switch S13.

Specifically, in the first embodiment, when the voltage is applied to the common electrode via the power supply terminal VS, the eleventh transistor switch S11 functioning as the third current cut-off element is connected to the collection circuit 121. When a voltage is applied to the common electrode, or when the collection circuit 121 recovers the voltage from the common electrode, a current path through which the currents i8, i7 and i9 flow (that is, the ninth and eighth connection points J9 and In the holding-clamp circuit 122 of the current path except for the path between J8).

Thus, in the first embodiment, the currents i8, i7 and i9 do not flow through the eleventh transistor switch S11, ensuring that it is possible to reduce power consumption in comparison with the conventional circuit 1000 shown in FIG. 1. do.

According to the first embodiment, the circuit 100 includes a scan-electrode driving circuit 110 for applying a driving voltage to the scan electrode of the plasma display panel Cp. The scan-electrode drive circuit 110 includes a sustain-clamp circuit 112 for applying a sustain-discharge pulse to the scan electrode, and a reset circuit 113 for applying a reset pulse to the scan electrode. The sustain-clamp circuit 112 includes a power supply terminal having a voltage higher than the ground voltage, a third transistor switch S3 capable of electrically connecting the power supply terminal VS to the scan electrode, and a ground terminal G1 having the ground voltage. ), And a fourth transistor switch S4 capable of electrically connecting the ground terminal G1 to the scan electrode. The reset circuit 113 includes a power supply terminal VW having a lower voltage than the ground voltage, and an eighth transistor switch S8 capable of electrically connecting the power supply terminal VW to the scan electrode. The sustain-clamp circuit 112 includes a fifth transistor switch S5 that functions as a first current cut-off element that prevents current from flowing from the ground terminal G1 to the power supply terminal VW. The fifth transistor switch S5 (first current cut-off element) is a holding-clamp circuit of the current path except for the current path through which the current i11 flows when a voltage is applied to the scan electrode through the power supply terminal VS. It is located at (112).

Thus, the current i11 does not flow through the fifth transistor switch S5, making it possible to reduce the power loss due to the current flowing through the fifth transistor switch S5.

According to the first embodiment, the circuit 100 includes a common-electrode driving circuit 120 for applying a driving voltage to the common electrode of the plasma display panel Cp. The common-electrode drive circuit 120 includes a sustain-clamp circuit 122 for applying a sustain-discharge pulse to the common electrode, and a resetability enhancement circuit 124 for applying a pulse to the common electrode to improve reset performance of the common electrode. ). The sustain-clamp circuit 122 includes a power supply terminal VS having a voltage higher than the ground voltage, a twelfth transistor switch S12 capable of electrically connecting the power supply terminal VS to a common electrode, and a ground having a ground voltage. A thirteenth transistor switch S13 capable of electrically connecting the terminal G2 and the ground terminal G2 to the common electrode. The resetability enhancement circuit 124 includes a power supply terminal VRST having a lower voltage than the ground voltage, and a tenth transistor switch S10 capable of electrically connecting the power supply terminal VRST to a common electrode. The sustain-clamp circuit 122 includes an eleventh transistor switch S11 that functions as a third current cut-off element that prevents current from flowing from the ground terminal G2 to the power supply terminal VRST. The eleventh transistor switch S11 (third current cut-off element) is a holding-clamp circuit of the current path except for the current path through which the current i8 flows when voltage is applied to the common electrode via the power supply terminal VS. It is located at 122.

Thus, the current i8 does not flow through the eleventh transistor switch S11, making it possible to reduce the power loss due to the current flowing through the eleventh transistor switch S11.

Second Embodiment

5 is a circuit diagram of the plasma display panel (PDP) driving circuit 200 according to the second embodiment of the present invention.

The circuit 200 according to the second embodiment is structurally different only in the differences mentioned later from the circuit 100 according to the first embodiment. Thus, the same reference numerals are given to the parts or components corresponding to the circuit 100 and operate in the same manner as the corresponding parts or components of the first embodiment unless explicitly stated below.

As shown in FIG. 5, the circuit 200 according to the second embodiment includes the circuit 100 according to the first embodiment only in that it includes the holding-clamp circuit 212 instead of the holding-clamp circuit 112. Structurally different.

Specifically, the sixth transistor switch S6 as part of the holding-clamp circuit 212 of the second embodiment is electrically connected to the source terminal of the third transistor switch S3 without passing through the second connection point J2. It is designed to have a source terminal to be connected and a drain terminal electrically connected to the second connection point J2.

In the circuit 200 according to the second embodiment, the sixth transistor switch S6 functioning as the second current cut-off element is the collection circuit 111 when the scan electrode is electrically connected to the ground terminal G1. When the voltage is applied to the scan electrode, or when the collection circuit 111 recovers the voltage from the scan electrode, the holding-clamp circuit 212 of the current path excluding the current path through which the currents i6, i1, i4 flow. )

Therefore, in the circuit 200 according to the second embodiment, the currents i6, i1 and i4 do not flow through the sixth transistor switch S6, and thus further power than the circuit 100 according to the first embodiment. Makes it possible to reduce the losses.

The circuit 200 according to the second embodiment provides the same advantages as provided by the circuit 100 according to the first embodiment.

In addition, the plasma display panel driving circuit 200 includes a scan-electrode driving circuit 110 for applying a driving voltage to the scan electrode of the plasma display panel Cp. The scan-electrode drive circuit 110 includes a sustain-clamp circuit 212 for applying a sustain-discharge pulse to the scan electrode, and a reset circuit 113 for applying a reset pulse to the scan electrode. The first holding-clamp circuit 212 supplies a power supply terminal VS, a third transistor switch S3 functioning as a first switching element capable of electrically connecting the power supply terminal VS to the scan electrode, and a ground voltage. It has the ground terminal G1 which has. The reset circuit 113 includes a power supply terminal VP having a voltage higher than the voltage of the power supply terminal VS, and a seventh transistor switch S7 capable of electrically connecting the power supply terminal VP to the scan electrode. do. The first holding-clamp circuit 212 includes a sixth transistor switch S6 that functions as a second current cut-off element that prevents current from flowing from the power supply terminal VP to the power supply terminal VS. The sixth transistor switch S6 is located in the holding-clamp circuit 212 of the current path except for the current path through which the current flows when the scan electrode is electrically connected to the ground terminal G1.

Thus, the current i6 does not flow through the sixth transistor switch S6, making it possible to reduce the power loss caused by the current flowing through the sixth transistor switch S6.

[Third Embodiment]

6 is a circuit diagram of a plasma display panel (PDP) driving circuit 300 according to a third embodiment of the present invention.

The circuit 300 according to the third embodiment is structurally different from the circuit 200 according to the second embodiment only in the differences mentioned later. Thus, the same reference numerals are given to the parts or components corresponding to the circuit 200, and operate in the same manner as the corresponding parts or components of the first embodiment unless explicitly described below.

As shown in FIG. 6, the circuit 300 according to the third embodiment includes the holding-clamp circuit 312 instead of the holding-clamp circuit 212. Structurally different from.

In the circuit 300 according to the third embodiment, it functions as a second current cut-off element instead of the sixth transistor switch S6 between the source terminal of the third transistor switch S3 and the second connection point J2. The fifth diode D5 is electrically connected.

Specifically, the fifth diode D5 has an anode terminal electrically connected to the source terminal of the third transistor switch S3, and a cathode terminal electrically connected to the second connection point J2.

Similar to the sixth transistor switch S6 of the second embodiment, the fifth diode D5 prevents current from flowing from the power supply terminal VP to the power supply terminal VS.

The circuit 300 according to the third embodiment provides the same advantages as provided by the circuit 200 according to the second embodiment.

Fourth Embodiment

7 is a circuit diagram of a plasma display panel (PDP) driving circuit 400 according to a fourth embodiment of the present invention.

The circuit 400 according to the fourth embodiment is structurally different only in the differences mentioned later from the circuit 200 according to the second embodiment. Thus, the same reference numerals are given to the parts or components corresponding to the circuit 200, and operate in the same manner as the corresponding parts or components of the first embodiment unless explicitly described below.

 As shown in FIG. 7, the circuit 400 according to the fourth embodiment includes the holding-clamp circuit 412 instead of the holding-clamp circuit 212. ) Is structurally different from

In the circuit 400 according to the fourth embodiment, it functions as a second current cut-off element instead of the fifth transistor switch S5 between the drain terminal of the fourth transistor switch S4 and the second connection point J2. The sixth diode D6 is electrically connected.

Specifically, the sixth diode D6 has a cathode terminal electrically connected to the drain terminal of the fourth transistor switch S4, and an anode terminal electrically connected to the second connection point J2.

Similar to the fifth transistor switch S5 of the second embodiment, the sixth diode D6 prevents current from flowing from the ground terminal G1 to the power supply terminal VW.

The circuit 400 according to the fourth embodiment provides the same advantages as provided by the circuit 200 according to the second embodiment.

[Fifth Embodiment]

8 is a circuit diagram of a plasma display panel (PDP) driving circuit 500 according to a fifth embodiment of the present invention.

The circuit 500 according to the fifth embodiment is structurally different only in the differences mentioned later from the circuit 100 according to the first embodiment. Accordingly, the parts or components corresponding to the circuit 100 are provided with the same reference numerals and operate in the same manner as the corresponding parts or components of the first embodiment unless explicitly explained below.

 As shown in FIG. 8, the circuit 500 according to the fifth embodiment includes the holding-clamp circuit 512 instead of the holding-clamp circuit 112, and accordingly the circuit 100 according to the first embodiment. Structurally different from.

The holding-clamp circuit 512 of the circuit 500 according to the fifth embodiment does not include the sixth transistor switch S6 when compared with the holding-clamp circuit 112 of the circuit 100 according to the first embodiment. Is designed not to. Therefore, the second connection point J2 is electrically connected directly to the third connection point J3.

The power supply terminal VP of the circuit 500 has a lower or equivalent voltage than the voltage of the power supply terminal VS, and therefore, the circuit 500 does not need to include the sixth transistor switch S6.

The circuit 500 according to the fifth embodiment has the same structure as the circuit 100 according to the first embodiment except that the sixth transistor switch S6 is not included. The circuit 500 according to the fifth embodiment provides the same advantages as provided by the circuit 100 according to the first embodiment.

[Sixth Embodiment]

9 is a circuit diagram of a plasma display panel (PDP) driving circuit 600 according to a sixth embodiment of the invention.

The circuit 600 according to the sixth embodiment is structurally different only in the differences mentioned later from the circuit 100 according to the first embodiment. Thus, the same reference numerals are given to the parts or components corresponding to the circuit 100 and operate in the same manner as the corresponding parts or components of the first embodiment unless explicitly stated below.

 As shown in FIG. 9, the circuit 600 according to the sixth embodiment includes the holding-clamp circuit 612 instead of the holding-clamp circuit 112, and accordingly the circuit 100 according to the first embodiment. Structurally different from.

The holding-clamp circuit 612 of the circuit 600 according to the sixth embodiment includes a source terminal electrically connected to a source terminal of the third transistor switch S3 without passing through the second connection point J2, and a second connection point. It is designed to include a sixth transistor switch S6 having a drain terminal electrically connected to J2.

The holding-clamp circuit 612 is designed to further include a fourth transistor switch S4 having a drain terminal electrically connected to the second connection point J2 without passing through the fifth transistor switch S5.

The holding-clamp circuit 612 further includes a fifth transistor switch S5 having a drain terminal electrically connected to the second connection point J2, and a source terminal electrically connected to the third connection point J3.

In the circuit 600 according to the sixth embodiment, the sixth transistor switch S6 functioning as the second cut-off element is the collection circuit 111 when the scan electrode is electrically connected to the ground terminal G1. When the voltage is applied to the scan electrode, or when the collection circuit 111 recovers the voltage from the scan electrode, the holding-clamp circuit 612 of the current path excluding the current path through which the currents i6, i1 and i4 flow. Located in

Thus, in the circuit 600 according to the sixth embodiment, the currents i6, i1 and i4 do not flow through the sixth transistor switch S6, resulting in a power loss compared to the circuit 100 according to the first embodiment. It is possible to further reduce.

However, the fifth transistor switch S5 of the circuit 600 is located similarly to the fifth transistor switch S5 of the conventional circuit 1000 shown in FIG. The position of the fifth transistor switch S5 of the circuit 600 causes slightly greater power loss than that of the first embodiment.

The plasma display panel driving circuit 600 includes a scan-electrode driving circuit 110 for applying a driving voltage to the scan electrode of the plasma display panel Cp. The scan-electrode drive circuit 110 includes a sustain-clamp circuit 612 for applying a sustain-discharge pulse to the scan electrode, and a reset circuit 113 for applying a reset pulse to the scan electrode. The first holding-clamp circuit 612 supplies a power supply terminal VS, a third transistor switch S3 functioning as a first switching element capable of electrically connecting the power supply terminal VS to the scan electrode, and a ground voltage. It has the ground terminal G1 which has. The reset circuit 113 includes a power supply terminal VP having a voltage higher than the voltage of the power supply terminal VS, and a seventh transistor switch S7 capable of electrically connecting the power supply terminal VP to the scan electrode. do. The first holding-clamp circuit 612 includes a sixth transistor switch S6 that functions as a second cut-off element that prevents current from flowing from the power supply terminal VP to the power supply terminal VS. The sixth transistor switch S6 is located in the holding-clamp circuit 612 of the current path except for the current path through which the current flows when the scan electrode is electrically connected to the ground terminal G1.

Thus, the current i6 does not flow through the sixth transistor switch S6, making it possible to reduce the power loss caused by the current flowing through the sixth transistor switch S6.

[Seventh Embodiment]

10 is a circuit diagram of a plasma display panel (PDP) driving circuit 700 according to the seventh embodiment of the present invention.

The circuit 700 according to the seventh embodiment is structurally different only in the differences mentioned later from the circuit 200 according to the second embodiment. Thus, the same reference numerals are given to the parts or components corresponding to the circuit 200, and operate in the same manner as the corresponding parts or components of the first embodiment unless explicitly described below.

 As shown in FIG. 10, the circuit 700 according to the seventh embodiment includes the holding-clamp circuit 712 instead of the holding-clamp circuit 212. Structurally different from.

The holding-clamp circuit 712 of the circuit 700 according to the seventh embodiment does not include the fifth transistor switch S5 when compared with the holding-clamp circuit 212 of the circuit 200 according to the second embodiment. Is designed not to.

Thus, the fourth transistor switch S4 of the sustain-clamp circuit 712 has a drain terminal electrically connected directly to the second connection point J2.

In the circuit 700 according to the seventh embodiment, the power supply terminal VW has a voltage higher than or equal to the voltage of the ground terminal G1, and thus the circuit 700 includes the fifth transistor switch S5. There is no need to do it.

The plasma display panel driving circuit 700 includes a scan-electrode driving circuit 110 for applying a driving voltage to the scan electrode of the plasma display panel Cp. The scan-electrode drive circuit 110 includes a sustain-clamp circuit 712 for applying a sustain-discharge pulse to the scan electrode, and a reset circuit 113 for applying a reset pulse to the scan electrode. The first holding-clamp circuit 712 provides a power supply terminal VS, a third transistor switch S3 functioning as a first switching element capable of electrically connecting the power supply terminal VS to the scan electrode, and a ground voltage. It has the ground terminal G1 which has. The reset circuit 113 includes a power supply terminal VP having a higher voltage than the power supply terminal VS, and a seventh transistor switch S7 capable of electrically connecting the power supply terminal VP to the scan electrode. The first holding-clamp circuit 712 includes a sixth transistor switch S6 that functions as a second current cut-off element that prevents current from flowing from the power supply terminal VP to the power supply terminal VS. The sixth transistor switch S6 is located in the holding-clamp circuit 712 of the current path other than the current path through which the current flows when the scan electrode is electrically connected to the ground terminal G1.

Thus, the current i6 does not flow through the sixth transistor switch S6, making it possible to reduce the power loss caused by the current flowing through the sixth transistor switch S6.

[Eighth Embodiment]

11 is a circuit diagram of a plasma display panel (PDP) driving circuit 800 according to an eighth embodiment of the present invention.

The circuit 800 according to the eighth embodiment is structurally different only in the differences mentioned later from the circuit 100 according to the first embodiment. Thus, the same reference numerals are given to the parts or components corresponding to the circuit 100 and operate in the same manner as the corresponding parts or components of the first embodiment unless explicitly stated below.

 As shown in FIG. 11, the circuit 800 according to the eighth embodiment includes the holding-clamp circuit 822 instead of the holding-clamp circuit 122, and accordingly the circuit 200 according to the second embodiment. Structurally different from.

In the circuit 800 according to the eighth embodiment, the eleventh transistor switch S11 of the sustain-clamp circuit 822 is located between the eighth connection point J8 and the twelfth transistor switch S12.

Specifically, the twelfth transistor switch S12 has a source terminal electrically connected to the source terminal of the eleventh transistor switch S11, and the eleventh transistor switch S11 is electrically connected to the eighth connection point J8. It has a drain terminal.

The thirteenth transistor switch S13 has a drain terminal electrically connected to the eighth connection point J8.

In the circuit 800, the eleventh transistor switch S11 serving as the third current cut-off element prevents current from flowing from the power supply terminal VSW to the power supply terminal VS.

The eleventh transistor switch S11 is located in the holding-clamp circuit 822 of the current path other than the current path through which the current flows when the common electrode is electrically connected to the ground terminal G2.

The Y-electrode driving circuit 110 of the circuit 800 according to the eighth embodiment has the same structure as that of the Y-electrode driving circuit 110 of the circuit 100 according to the first embodiment. The Y-electrode driving circuit 110 of the circuit 800 according to the eighth embodiment has the same structure as that of the Y-electrode driving circuit 110 of any of the second to seventh embodiments.

The circuit 800 includes an X-electrode driving circuit 120 for applying a driving voltage to a common electrode of the plasma display panel, and the X-electrode driving circuit 120 applies a sustain-discharge pulse to the common electrode. Sustain-clamp circuit 822, and sub-voltage application circuit 123 for applying a sub-scan-voltage to the common electrode. The sustain-clamp circuit 822 includes a power supply terminal VS having a voltage higher than the ground voltage, a twelfth transistor switch S12 capable of electrically connecting the power supply terminal VS to a common electrode, and a ground voltage. A ground terminal G2 and a thirteenth transistor switch S13 capable of electrically connecting the ground terminal G2 to the common electrode. The sub-voltage application circuit 123 has a power supply terminal VSW having a voltage higher than that of the power supply terminal VS, and a ninth transistor switch S9 capable of electrically connecting the power supply terminal VSW to a common electrode. ). The second holding-clamp circuit 822 includes an eleventh transistor switch S11 that functions as a third current cut-off element that prevents current from flowing from the power supply terminal VSW to the power supply terminal VS. The eleventh transistor switch S11 is located in the holding-clamp circuit 822 of the current path other than the current path through which the current i10 flows when the common electrode is electrically connected to the ground terminal G2.

Thus, the current i10 does not flow through the eleventh transistor switch S11, making it possible to reduce the power loss caused by the current flowing through the eleventh transistor switch S11.

In the above embodiments, the third current cut-off element is made of the eleventh transistor switch S11. The third current cut-off element may be made of a diode instead of the eleventh transistor switch S11.

In the above-described embodiments except for the third embodiment, the second current cut-off element consists of a sixth transistor switch S6. The second current cut-off element may be made of a diode instead of the sixth transistor switch S6.

In the above-described embodiments except for the fourth embodiment, the first current cut-off element is made of the fifth transistor switch S5. The first current cut-off element may be made of a diode instead of the fifth transistor switch S5.

In the above embodiments, the first to seventeenth transistor switches S1 to S15, S21 and S22 are made of n-type MOSFETs. This may be done with transistors other than n-type MOSFETs. Alternatively, a switch other than the transistor switch may be used instead of the first to seventeenth transistor switches S1 to S15, S21 and S22.

Through the present invention, it is possible to reduce a lot of power loss that occurs when a current caused when a driving voltage is applied to the plasma display panel Cp flows through the components of the plasma display panel Cp driving circuit, and in particular, The power loss caused when the sustain-discharge pulse is applied to the drive circuit can be reduced.

Claims (14)

A plasma display panel driving circuit comprising a scan-electrode driving circuit for applying a driving voltage to a scanning electrode of a plasma display panel, The scan-electrode driving circuit may include a first sustaining-clamp circuit for applying a sustaining-discharge pulse to the scan electrode, and a reset circuit for applying a reset pulse to the scan electrode. Including, The first sustain-clamp circuit includes a first power supply terminal having a voltage higher than a ground voltage, a first switching element capable of electrically connecting the first power supply terminal to the scan electrode, and a first ground having a ground voltage. A terminal and a second switching element capable of electrically connecting the first ground terminal to the scan electrode, The reset circuit includes a second power supply terminal having a lower voltage than the ground voltage, and a third switching element capable of electrically connecting the second power supply terminal to the scan electrode, The first holding-clamp circuit includes a first current cut-off element that prevents current from flowing from the first ground terminal to the second power supply terminal, Wherein the first current cut-off element is located in the first holding-clamp circuit in a current path other than a current path through which current flows when a voltage is applied to the scan electrode through the first power terminal. Panel drive circuit. The method of claim 1, And the first current cut-off element comprises a switching element. The method of claim 1, And the first current cut-off element is made of a diode. The method of claim 1, The reset circuit includes a third power supply terminal having a voltage higher than that of the first power supply terminal, and a fourth switching element capable of electrically connecting the third power supply terminal to the scan electrode, The first holding-clamp circuit includes a second current cut-off element that prevents current from flowing from the third power supply terminal to the first power supply terminal, And said second current cut-off element is located in said first holding-clamp circuit in a current path other than the current path through which current flows when said scan electrode is electrically connected to said first power supply terminal. Circuit. The method of claim 1, The scan-electrode driving circuit further comprises a first collection circuit for applying a voltage to the scan electrode and recovering the voltage from the scan electrode, The reset circuit includes a third power supply terminal having a voltage higher than that of the first power supply terminal, and a fourth switching element capable of electrically connecting the third power supply terminal to the scan electrode, The first holding-clamp circuit includes a second current cut-off element that prevents current from flowing from the third power supply terminal to the first power supply terminal, The second current cut-off element is configured when the first collection circuit applies a voltage to the scan electrode, when the first collection circuit collects a voltage from the scan electrode, or And located in the first holding-clamp circuit in a current path other than the current path through which current flows when the scan electrode is electrically connected to the first power supply terminal. A plasma display panel driving circuit comprising a scan-electrode driving circuit for applying a driving voltage to a scan electrode of a plasma display panel, The scan-electrode driving circuit includes a first sustain-clamp circuit for applying a sustain-discharge pulse to the scan electrode, and a reset circuit for applying a reset pulse to the scan electrode, The first sustain-clamp circuit includes a first power supply terminal, a first switching element capable of electrically connecting the first power supply terminal to the scan electrode, and a first ground terminal having a ground voltage, The reset circuit includes a third power supply terminal having a voltage higher than that of the first power supply terminal, and a fourth switching element capable of electrically connecting the third power supply terminal to the scan electrode, The first holding-clamp circuit includes a second current cut-off element that prevents current from flowing from the third power supply terminal to the first power supply terminal, And said second current cut-off element is located in said first holding-clamp circuit of a current path other than the current path through which current flows when said scan electrode is electrically connected to said first ground terminal. Circuit. The method of claim 6, The scan-electrode driving circuit further comprises a first collection circuit for applying a voltage to the scan electrode and recovering the voltage from the scan electrode, The second current cut-off element is other than a current path through which current flows when the first collection circuit applies a voltage to the scan electrode or when the first collection circuit recovers a voltage from the scan electrode. And located in the first holding-clamp circuit of the current path of the plasma display panel. The method according to any one of claims 4 to 6, And said second current cut-off element comprises a switching element. The method according to any one of claims 4 to 6, And the second current cut-off element is made of a diode. A plasma display panel driving circuit comprising a common-electrode driving circuit for applying a driving voltage to a common electrode of a plasma display panel, The common-electrode driving circuit includes a second sustain-clamp circuit for applying a sustain-discharge pulse to the common electrode, and a resetability improving circuit for applying a pulse to the common electrode to improve reset performance of the common electrode. reset-enhancing circuit), The second holding-clamp circuit includes a fourth power supply terminal having a voltage higher than a ground voltage, a fifth switching element capable of electrically connecting the fourth power supply terminal to the common electrode, and a second ground having a ground voltage. A terminal and a sixth switching element capable of electrically connecting the second ground terminal to the common electrode, The resetability improving circuit includes a fifth power supply terminal having a voltage lower than a ground voltage, and a seventh switching element capable of electrically connecting the fifth power supply terminal to the common electrode, The second holding-clamp circuit includes a third current cut-off element that prevents current from flowing from the second ground terminal to the fifth power supply terminal; Wherein the third current cut-off element is located in the second holding-clamp circuit of a current path other than a current path through which current flows when a voltage is applied to the common electrode through the fourth power supply terminal. Driving circuit. A plasma display panel driving circuit comprising a common-electrode driving circuit for applying a driving voltage to a common electrode of a plasma display panel, The common-electrode driving circuit includes a second sustain-clamp circuit for applying a sustain-discharge pulse to the common electrode, and a sub-voltage application circuit for applying a sub-scan-voltage to the common electrode, The second holding-clamp circuit includes a fourth power supply terminal having a voltage higher than a ground voltage, a fifth switching element capable of electrically connecting the fourth power supply terminal to the common electrode, and a second ground having a ground voltage. A terminal and a sixth switching element capable of electrically connecting the second ground terminal to the common electrode, The sub-voltage application circuit includes a fifth power supply terminal having a voltage higher than that of the fourth power supply terminal, and a sixth switching element capable of electrically connecting the fifth power supply terminal to the common electrode. , The second holding-clamp circuit includes a third current cut-off element that prevents current from flowing from the fifth power supply terminal to the fourth power supply terminal, The third current cut-off element is located in the second holding-clamp circuit of a current path other than a current path through which current flows when the common electrode is electrically connected to the second ground terminal. . The method of claim 10 or 11, The common-electrode driving circuit further includes a second collection circuit for applying a voltage to the common electrode and recovering the voltage from the common electrode, The third current cut-off element is other than a path through which current flows when the second collection circuit applies a voltage to the common electrode or when the second collection circuit recovers a voltage from the common electrode. And a second holding-clamp circuit in the current path. The method of claim 10 or 11, And said third current cut-off element comprises a switching element. The method of claim 10 or 11, And the third current cut-off element is made of a diode.

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